Lecture 21:

RTL Design

CSE 140: Components and Design Techniques for

Digital Systems
Diba Mirza
Dept. of Computer Science and Engineering
University of California, San Diego

Digital Design 2e
Copyright 2010
Frank Vahid

5.1

Combinational design (Logic Level)

Capture Comb. behavior: Equations, truth tables
Convert to circuit: AND + OR + NOT Comb. Logic

Controller Design (Logic Level)

Capture sequential behavior: FSMs
Convert to circuit: Register + Comb. logic Controller

Higher levels

RTL Design
Registertransfer
level (RTL)
Logic level
Transistor level

Levels of digital
Processor Design (Register Transfer Level)
design abstraction
Standard Modules (used in Processor design)
Adders, shifters, counters, decoder, muxs,

Digital Design 2e
Copyright 2010
Frank Vahid

5.1

Processor Design (Register Transfer Level)

Capture behavior: High-level state machine or
pseudocode
Convert to circuit: Controller + Datapath Processor
Known as RTL (register-transfer level) design

Higher levels

RTL Design
Registertransfer
level (RTL)
Logic level
Transistor level

Levels of digital
design abstraction

Processors:
Programmable
(microprocessor)
Custom
Digital Design 2e
Copyright 2010
Frank Vahid

5.2

High-Level State Machines (HLSMs)

Some behaviors too complex for
equations, truth tables, or FSMs
Ex: Soda dispenser
c: bit input, 1 when coin deposited
a: 8-bit input having value of
deposited coin
s: 8-bit input having cost of a soda
d: bit output, processor sets to 1
when total value of deposited coins
equals or exceeds cost of a soda

c
d

Soda
dispenser
processor

0 1 0 1 0
c
d

0 1
Digital Design 2e
Copyright 2010
Frank Vahid

50

a 25

25

Soda tot:
tot:
dispenser
25
processor50

5.2

High-Level State Machines (HLSMs)

Which of the following makes the FSM
design of this problem difficult?
A. 8-bit input/output
B. Tracking the current total
C. All of the above

c
d

Soda
dispenser
processor

0 1 0 1 0
c
d

0 1
Digital Design 2e
Copyright 2010
Frank Vahid

50

a 25

25

Soda tot:
tot:
dispenser
25
processor50

HLSMs

s
8

High-level state machine

(HLSM) extends FSM with:

c
d

Numbers:
Single-bit: '0' (single quotes)
Integer: 0 (no quotes)
Multi-bit: 0000 (double quotes)
a

== for equal, := for assignment

Multi-bit outputs must be
registered via local storage
// precedes a comment
Digital Design 2e
Copyright 2010
Frank Vahid

Soda
dispenser
processor

Multi-bit input/output
Local storage
Arithmetic operations
Conventions

Inputs: c (bit), a (8 bits), s (8 bits)

Outputs: d (bit) // '1' dispenses soda
Local storage: tot (8 bits)
c
Add

Init
d:='0'
tot:=0

Wait

tot:=tot+a
c'*(tot<s)

c*(tot<s)

Disp
SodaDispenser

d:='1'
6

HLSMs

a
8

Q: How does the HLSM differ from the FSM

for this problem?
A.The HLSM requires storing data, but the
FSM doesnt
B.The FSM required storing the state but
the HLSM doesnt
C.Implementing the HLSM requires
registers, registers are not required to
implement the FSM

c
d

Soda
dispenser
processor

Inputs: c (bit), a (8 bits), s (8 bits)

Outputs: d (bit) // '1' dispenses soda
Local storage: tot (8 bits)
c
Add

Init
a

d:='0'
tot:=0

Wait

tot:=tot+a
c'*(tot<s)

c*(tot<s)

Disp
SodaDispenser
Digital Design 2e
Copyright 2010
Frank Vahid

d:='1'
7

HLSMs
Q: Which of the following is common
between HLSMs and FSMs?
A. Transitions happen at the rising
edge of the clock
B. They both have external data
and control inputs and outputs

a
8

c
d

Soda
dispenser
processor

Inputs: c (bit), a (8 bits), s (8 bits)

Outputs: d (bit) // '1' dispenses soda
Local storage: tot (8 bits)
c
Add

Init
a

d:='0'
tot:=0

Wait

tot:=tot+a
c'*(tot<s)

c*(tot<s)

Disp
SodaDispenser
Digital Design 2e
Copyright 2010
Frank Vahid

d:='1'
8

5.3

RTL Design Process

Capture behavior
Convert to circuit
High-level architecture (datapath
and controlpath)
Datapath capable of HLSM's
data operations
Controller to control datapath

Digital Design 2e
Copyright 2010
Frank Vahid

External
control
...
inputs
External ...
control
outputs

DP
control
inputs
...

External data
inputs
...

Datapath

Controller
...
DP
control
outputs

...
External data
outputs

5.3

RTL Design Process

Capture behavior
Convert to circuit
High-level architecture (datapath
and controlpath)
Datapath capable of HLSM's
data operations
Controller to control datapath

Digital Design 2e
Copyright 2010
Frank Vahid

External
control
...
inputs
External ...
control
outputs

DP
control
inputs
...

External data
inputs
...

Datapath

Controller
...
DP
control
outputs

...
External data
outputs

10

Design datapath (2A)

Step 1

Inputs: c (bit), a (8 bits), s (8 bits)

Outputs: d (bit) // '1' dispenses soda
Local storage: tot (8 bits)
c
Init
d:='0'
tot:=0

Wait

Add

tot_ld
tot_clr

ld
clr

tot
a

tot:=tot+a

c'*(tot<s)

c*(tot<s)

Datapath

d:='1'

8-bit
adder

8-bit
<

tot_lt_s

Disp
SodaDispenser

Step 2A

What do we need for DP?

c
tot_ld

tot_clr
Controller
Digital Design 2e
Copyright 2010
Frank Vahid

tot_lt_s

Datapath

Step 2B

11

Design the datapth (2A)

Inputs: c (bit), a (8 bits), s (8 bits)
Outputs: d (bit) // '1' dispenses soda
Local storage: tot (8 bits)
c
Init
d:='0'
tot:=0

Wait

Add

tot_ld
tot_clr

ld
clr

c'*(tot<s)

c*(tot<s)

tot_lt_s

d:='1'

tot

tot:=tot+a

Disp
SodaDispenser

8-bit
<
Datapath

8-bit
adder
8

Step 2A

Q: According to the current design, under which of the following conditions

does the register output tot change?
A.Whenever the value of the coin inserted (a) changes
B.Whenever the cost of the soda (s) changes
C.When the signal tot_ld becomes high
D.When the signal tot_clr becomes high
Digital Design 2e
Copyright 2010
Frank Vahid

12

Connect data path to controller(2B)

s

8
tot_ld
tot_clr

ld
clr

tot_clr
Controller

tot_lt_s

Step 2B

tot

tot_ld

Datapath

tot_lt_s

8-bit
<
Datapath

8-bit
adder
8

Step 2A

Digital Design 2e
Copyright 2010
Frank Vahid

13

Design control path FSM

s

Inputs: c (bit), a (8 bits), s (8 bits)

Outputs: d (bit) // '1' dispenses soda
Local storage: tot (8 bits)

d:='0'
tot:=0

tot_ld

tot_clr

Add

Wait

c
Init

Controller

tot:=tot+a

tot_lt_s

Datapath

Step 2B

c'*(tot<s)

c*(tot<s)

Disp
SodaDispenser

d:='1'

Step 1

Inputs : c, tot_lt_s (bit)

Outputs : d, tot_ld , tot_clr (bit)
c
d

c
Init
d=0
tot_clr=1

Wait

tot_ld
Add

tot_clr

tot_ld=1

tot_lt_s

c' *
c*tot_lt_s
tot_lt_s

Disp
Controller
Digital Design 2e
Copyright 2010
Frank Vahid

d=1

Step 2C

14

Implement controller FSM

Inputs : c, tot_lt_s (bit)
Outputs : d, tot_ld , tot_clr (bit)

Wait

n0

tot_clr

Add

n1

tot_ld

Disp

tot_lt_s

Init

0
0
0
0
1

1
1
1
1
0

0
0
1
1
0

0
1
0
1
0

1
0
1
1
0

1
1
0
0
1

0
0
0
0
0

0
0
0
0
1

0
0
0
0
0

s1

s0

c
Init

Wait

d=0
tot_clr=1

c*
tot_lt_s

Controller

tot_ld
Add

tot_clr

tot_ld=1

tot_lt_s

c*tot_lt_s
Disp
d=1

Step 2C
Use controller (FSM) design
process from previous lectures to
complete the design

a
Digital Design 2e
Copyright 2010
Frank Vahid

15

RTL Design ProcessStep 2A: Create a datapath

Need component library from which to choose

clr I
ld reg
Q

A
B
add
S

A
B
cmp
lt eq gt

I
shift<L/R>
Q

I1 I0
mux2x1
s0 Q

clk^ and clr=1: Q=0

clk^ and ld=1: Q=I
else Q stays same

S = A+B

(unsigned)
A<B: lt=1
A=B: eq=1
A>B: gt=1

shiftL1: <<1
shiftL2: <<2
shiftR1: >>1
...

s0=0: Q=I0
s0=1: Q=I1

Digital Design 2e
Copyright 2010
Frank Vahid

16

Step 2A: Create a DatapathSimple Examples

X

Preg = X + Y + Z

Preg = Preg + X

Preg

Preg

Preg

regQ

(a)
X

(b)

Z
DP

0
1
DP

clr I
ld Preg
Q
P

Digital Design 2e
Copyright 2010
Frank Vahid

A B
add1
S

A
B
add2
S

0 clr I
1 ld Preg
Q

0 clr I
1 ld regQ
Q

A
B
add1
S
0
1

(d)

A
B
add1
S

A
B
add2
S

DP

X+Y
A
B
add2
S
X+Y+Z

(c)

A
B
add1
S

k=0: Preg = Y + Z
k=1: Preg = X + Y
Preg

Preg=X+Y; regQ=Y+Z

clr I
ld Preg
Q

I1 I0
mux2x1
s0 Q

DP

0 clr I
1 ld Preg
Q
P

17

5.4

More RTL Design

Additional datapath components
(signed)
A
B
sub
S
S = A-B
(signed)

Digital Design 2e
Copyright 2010
Frank Vahid

A
B
mul
P

A
abs
Q

P = A*B
Q = |A|
(unsigned) (unsigned)

clr
inc upcnt
Q

clk^ and clr=1: Q=0

clk^ and inc=1: Q=Q+1
else Q stays same

W_d
W_a
clk^ and W_e=1:
W_e
RF[W_a]= W_d
RF R_e=1:
R_a
R_e
R_d = RF[R_a]
R_d

18

Summary
Modern digital design involves creating processor-level components
High-level state machines
RTL design process
1. Capture behavior: Use HLSM
2. Convert to circuit
A. Create datapath B. Connect DP to controller C. Derive controller FSM

Digital Design 2e
Copyright 2010
Frank Vahid

19