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VLSI Testing

Testability
Testability Analysis
Analysis
Virendra Singh
Indian Institute of Science (IISc)
Bangalore
virendra@computer.org
E0-286: Testing and Verification of SoC Design
Lecture - 11
Feb 15, 2008

E0-286@SERC

Controllability
Controllability Examples
Examples

Feb 15, 2008

E0-286@SERC

Controllability
Controllability Examples
Examples

Feb 15, 2008

E0-286@SERC

Observability
Observability Examples
Examples
To observe a gate input:
Observe output and make other input values non-controlling

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Observability
Observability Examples
Examples
To observe a fanout stem:
Observe it through branch with best observability

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Levelization
Levelization Algorithm
Algorithm
Label each gate with max # of logic levels from

primary inputs or with max # of logic levels from


primary output
Assign level # 0 to all primary inputs (PIs)
For each PI fanout:
Label that line with the PI level number, &
Queue logic gate driven by that fanout
While queue is not empty:
Dequeue next logic gate
If all gate inputs have level #s, label the gate
with the maximum of them + 1;
Else, requeue the gate
Feb 15, 2008

E0-286@SERC

Controllability
Controllability -- Level
Level 0
0
Circled numbers give level number. (CC0, CC1)

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Controllability
Controllability -- Level
Level 2
2

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Combinational
Combinational Controllability
Controllability

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Observability
Observability for
for Level
Level 1
1
Number in square box is level from primary outputs (POs).
(CC0, CC1) CO

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Observabilities
Observabilities -- Level
Level 2
2

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Example
Example (PODEM)
(PODEM)

Select path s Y for fault propagation

sa1

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Example
Example --- Step
Step 2
2 ss sa1
sa1

Initial objective: Set r to 1 to sensitize fault

sa1

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Example
Example --- Step
Step 3
3 ss sa1
sa1

Backtrace from r

sa1

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Example
Example --- Step
Step 4
4 ss sa1
sa1

Set A = 0 in implication stack

1
0
sa1

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Example
Example --- Step
Step 5
5 ss sa1
sa1

Forward implications: d = 0, X = 1

1
0

0
sa1

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E0-286@SERC

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Example
Example --- Step
Step 6
6 ss sa1
sa1

Initial objective: set r to 1

1
0

0
sa1

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Example
Example --- Step
Step 7
7 ss sa1
sa1

Backtrace from r again

1
0

0
sa1

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Example
Example --- Step
Step 8
8 ss sa1
sa1

Set B to 1. Implications in stack: A = 0, B = 1

1
0
1

Feb 15, 2008

0
sa1

E0-286@SERC

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Example
Example --- Step
Step 9
9 ss sa1
sa1

Forward implications: k = 1, m = 0, r = 1, q = 1,
Y = 1, s = D, u = D, v = D, Z = 1
1
1
0
0

1
1

sa1

D
1
D

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Backtrack
Backtrack --- Step
Step 10
10 ss sa1
sa1

X-PATH-CHECK shows paths s Y and


Z blocked (D-frontier disappeared)

1
0

suv

0
sa1

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E0-286@SERC

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Step
Step 11
11 --- ss sa1
sa1

Set B = 0 (alternate assignment)

1
0
0

Feb 15, 2008

sa1

E0-286@SERC

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Backtrack
Backtrack --- ss sa1
sa1

Forward implications: d = 0, X = 1, m = 1, r = 0,
s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.

0
0
0

0
1

sa1

0
1
0

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E0-286@SERC

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Step
Step 13
13 --- ss sa1
sa1

Set A = 1 (alternate assignment)

1
1
sa1

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E0-286@SERC

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Step
Step 14
14 --- ss sa1
sa1

Backtrace from r again

1
1
sa1

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E0-286@SERC

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Step
Step 15
15 --- ss sa1
sa1

Set B = 0. Implications in stack: A = 1, B = 0

1
1
0

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sa1

E0-286@SERC

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Backtrack
Backtrack --- ss sa1
sa1

Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict:


fault not sensitized. Backtrack

0
1
0

0
1

sa1

0
1
0

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Step
Step 17
17 --- ss sa1
sa1

Set B = 1 (alternate assignment)

1
1
1

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sa1

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Fault
Fault Tested
Tested -- Step
Step 18
18

d = 1, m = 1, r = 1, q = 0, s = D, v =

Forward implications:
D, X = 0, Y = D

1
1

1
1
1

sa1

0
D

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Example
Example (D-Algo)
(D-Algo)

Primitive D-cube of Failure

sa1

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Example
Example Step
Step 2
2

Propagation D-cube for v


1

sa1
0

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Example
Example Step
Step 2
2
Forward & Backward Implications

1
1

1
1

sa1
0

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Example
Example Step
Step 3
3 ss sa1
sa1

Propagation D-cube for Z test found!


0

1
1

1
1

sa1
0

1
Feb 15, 2008

E0-286@SERC

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Thank You
Feb 15, 2008

E0-286@SERC

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