III.

VLSI
Matthias Bucher




2014

Bucher electronics.tuc.gr
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Silicon wafers

Figure A.1 Silicon ingot and wafer slices.

Packaging

Figure A.2 (a) An 8-pin plastic dual-in-line IC package, (b) A 16-pin surface mount package.

Fabrication process (i)

(a) Define n-well diffusion (mask #1)

(c) LOCOS oxidation

(b) Define active regions (mask #2)

(d) Polysilicon gate (mask #3)

Figure A.3 A typical n-well CMOS process flow.

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Fabrication process (ii)

(e) n+ diffusion (mask #4)

(g) Contact holes (mask #6)

(f) p+ diffusion (mask #5)

(h) Metallization (mask #7)

Figure A.3 A typical n-well CMOS process flow.

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NMOS and PMOS cross-section

Figure A.4 Cross-sectional diagram of an n- and p-MOSFET.

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pn Junction

Figure A.7 A pn junction diode in an n-well CMOS process.

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Lateral npn Transistor

Figure A.9 A lateral pnp transistor.

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SiGe Heterojunction Bipolar Transistor (HBT)

Figure A.11 Cross-sectional diagram of a symmetrical self-aligned npn SiGe heterojunction bipolar transistor (HBT).

Resistors (i)

Figure A.5 Cross sections of resistors of various types available from a typical n-well CMOS process.
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Resistors (ii)

Figure A.10 p-Base and pinched p-base resistors.

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MIM and MOSVAR capacitors

Figure A.6 Interpoly and MOS capacitors in an n-well CMOS process.

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BiCMOS cross section

Figure A.8 Cross-sectional diagram of a BiCMOS process.

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CMOS inverter cross-section

Figure A.13 Cross section along the plane AA of a CMOS inverter.

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CMOS inverter layout

Figure A.12 A CMOS inverter schematic and its layout.

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Figure A.14 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate: (a), (d),
(e), and (f) dark-field masks; (b), (c), and (g) clear-field masks.
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