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    micro controladores y mocroprocesadores

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    17 просмотров16 страниц

    Datasheet 8085A

    Загружено:

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    micro controladores y mocroprocesadores

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    © All Rights Reserved
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    8085A/8085A-2 SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSORS = Single +5V Power Supply = Four Vectored Interrupt Inputs (One is = 100% Software Compatible with 8080A en pis an Cok = 1.3 us Instruction Cycle (8085A); ‘ompatibie Interrupt 0.8 us (8085A-2) = Serial In/Serial Out Port = On-Chip Clock Generator (with External _ Crystal, LC or RC Network) . ain eeusaa and Double Precision = On-Chip System Controller; Advanced Cycle Status Information Available for = Direct Addressing Capability to 64k Large System Control Bytes of Memory The intel® 8085A is a complete 8 bit parallel Central Processing Unit (CPU). Its instruction sets 100% software compatible with the 8080A microprocessor, and itis designed to improve the present 8080A's performance by higher system speed. Its high level of system integration allows a minimum system of three IC's [B085A (CPU), 8156 (RAM/1O} and6355/8755A, [ROM/PROM/0}] while maintaining total system expandabilty. The BOBSA-2 Is a faster version of the BOB5A, ‘The 8085A incorporat ofthe features that the 6224 (clock generator) and 8228 (system controller) provided for the high level of system integration. .ddress is split between the 8 bit address bus and the & bit data bus. The ‘on-chip address latches of 8155/8156/8355/8755A memory products allow a direct intertace with the BOB5A, __ Figure 2. 8085A Pin Figure 1. 6085A CPU Functional Block Diagram ‘Configuration 610 powers 8085A/8085A-2 Table 1. Pin Description Symbol [Type ‘ame ad Funetion ‘Symbol Wee ‘Wame and Function Aehts ° ‘during RESET. 4 ‘Adress Bus: The most significant {bite of the memory address or the 8 bits of the UO address, Stated uring Hold and Halt modes and READY Wultiplexed Addross/Data Buc Lower 8 bits ofthe memory address (or VO address) appear on the Dus suring the fet clock cycle (Teta) fof amachine eel. t then becomes ‘tho data bus during the second and third clock cycles. 1 Ready: 1 READY is high during a read of writ cyte it indicates that the memory or peripheralisready to ‘20nd oF receive data I READY ie Tow, the cpu will wait an intogral ‘umber of clock eyeles for READY to go high botore completing the ead or write cycle. READY must Conform to specified etupand holt times (HOLD NE ° “Address Latch Enable ‘uring the fst clock stato of ama- chine cycloand enabies theadress te getiatched ito t of periphoras. The fang edge of [ALE is sotto guarantee setup and hho tines forthe acaross informa tion. The fang edge of ALE can ‘also be used to strobe the status information, ALE is never @-stated nvchip latch 0.81, andiony 0 Machine Cycle Status: 8 Status tom 8; ° x x * = stato (high impedance) X= unspecified 1 can be used ae an advanced RAW satus. 1O/M, Sp and S; become ‘alld ai the bogianing of a machine Cycle and remain stable throughout tho cycle, The falling edge of ALE may be used to latch the state of thate kes, ° x x Momory write Momory read vo write WO read Opcode fetch Opeode tater Interrupt Acknowledge Hatt Hold Reset Hold Indices that another mesior Is requesting the uso ofthe address fand data buses, The cpu, upon receiving the hold request, will Felingulsh the use of tho bus as '800n a8 the completion of the cur rent bus transfer Internal process ing can continue. The processor Coan regain the bus only ator the HOLD te removed. When the HOLD is acknowledged, the Address, Data FD, WA, and IMM tines are Stated. HLA Hold Acknowledge: indicates that the epu has recaived the HOLD ro- (quest and that it wil oinquish the Bus In the next clock cya. HLDA 088 low after the Hold request is Temoved. The cpu takes thebus one half clock cycle after HLDA goes tov NTR Read Control: A low jovel on AB Indicates the selected memory oF WO device ie tobe aad and that tho Data Bus is avaliable for the dat transfer, S-tated during Hold and Halt modes snd during RESET. Interrupt Request: used as @ general purpose interrupt. It is ‘Sampled only during the next tothe last clock cycle of an instruction ‘and during Hold and Hel states it Js activa, the Program Counter (PC) ‘wil be inhibited from Inerementing land an INTA wil be issued. During this cycle a RESTART of CALL ine struction can be Ingorted tojump to the intorupt service routine. The INTR is enabled anc labled by software. tie disabled by Reset and Immediately ater an interupt ac cepted. ‘Wate Control: A low level on WAL Indicates the dataon the Data Susie to be written Into the selected ‘memory oF 0 location. Datals set ling edge of WR. 3- Stated during Hold and Halt modes tp at the land during RESET. Taterupt Acknowledge: lsusedin- stead of (and has the same ting 23) RD curing the Instruction cycle ator an INTA ls aocopted. It can be {Used to activa an 82594 Intorupt chip or some other interupt port. ners RST 6S RST 75 Restart interrupta: These three in puts have the same timing as INTL except they cause an internal RESTART to be automatically insorted, “The priory of these intorupte Ie ‘ordered as shown in Table 2. Theee Interrupts have 8 higher priority than INTR. tn alton, they may Be individual matkes out Using the SIM Instruction. ett intel 8085A/8085A-2 Table 1. Pin Description (Continued) ‘Symbol - ‘Tyee ‘Name and Function ‘Symbol Tyee ‘Name and Function TRAP ' Trap interrupt ie a non- Reset out | 0 | Resetout: Reset Outindicates cpu rmaskable RESTART intorrupt, Its Doing reset. Can be used ‘ecognizea at the same time a a a eysiom resot. The signal Is INTRorRSTS5-7.5. Ite unetfectes synchronized to the processor by any mask oF interrupt Enable clock and lasts an intogral number has the highest prot of any itor. of clock periods. pt (S20 Table 2) XX T [iG and xg: Are connected to & TRESETIN | 1 | Rost in: Sets the Program Goun- crystal, LC, or RC network to drive ter to zar0 and resets the Interrupt the internal clock gonarator.X; can Enable and HLDA flip-iops. The algo be an external clock input rom data and adcrese buses and the ‘logle gate The Input frequoncy Is ‘contro ines are $-stated during ‘vided by 2 to give the processar's RESET and because of the Internal operating frequency. asynchronous nature of RESET, the rg 5 Ghee Cock outpatoruneas any processors Internal registers and fiags may be altered by RESET with unpredictable results. AESETINisa tem clock. The perlod of CLIC Is twice the X,, Xp Input periog. | ‘Schmitttriggered input, allowing a0 1] Seria nput Bata Line: The deta on connection to an R-C network for {Ws ine loaded Into accumulator | power-on RESET delay. The cpu is Dit whenever @ RIM instruction Is held in the raset condition 88 Tong srecuted. as RESET W is applies, 's00 (© | Sertat Output Data Line: The out. PULSOD is et or rosot as epecilog bythe SIM instruction. Ves Power: +5 vot supply Ves Ground: Reference Table 2. interrupt Priority, Restart Address, and Sensitivity ‘Address Branched To (1) Name | Prlority | When Interrupt Occurs ‘Type Trigger TRAP, 1 2H Rising edge AND high level unt RST TS 2 SCH Rising edge (latched), RST 6S 3 34H High level untii sampled. FSTS5, 4 20H High level until sampled. INTR 3 See Note (2) High level until sampled. Notes: 1. The procestor pushes the PC on the stack before branching to the indletad adress. 2. The address branched fo depends onthe instruction provided to the cpu when the Interupt is acknowledge. e12 pena intel FUNCTIONAL DESCRIPTION ‘The 8086A is a complete 8-bit parallel central processor. Itie designed with N-channel depletion loads and requires 1 single +5 volt supply. Its basic clock speed is 3 MHz (8085A) or 5 MHz (8085A-2), thusimprovingon thepresent ‘8060A's performance with higher system speed. Also itis. designed to fit into a minimum system of three IC's: The {pu (8085A), @ RAM/IO (8156), and a ROM or EPROM/IO, chip (8356 oF 87554), ‘The 8085A has twelve addressable 6-it registers. Fourof thom can function only as two 16-bit register pairs. Six others can be used interchangeably as &-bit registers or as 16-bit register pairs. The B085A register setisas follows: Mnemonic — Reglater Contents ACGorA Accumulator bits Po Program Counter —_16-bitaddress BO,DEHL General-Purpose bits x6 or Registers; data 16 bits x3 pointer (HL) SP Stack Pointer 16-bit address FlagsorF Flag Register Stags (8-bitspace) ‘The 8085A uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus and the lower B-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent ‘out on the Addrass/Data bus, These lower 8 bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycte the data bus is Used for memory or /0 data. ‘The 8085A provides FD, WR, So, S,, and IO/M signals for bus control. An Interrupt Acknowledge signal (INTA) is, ‘algo provided. HOLD and all Interrupts are synchronized with the processor's internal clock. The 085A also pro- vides Serial Input Data (SID) and Serial Output Data (80D) lines for simple serial interface. {In adsition to these features, the 8O85A has three mask able, vector interrupt pins and one nonmaskable TRAP Interrupt. INTERRUPT AND SERIAL 1/0. ‘The 6085A has 5 interrupt inputs: INTA, RST 5.5, RST6.S, RST 7.5, and TRAP. INTR is identical in function to the 080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP Is also @ RESTART interrupt but itis nonmaskable. The three maskable interrupts cause the Intern ‘execution of RESTART (saving the program counter in the ck and branching to the RESTART addross) if tho inter- rupts are enabled and Ifthe interrupt mask is not set. The ‘non-maskable TRAP causes the Internal execution of a RESTART vector independent of the state of the interrupt tenable or masks. (See Tablo 2) ‘There are two different types of inputs inthe restart inter- rupts. AST 5.5 and RST 6.5 are high lovol-sensitive like INTR (and INT on the 8080) and are recognized with the ‘same timing as INTA. RST 75 is rising edgo-sensitive. For RST 75, only a pulse Is required to set an internal flip-flop which generates the internal interrupt request. (See Section 52,7.) The RST 7.5 request flip-tlop remains ‘8085A/8085A-2 set until the request is serviced. Then it is reset auto- matically. This flip-lop may also be reset by using the SIM instruction or by issuing a RESET IN to the 8085A. ‘The RST 7.5 internal flip-lop will bo set by @ pulse on the ST 7.5pin even when theRST 7.5 interruptis masked out ‘The status of the three AST Interrupt masks can only be affected by the SIM instruction and RESET IN. (See SIM, Chapter 5. “The interrupts are arcanged in a fixed priority that deter- mines which interrupt is to be recognized if more than ‘one is pending as follows: TRAP — highest priority RST 75, RST 65, AST 55, INTR — lowest priorty. This priority scheme does not take into account the priority fof a routine that was started by a higher priority interrupt RST 55 can interrupt an AST 7.5 routine ifthe interrupts are re-enabled betore the end of the RST 7.5 routine. ‘The TRAP interrupt is useful for catastrophic events such fas power failure or bus error. The TRAP input is recog rized Just as any other interrupt but has the highest priority. Its not affected by any flag or mask. The TRAP input is both adge and level sensitive. The TRAP Input ‘must go high and remain high until it is acknowledged. Iwill not be recognized again until it oes tow, then high ‘again. This avoids any false triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the B085A, Note thatthe servicing of any interrupt (TRAP. AST 7.5, RST 8.5. ASTS.5. INTA) isables all future interrupts (except TRAPS) until an El Instruction is executed Do Figure 3. TRAP and RESET IN Circult ‘The TRAP interrupt s special in that it disables interrupts, but preserves the previous interrupt enable status. Per- {orming the first RIM instruction following a TRAP inter- fupt allows you to determine whether interrupts were tnabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM Instruction following INTR, or RST 55-75 will provide current Interrupt Enable status, revealing that Interrupts are disabled. See the descrip- ton of the RIM instruction in Chapter 5. “The serial /O system is also controlled by the RIM and SIM instructions, SID is read by RIM, and SIM sets the SOD data DRIVING THE X1 AND X2 INPUTS You may drive the clock inputs of the 80BSA or 8085A-2 with a crystal, an LC tuned circuit, an AC network, or an ‘external clock source. The driving frequency must be at least 1 MHz, and must be twice the desired internal clock frequency; hence, the 8085A is operated with a 8 MHz crystal for 3MHz clock), and the 8085A-2.can be operated with @ 10 MHz crystal (for § MHz clock), Ia crystalis used, it must have the following characteristics: Parallel resonance at twice the clock frequency desired C1 {load capacitance) = 90 pt Gs (shunt capacitance) 7 pt Re (equivalent shunt resistance) < 75 Ohms Drive level: 10 mW Frequency tolerance: +.006% (suggested) Note the use of tho 20pF capacitor between X- and ground, This capacitor is required with crystal frequencies below 4MH2 to assure oscillator startup at the correct frequency. A parallel‘esonant LC circuit may be used as the frequency-determining network for the 8085A, providing that its frequency tolerance of approximately =10% is acceptable. The components fre chosen from the formula: 1 Be JUiCon* Cin 8085A/8085A-2 To minimize variations in frequency, itis recommended that you choose a value for Cex that is atleast twice that Of Cig, oF 80 pF. The use of an LC circuit is not recom ‘mended for frequencies higher than approximately SMMz, ‘An RC circuit may be used as the requency-determining ‘etwork for the 8085A if maintaining a precise clock tre quency is of no importance. Variations in the on-chip timing generation can cause awide variation in frequency ‘when using the RC mode. Its advantage is its low com- Ponent cost. The driving frequency generated by the Circult shown is approximately 3 MHz. It is not recom- ‘mended that frequencies greatly higher or lower than this be attempted Figure 4 shows the recommended clock driver circuits Noten D and that pullup resistors are required to assure that the high level voltage of the input is atleast 4 V. For driving frequencies up to and including 6 MHz you ‘may supply the driving signal to X1 and leave Xe open- circuited (Figue 40). f the driving frequency is rom MHz to 10 Miz, stabity of the clock generator willbe improved by driving both X; and Xz with a push-pull source (Figure 4£), To pravent self-oscillation of the B085A, be sure th Xz Is not coupled back to Xi through the driving circuit. m . Quartz Crystal Clock Driver ¢. RC Clreult Clock Driver . 1-6 MHz Input Frequency Driver Circult External Clock a . 1-10 MHz Input Frequency External Clock Driver Circult Figure 4, Clock Driver Circuits eta arwarean intel GENERATING AN 8085A WAIT STATE Figure § may be used to insert one WAIT state in 6 8085A machine eycle ‘The D flip-flops should be chosen so that *# CLK is rising edge-triggerad * CLEAR is low-level active Figure 5. Generation of a Walt State for 80854 cPU {As in the 8060, the READY line is used to oxtend the road {and write pulse lengths so that the 885A can beused with slow memory. HOLD causes the cpu to relinquish the bus ‘when itis through with it by floating the Address and Data Bus SYSTEM INTERFACE ‘The 8085A family includes memory components, which are directly compatible to the 8085A cpu. For example, a system consisting of the three chips, 8085A, 8158, and 18355 will have the following features: 2k Bytes ROM 256 Bytes RAM 1 Timer/Counter 4 bit /0 Ports 1 6:bit 1/0 Port 4 Interrupt Levels ‘This minimum system, using the standard /O technique Is as shown in Figure 6 {In addition to standard V/O, the memory mapped 1/0 offers an efficient 0 addressing technique. With thi technique, an area of memory address space is essigned {or 1/0 address, thereby, using the memory address for VO manipulation. Figure 7 shows the system contigura- tion of Memory Mapped 1/0 using B0B5A. 808 /8085A. 615 ‘The 8085A cpu can also interface with the standard ‘memory that does not have the multiplexed adéress/ci ‘bus. It will require a simple 8212 (8-bit latch) as shown Figure 8. + Figure 6. 8085A Minimum System (Standard VO Technique) intel 8085A/8085A-2 oe ce a 2 bo 186 IRAM + 1/0 + COUNTER/TIMER} 8355 [ROM +1/0} OR {87554 [PROM+ V0} Figure 7, MCS-85™ Minimum Syatem (Memory Mapped /0) hata Px oon ‘rs Figure &. MCS-85™ System (Using Standard Memorles) 616 senor intel 8085A/8085A-2 BASIC SYSTEM TIMING ‘Table 3. 8085A Machine Cycle Chart ‘The 6085A has # multiplexed Date Bus. ALE is usedasa — [cowncoveue ay a0) strobe to sample the lower bits of address on the Data ro [=o [68 Bus. Figure 8 shows an instruction fetch, memory read [OROBEFETOR (OH ereyared ays ‘and 1/0 write cycle (as would occur during processing of | |meyonvimire. tn) Ue eee the OUT instruction). Note that during he 1/0 write and |tomena"”" fom + [sepa] st ‘ead cycle that the /O port address scopiedon boththe — |Ownite wom Votes] ofa Upper and lower half of the address acorcmeoce yee ‘There are seven possibletypes of machine cycles, Which | BUSIDLE ta oan ofifola yi mn takes place Ie defined by the status ofthe wooo TL, lines (10/M, Sy, So) and the three control WALT ws} 0] ofrs| rs] signals (FD, WR, and INTA). (See Table 3.) The status lines can be used as advanced controle (for device selec- tion, for example), since they become active at the Ts sate, at the outset of each machine cycle. Control ines RD and WR become active later, at the time when the transfer of data isto take place, so are used as command lines. fh x vito e ‘A machine cycle normally consists of three T states, with In |x fx | x x|xla the exception of OPCODE FETCH, which normally has Jr |x fx | x | x | x | xf e either four or six T states (unless WAIT or HOLD states ts | xix |x| x |x} xto are forced by the receipt of READY or HOLD inputs). Any Ju fafotx | we fa late state must be one often possible states, shown in Tablo4, wm jtfel|x|w | alate twer | oj ts| ts | is | we] | 0 seta) mamoronoenasonems |X eer [Xenon IS In rn LTS i er ee pL sew [Xamon Xo Xe 7 Figure 9. 8085A Basic System Timing 617 arwovaean intel ABSOLUTE MAXIMUM RATINGS ocr 70°C “65°C to +150°C ‘Ambient Temperature Under Bat, Storage Temperature Voltage on Any Pin With Respect to Ground Power Dissipation ~0.5V 10470 1.5 Watt D.C. CHARACTERISTICS (Tq ~ 0°C to 70°C, Voc = ov 8085A/8085A-2 “NOTICE: Strossos above those listed under “Absolute Maximum Ratings” may cause permanent damage to the ovice. This is @ stress rating only and functional opers- tion of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absoluta ‘maximum rating conditions for extended periods may affect device rolabilty. '=5%, Vg = OV; unless otherwise specified) ‘Symbot Parameter Min, Max. [Unite “Tost Conditions Vie Input Low Vohage “08 408 v Vin Input High Voltage 20 | Vocws | Vv Vou (Output Low Voltage 0.45 v Vou. ‘Output High Voltage 24 v lee. Power Supply Current 170 mA Ui Taput Leakage 310 A = Viv

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