library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LAB3 is port (
CLOCK_50 : in std_logic;
KEY: in std_LOGIC_VECTOR(3 downto 0);
SW : in std_logic_vector(9 downto 0);
HEX3,HEX2,HEX1,HEX0 : out std_logic_vector(6 downto 0));
End lab3;
architecture topLevel of LAB3 is
signal next_count,current_count: integer range 0 to 50000000;
signal en,en1: std_logic;
signal d:integer:=0;
begin
en<='1' when current_count =1 else '0';
process(clock_50,next_count)
begin
if clock_50='1' and clock_50'event then -- at raising edge of clock
current_count<=current_count +1;-- current count used for delay
if (current_count = 5000000) then-- 5000000 count used as it represents 0.1 sec
in a 50Mhz clock
current_count<= 0;
end if;
end if;
if (rising_edge(en)) then
if(KEY(0)='1') then
d<=d+1;
-- variable D add's up everytime the enable reaches high
if(d>11) then
d<=0;
end if;
IF (KEY(0)='0')
THEN
next_count<= current_count;
END IF;
end if;
end if;
end process;
with d select
hex0<="1111001" when 0,
"0111111" when 1,
"1110110" when 9,
"1111111" when others;
with d select
hex1<="0111111" when 2,
"1110110" when 7,
"1110110" when 8,
"1111111" when others;
with d select
hex2<="0111111" when 3,
"1111111" when others;
with d select
hex3<="0111111" when 4,
"1001111" when 5,
"1110110" when 6,
"1111111" when others;
end topLevel;