I HC QUC GIA THNH PH H CH MINH

TRNG I HC BCH KHOA

KHOA KHOA HC - K THUT MY TNH

N THIT K LUN L
Bo co tun 1

Tip cn ti

Lp:
SVTH:

MT13KTTN
Phm Trung Kin
Hunh Quang Phng
ng Quc Sn

- 51301941
- 51303097
- 51303399

TP. H CH MINH, THNG 9/2015

Trng i Hc Bch Khoa Tp.H Ch Minh

Khoa Khoa Hc v K Thut My Tnh

Mc lc
1 Ni dung yu cu tun 1

2 Kt qu t c
2.1 Tm hiu board DE2i 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Tm hiu Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2
2
2

3 M hnh cc module ca my tnh b ti

3.1 Chc nng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 D liu vo ra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3
3
4

4 Phn cng cng vic

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Trng i Hc Bch Khoa Tp.H Ch Minh

Khoa Khoa Hc v K Thut My Tnh

Ni dung ti:
Yu cu:

Xy dng my tnh b ti n gin bng verilog HDL trn board DE2i 150.

Thc hin php tnh cng tr nhn chia s nguyn 8 k s.

Hin th trn LCD.

Ni dung yu cu tun 1

- Tm hiu cu to tnh nng ca board DE2i 150.

- Tm hiu li cch m t phn cng trn Behavioral level.
- Phc tho s b cc module cn c ca my tnh b ti.

Kt qu t c

2.1

Tm hiu board DE2i 150

Board DE2i-150 l board mch phc v cho vic nghin cu v pht trin v cc lnh vc lun l s hc (digital
logic), t chc my tnh (computer organization) v FPGA.
Board DE2i-150 cung cp kh nhiu tnh nng h tr cho vic nghin cu v pht trin, di y l mt s
thng tin ca board DE2i 150:
Cc thit b xut nhp:
- USB Blaster cho lp trnh v iu khin API ca ngi dng; h tr c 2 ch lp trnh JTAG v AS.
- B iu khin Cng 10/100/1000 Mbps Ethernet.
- Cng HSMC (High Speed Mezzanine Card).
- Cng VGA-out.
- B gii m TV v cng ni TV-in.
- B iu khin USB Host/Slave vi cng USB kiu A v kiu B.
- Cng ni PS/2 chut/bn phm.
- B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm line-in, line-out, v microphone.
- 2 Header m rng 40-pin vi lp bo v diode.
- Cng giao tip RS-232 v cng ni 9-pin.
- Cng giao tip hng ngoi.
B nh:
- 128 MB SDRAM
- 4 MB SSRAM
- 64 MB Flash
Switch, cc n led, LCD, xung clock:
- 4 nt nhn, 18 nt gt.
- 18 LED , 9 LED xanh, 8 Led 7 on
- LCD 16x2
- B dao ng 50-MHz.

2.2

Tm hiu Verilog HDL

Verilog va l mt ngn ng hnh vi va l mt ngn ng cu trc. Trong mi module chng ta c th s dng 4

mc tru tng ha ty thuc vo mc ch thit k. Cc level c nh ngha nh sau:[Palnitkar(February 21, 2003)]
Behavioral or algorithmic level
y l m hnh tru tng ha cao nht c cung cp bi verilog HDL. Thit k level ny tng t
nh lp trnh vi ngn ng C.
Dataflow level
Trong lp ny cc module c thit k bng cch xc nh r lung d liu. Cc nh thit k xc nh
d liu c flow nh th no trong cc thanh ghi v d liu c x l nh th no.

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Trng i Hc Bch Khoa Tp.H Ch Minh

Khoa Khoa Hc v K Thut My Tnh

Gate level
lp ny cc module c thit k bng cc cng logic.
Switch level
lp ny cc module c thit k bng cc transistor.
Chng ti s hon thnh n trn Behavioral level.

M hnh cc module ca my tnh b ti

Hnh 1: S h thng my tnh b ti

3.1

Chc nng

MEM:
Nhn d liu u vo n nh d liu trong cc thanh ghi.
Truyn d liu nhn c vo khi CTRL a vo ALU x l v hin th trn LCD
CTRL: iu khin ton b h thng
Nhn d liu t MEM truyn cho ALU tnh ton.
Nhn kt qu tr v t ALU hin th ln LCD.
iu khin LCD.
Ton b h thng s nhn 1 clock ng b d tnh 1MHz.

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Trng i Hc Bch Khoa Tp.H Ch Minh

Khoa Khoa Hc v K Thut My Tnh

3.2

D liu vo ra

INPUT: s s dng 2 key nhp cc s hng tnh ton, 1 key chn php tnh v 1 key hin th kt
qu.
OUTPUT: hin th cc d liu nhp v kt qu tc th ln LCD.

Phn cng cng vic

....

Ti liu
[de2()] DE2i-150_FPGA_System_manual.
[Cng()] Phm Quc Cng. Thit k vi mch s dng hdl. Chapter 4, 5.
[Palnitkar(February 21, 2003)] Samir Palnitkar. Verilog HDL: A Guide to Digital Design and Synthesis. Prentice Hall PTR, February 21, 2003.

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