Design Flow in VHDL

In VHDL design flow is composed of 3 steps:

1. Coding
2. Simulation
3. Synthesis
Coding: The phase in which VHDL code is written.
Simulation: In this phase the prepared VHDL code is tested before downloading to the
FPGA.By simulation possible errors are minimized.
Synthesis: In this phase, the VHDL code is translated to hardware, i.e. converted to RTL.
This process is carried on by the synthesizers.