Assignment-3

1) Find the a.c incremental current Iout flowing from node A to ground when
=0 and 0.
(Assuming all devices are equal in size and the tail current source is Ideal)
Sol:

Q.3 In Fig.3, VDD = 1.8, RD= 2K. Initially it was designed for a gain of 4 (Pick
your own 130nm technology file and get gain of 4). Now bias the transistor
which you have used to achieve gain 4 in order to achieve maximum gain
without distortions.
Calculate the:
a) D.C level of Input b) D.C level of output node
c) Power Dissipation
d) Threshold voltage of M1
e) Value of parameter K
Soln:

(Gain=4 figure)

(Gain Maximum)

(Screenshot of NetList Used)

(Gain by increasing the Value of Vgs)

Hand Calculations:

Q2.

*question2
.include /home/rajendra15106/modal.mod
M1 7 5 3 3 pmos w=13u l=.13u
M2 8 6 3 3 pmos w=13u l=.13u
M3 7 7 0 0 nmos w=6.5u l =0.13u
M4 8 7 0 0 nmos w=6.5u l=0.13u
M5 3 2 1 1 pmos w=13u l=.13u
M6 4 2 1 1 pmos w=13u l= 0.13u
M7 4 8 0 0 nmos w=13u l=0.13u
M8 2 2 1 1 pmos w=13u l=0.13u
i1 2 0 dc 25u
V1 1 0 dc 2.0
Va 5 11 sin(1.2 0.2u 1k 0 0 )
Vg1 11 0 dc 0.5
Vb 6 12 sin(1.2 0.2u 1k 0 0 )
Vg2 12 0 dc 0.5
.op
.tran 1n 2m
.probe V
*.probe V(4)
*.plot tran V(8)
*.plot tran V(4)
*.plot ac V(6)
*.plot i(*)

.end

Submitted By
Rajendra Prasad Nayak
MT15106