LIBRARY ieee;

USE ieee.std_logic_1164.all;
ENTITY lab2_8register IS
PORT(SW:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LEDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
KEY: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- reset: IN STD_LOGIC;
CLOCK_50: IN STD_LOGIC);
END lab2_8register;
ARCHITECTURE arch_lab2 OF lab2_8register IS
--signal declerations
SIGNAL LED_sig:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLOCK_50, KEY(1), KEY(0))
BEGIN
IF(CLOCK_50'EVENT AND CLOCK_50='1') --Rising Edge Trigger
THEN
LEDR<=LED_sig;
--LEDR<=LED_sig;
IF(KEY(0)='0')
THEN
LED_sig<=SW;
ELSIF(KEY(0)='1')
THEN
LEDR<=LED_sig;
IF (KEY(1)='0')
THEN
LED_sig<="00000000";
END IF;
END IF;
END IF;