Microprocessadores

Prof. Adriano Cardoso

adrianosvc@ufsj.edu.br

Especifica
c
oes da m
aquina did
atica

15 de outubro de 2015

Caminho de dados

in
AA
3

DA

file registers

BA

3
r/W

PC

wpc

16

address
1
16
0
A

fs
3
oe

1
B

pcs

asel

IR

wir

MEM

ALU
rw
me

data

Microprocessadores

Engenharia Mecatr
onica

Especifica
c
oes da m
aquina did
atica

15 de outubro de 2015

Instru
c
oes: opera
c
oes l
ogicas, aritm
eticas e de deslocamento
instru
c
ao
AND Ra,Rb
OR Ra,Rb
XOR Ra,Rb
NOT Ra,Rb
ADD Ra,Rb
INC Ra,Rb
SUB Ra,Rb
DEC Ra,Rb
LS Ra,Rb
RS Ra,Rb

opera
c
ao
Ra Ra & Rb
Ra Ra | Rb
Ra Ra ^ Rb
Ra ~ Rb
Ra Rb + Ra
Ra Rb + 1
Ra Rb - Ra
Ra Rb - 1
Ra Rb << 1
Ra Rb >> 1
6
op code

op
00
00
00
00
00
00
00
00
00
00

code
0000
0001
0010
0011
0100
0101
0110
0111
1001
1010

bin
ario
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
00 1001
01 1010

xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx

reservado

Rb
BA

Ra
AA/DA

ALU fs

bbb
bbb
aaa
bbb
bbb
bbb
bbb
bbb
bbb
bbb

aaa
aaa
bbb
aaa
aaa
aaa
aaa
aaa
aaa
aaa

16

Microprocessadores

Engenharia Mecatr
onica

Especifica
c
oes da m
aquina did
atica

15 de outubro de 2015

L
ogica de controle
inst

op code
xx xxxx

fs
xxxx

oe
0

pcs
x

inst

op code
xx xxxx

fs
0101

oe
1

pcs
1

inst

op code
xx xxxx

fs
xxxx

oe
0

pcs
x

inst

op code
xx xxxx

fs
0101

oe
1

pcs
1

inst
AND
OR
XOR
NOT
ADD
INC
SUB
DEC
LS
RS

op
00
00
00
00
00
00
00
00
00
00

fs
0000
0001
0010
0011
0100
0101
0110
0111
1x01
1x10

oe
1
1
1
1
1
1
1
1
1
1

pcs
0
0
0
0
0
0
0
0
0
0

code
0000
0001
0010
0011
0100
0101
0110
0111
1001
1010

Microprocessadores

t = 0: IRL mem[PC]
AA BA DA r/W wpc
x
x
x
0
0
t = 1: PC PC + 1
AA BA DA r/W wpc
x
x
x
0
1
t = 2: IRH mem[PC]
AA BA DA r/W wpc
x
x
x
0
0
t = 3: PC PC + 1
AA BA DA r/W wpc
x
x
x
0
1
t = 4: execution
AA BA DA r/W wpc
Ra
Rb
Ra
1
0
Ra
Rb
Ra
1
0
Ra
Rb
Ra
1
0
Ra
Rb
Ra
1
0
x
Rb
Ra
1
0
Ra
Rb
Ra
1
0
x
Rb
Ra
1
0
Ra
Rb
Ra
1
0
x
Rb
Ra
1
0
x
Rb
Ra
1
0

Engenharia Mecatr
onica

asel
0

rw
0

me
1

wirl
1

wirh
0

asel
x

rw
x

me
0

wirl
0

wirh
0

asel
0

rw
0

me
1

wirl
0

wirh
1

asel
x

rw
x

me
0

wirl
0

wirh
0

asel
0
0
0
0
0
0
0
0
0
0

rw
x
x
x
x
x
x
x
x
x
x

me
0
0
0
0
0
0
0
0
0
0

wirl
0
0
0
0
0
0
0
0
0
0

wirh
0
0
0
0
0
0
0
0
0
0