FPGA

Prototyping and So1ware Construc8on for ASIC and USB Interface

for Stereo Vision Hardware Accelerator
1
2
2
2
Sungil Kim , Ziyun Li , Hun-Seok Kim , and David T. Blaauw

1Department of Electrical and Computer Engineering, Auburn University, Auburn, AL , 2Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI

Tools

Background

Motivation

Stereo Vision: Extracting 3D (depth) from 2D

images or videos.

Increasing ASICs development cost [1]

Decreasing Time-To-Market [2]
Necessity of Real-time verification [3]

Application-Specific Integrated Circuits (ASIC):

process above algorithm.
Field-Programmable Gate Array (FPGA): an
integrated circuit that can be configured with
HDL (Verilog), used to prototype ASIC.

Spartan 6 FPGA
FX3
ZED Stereo Camera
USB 3.0
Xilinx ChipScope

Objective
Real-time verification of interface among
FPGA, FX3, and USB
Software construction for processing images
and interface testing

Testing Methods

HOST PC
binary le

Verified the circuit behavior

All flags and signals responded correctly
Post-processing of images are needed for rectification.
Debugging interface is difficult, when the system is not
verified at real-time.
Software simulations ran not at real-time (most of the cases)
cannot verify the interface fully.
FPGAs reprogrammable and deterministic system, lowpower consumption, and relatively fast speed makes it an
ideal candidate for ASIC prototype.
Prototyped FPGA
Data transfer rate of 330~400MB/s
Total power consumption of 156mW (dynamic 84mW)

Software Algorithm

[4]
leR/right images

Discussions

Conclusions

Applications

FPGA prototyping is particularly effective for handling realtime signals.

Software simulation alone cannot fully verify interface.
The verifying step via FPGA prototyping can significantly
reduce chip failure and manufacturing cost and increase
design pace.

Autonomous automobile
Robots
3D reconstrucVon
NavigaVon aid for blind
Biomedical images

Future Work
Reusability of the prototype for general data transfer
interface.
Scalability of FPGA to test the state-of-art ASICs.

Results

Acknowledgements
This work was supported by the University of Michigan
Summer Research Opportunity Program (SROP).
The author would like to thank Rackham Graduate School,
College of Engineering, and VLSI Design/Automation Lab.

Output
Figure A. Stream OUT
ChipScope

Figure B. Stream IN

References
1. Dr. Handel Jones, IBS "Factors for Success in System IC Business and Impact on Business
Model", Q4 2012 Report.
2. Ed Clarke, FPGAs and Structured ASICs: Low-Risk SoC for the Masses, Altera
Corporation Report.
3. P. Murugappa, J.-N. Bazin, A. Baghdadi, and M. Jez equel, FPGA Prototyping and
Performance Evaluation of Multi-standard Turbo/LDPC Encoding and Decoding, in Proc. of
the 23nd IEEE International Symposium on Rapid System Prototyping (RSP), 2012.
4. Y. Boykov, O. Veksler and R. Zabih, Fast Approximate Energy Minimization via Graph
Cuts, IEEE Trans. PAMI vol. 23, no. 11, 2001, pp. 1222-1239.