Low

Power Subthreshold Circuit Design for Biomedical Electronics

Sungil Kim and Vishwani D. Agrawal

Department of Electrical and Computer Engineering, Auburn University, Auburn, AL

Objective I. Analytical Delay Model
Accurately estimates circuit delay, especially in
subthreshold region
Previous research [1], alpha-power law, has a
maximum error of 4x in subthreshold region.

Results
error of model [1] = 404%

Motivation

average error = 15%

More accurate delay model can improve circuit

optimization and better predict the future technology
trend.

error of model [1] = 21%

average error = 15%

Method
Previous research [2] presents the variation aware
analytical model.
From that model, the exponential dependence of
delay on differential supply voltage is found.

Objective II. Dual-Threshold Design

Low power consumption is more important than
speed for biomedical electronics
Subthreshold circuit design can significantly reduce
power consumption
However, performance degradation prevents further
applications of subthreshold circuit.

Algorithm

Result

Motivation
Optimize circuit to deter performance degradation
while achieving significant reduction in power

Example:

Method

optimal operating point

at subthreshold voltage

Using both high threshold (slow, more power) and

low threshold (fast, less power) gates.
Optimal gate assignment algorithm [3] is used.

Objective III. Interconnect Optimization

Conclusions

Result

Subthreshold circuit design reduces overall power consumption

More accurate analytical delay model is presented and verified.
Dual-threshold design algorithm is presented, and 25% reduction
in power consumption without performance degradation is shown.
A tapered interconnect driver can reduce enegy up to 75%.
Biomedical electronics can benefit from these techniques to
achieve ultra-low power while maintaining reasonable speed.

Wire capacitance does not scale with VDD

Global interconnect suffers significant performance
drawback
The driver delay dominates the overall delay.

Motivation
Repeater insertion technique [4] is not useful for
subthreshold circuit.
Optimize driver to increase throughput of the circuit

Method
Using tapered driver (upsized driver) to drive the
global interconnect to minimize the overall circuit
delay and increase the performance

25% reduction in power

no change in critical path

75% energy reduction

Future Work
The combination effects of several techniques discussed here
Investigation on the effect of technology scaling
as interconnect length increases,
a tapered driver is more effective

References
[1] T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas." JSSC, vol. 25, no. 2,
pp. 584-594, April 1990. [2] F. Frustaci and P. Corsonello, Analytical delay model considering variability effects in subthreshold domain, IEEE Trans.
Circuits Syst. II, vol. 59, no. 3, pp. 168-172, March 2012. [3] J. Yao and V. D. Agrawal, Dual-threshold design of sub-threshold circuits, in Proceedings
of IEEE SOI-3D-Subthreshold Microelectronics Technology Conference, October 2013, pp. 7778. [4] V. Deodhar and J. Davis, Optimal voltage scaling,
repeater insertion, and wire sizing for wave-pipelined global interconnects, IEEE Trans. Circuits Syst. I, vol. 55, no. 4, pp. 10231030, May 2008.