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# The operational amplifier

Vcc+
Ro
+
+

V1

Ri
_

Vo

V2
Vcc-

V1

+
A(V1-V2)

Vo

V2

Difference amplifier
Model
For an ideal op amp
Ri
Ro0
A

Vcc-

14

+ _

Vsat+
t
Vsat-

Vcc-

_ +

Vcc+

+ _

_ +

Vcc+

LM324

## For an actual op-amp:

Example of packaging
A = 105
Vcc+
Rin= 2 M
Ro = 75
+
Vsat+= 13.5V
Vsat-= -13.5V
In the open loop mode it operates as a comparator
_
Vcc+

Vsat+
V1
V1-0.135mV

Vcc-

V1+0.135mV

V2
Vsat-

V1

Vo

V2
Vcc-

## Digital to Analogue Converter (D/A Converter)

b3b2b1bo is a 4-bit binary number

b3
b2
b1
bo

Ri

## Vo= - Rf/Ri [ b3+ b2/ 2 + b1/4 + bo/8 ]

2Ri

Rf

4Ri
8Ri

_
+

Vo= - Rf / (8Ri) [ 8 b3 + 4 b2 + 2 b1 + bo ]
Vo= - Rf / (8Ri) [ 23 b3 + 22 b2 + 21 b1 + 2o bo ]

Vo

ramp o/p
Vi

Single Slope

Dual Slope

## Single Slope A/D Converter

Vi

t
Comparator
o/p

+ Comparator
_
And

Counter

ramp
generator

t
Input to
counter
Clock

A single slope A/D converter has a ramp generator with a slope of 1 V/ms and a clock
frequency of 100 kHz. If the analogue input voltage is 2 volts, what is the count at the
end of the conversion cycle?
The time taken by the ramp to reach 2 V
(2V) / (1V/ms) = 2 ms
The counter counts for 2 ms at a frequency of 100 kHz
During 2 ms the number counted by the counter is
( 100 103 2 10-3 = 20010 clock pulse or 110010002

Ramp Generator
R1

V1

Vo R 1

R2

V1 =
R1+R2

R4

V2

_
+
R4

R3 V2 V1

Vin

Vo

Vin

R3

SR3

1
SC

Vo

1
SC

Vin

Vo - V2
- V2sC +

R4 Vin /s
V2 =

Vo
+

R3 [ 1 + R4Cs ]

=
[ 1 + R4Cs ]

sR3

R1

= 0
R4

Vo
[ R1+R2]

## V2[ sC + 1/R4] =Vin/(sR3) + Vo/R4

V2[R4sC + 1 ] = R4 Vin/(sR3)+ Vo

R4 Vin /s

Vo

V2 =
Vo

R1

+
R3 [ 1 + R4Cs ]

=
[ 1 + R4Cs ]

R4 Vin/s

R1
= (

R3 [ 1+R4Cs ]

[ R1+R2]
1

[R1+R2]

)
[ 1+ R4Cs]

[ 1+R4Cs ] R1
R4/R3 Vin/s = (

- 1 ) Vo
[R1+R2]
R1+R1R4Cs R1 R2

R4/R3 Vin/s =

Vo
[R1+R2]
R1R4Cs R2

R4/R3 Vin/s =

Vo
[R1+R2]

Vo

## Dual Slope A/D Converter

R2

R1

comparator

AND gate

+
Vin

R4

R3

counter

MSB
C
clock

- Vref

ramp generator
electronic switch