DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINERRING

Experiment: 01
Object: Write the Verilog Code & Simulate all basic Logic Gates.
Software Required: Project Navigator
Program Code:

Verilog code for AND GATE

Verilog code for OR GATE

module and12(a,b,c);
input a;
input b;
output c;
assign c = a & b;
endmodule

module or12(a,b,d);
input a;
input b;
output d;
assign d = a | b;
endmodule

Verilog code for NAND GATE

Verilog code for XOR GATE

module nand12(a,b,e);
input a;
input b;
output e;
assign e = ~(a & b);
endmodule
Verilog code for XNOR GATE

module xor12(a,b,h);
input a;
input b;
output h;
assign h = a ^ b;
endmodule
Verilog code for NOR GATE

module xnor12(a,b,i);
input a;
input b;
output i;
assign i = ~(a ^ b);
endmodule
Verilog code for NOT GATE

module nor12(a,b,f);
input a;
input b;
output f;
assign f = ~(a | b);
endmodule

module not12(a,g);
input a;
output g;
assign g = ~a;
endmodule
Simulation Result:
Result: We have successfully simulated all basic Logic Gates.

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Software Lab - II (ECP-0603)