CS6211Digital Lab
Pin Details of Digital Logic Gates:
CS6211Digital Lab
7476
7474
CS6211Digital Lab
Postulates and Theorems of Boolean algebra:
S.No
Postulate/Theorem
Duality
Remarks
1.
X+0=X
X.1 = X
2.
X + X = 1
X.X = 0
3.
X+X=X
X.X = X
4.
X+1=1
X.0 = 0
5.
(X) = X
6.
X+Y=Y+X
X.Y = Y.X
Commutative
7.
X + (Y + Z) = (X + Y) + Z
X.(Y.Z) = (X.Y).Z
Associative
8.
X + (Y.Z) = (X + Y)(X + Z)
Distributive
9.
(X + Y) = XY
(XY) = X + Y
10.
X + XY = X
X.(X + Y) = X
DeMorgans
Theorem
Absorption
Involution
Bit Grouping:
Bit
Two bits.
Nibble or Nybble
Four bits.
Nickle
Five bits.
Byte
Eight bits.
Deckle
Ten bits.
Playte
Sixteen bits.
Dynner
Thirtytwo bits.
Word
(system dependent).
Arithmetic Notations:
Augend
Addend
Sum
Minuend
Subtrahend
Difference
Multiplicand
Multiplier
Product
Dividend
Divisor
Quotient
CS6211Digital Lab
FLIP FLOPS
JK FLIP FLOP
SR FLIP FLOP
D FLIP FLOP
T FLIP FLOP
CS6211Digital Lab
Verification of Logic Gates:
CS6211Digital Lab
VERIFICATION OF BOOLEAN THEOREMS USING
DIGITAL LOGIC GATES
EXPT NO. :1
DATE :
Aim:
To verify the truth table of basic Boolean algebric laws by using logic gates.
Components Required:
S.NO
1
COMPONENTS
Digital IC trainer
kit
IC
3
4
Bread board
Connecting wires
RANGE
QUANTITY
7400
7402
7404
7408
7432
7486

1
1
1
1
1
1
1
As required
Theory:
Demorgans Theorems
First Theorem:
It states that the complement of a product is equal to the sum of the complements.
(AB) =A +B
Second Theorem:
It states that the complement of a sum is equal to the product of the complements.
(A+B) =A.B
Boolean Laws:
Boolean algebra is a mathematical system consisting of a set of two or more distinct
elements, two binary operators denoted by the symbols (+) and (.) and one unary operator
denoted by the symbol either bar () or prime (). They satisfy the commutative, associative,
distributive and absorption properties of the Boolean algebra.
Commutative Property:
Boolean addition is commutative, given by
A+B=B+A
Boolean algebra is also commutative over multiplication, given by
A.B=B.A
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CS6211Digital Lab
DeMorgans Theorem:
Truth Table:
Input
Output
(A+B)
A. B
Commutative Law:
Truth Table:
Input
Output
A+B
B+A
CS6211Digital Lab
Associative Property:
The associative property of addition is given by
A+ (B+C) = (A+B) +C
The associative law of multiplication is given by
A. (B.C) = (A.B).C
Distributive Property:
The Boolean addition is distributive over Boolean multiplication, given by
A+BC = (A+B) (A+C)
Boolean multiplication is also distributive over Boolean addition given by
A. (B+C) = A.B+A.C
Realization of circuits for Boolean expression after simplification:
A binary variable can take the value of 0 or 1. A Boolean function is an expression
formed with binary operator OR, AND and a unary operator NOT, parenthesis function can be 0
or 1.
For example, consider the function
The prime implicants are found by using the elimination of complementary function. The circuit
diagram for the function is drawn using AND.OR and NOT gates. The output for the
corresponding input of A1, A0, B1, BO is calculated and the truth table is drawn.
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
CS6211Digital Lab
Associative Law:
Truth Table:
Input
Output
A+B
(A+B)+C
B+C
A+(B+C)
Distributive Law:
10
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Truth Table:
Input
Output
B+C
A.(B+C)
A.B
A.C
A.B+A.C
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VIVA QUESTION:
1.Define logic gates?Give examples with symbols.
2.What are universal gates? Why it is called so?
3.What are special type of gates with examples?
4.Explain positive and negative logic.
5.Explain duality theorem.
6.State DeMorgans theorem.
7.What are the basic rules used in Boolean expressions?
8.What are the differences between Boolean and Ordinary Algebra?
9.What are the Boolean postulates?
10.State inversion law.
APPLICATIONS:
EXOR gate can be used for communication transmission and reception.
AND gate is used in Electronic door.
NOT gate is used in House alarm and Traffic lights.
EXNOR gate is used in Warning lights.
All basic gates can be used for signal processing and communication.
RESULT:
Thus the truth table of basic Boolean algebraic laws by using basic logic gates are verified.
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CS6211Digital Lab
Truth Table for Arbitrary Function:
Input
Output
A1
A0
B1
B0
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CS6211Digital Lab
DESIGN AND IMPLEMENTATION OF COMBINATIONAL
CIRCUITS USING BASIC GATES FOR ARBITRARY
FUNCTIONS,CODE CONVERTERS,ETC
EXPT NO. :2
DATE :
Aim:
To design and implement a combinational circuit using basic gates for arbitrary functions
and code converters.
Components Required:
S.NO
1
COMPONENTS
Digital IC Trainer
kit
IC
3
4
Connecting wires
Bread board
RANGE
QUANTITY
7404
7408
7432
7486

1
2
1
1
As required
1
Theory:
Adder:
Digital computers perform various arithmetic operations. The most basic operation is the
addition of two binary digits. The simple addition consists of four possible elementary operations,
namely
A B Sum Carry
0 0
0
0
0 1
1
0
1 0
1
0
1 1
0
1
The logic circuit which performs the addition of two binary digits which results a sum and carry
output is called a half adder. In the above operations the first three operations result with zero
carry but fourth operation has carry 1. The circuit which performs addition of three bits is called
a full adder. A full adder is a combinational circuit that forms the arithmetic sum of three input
bits. It consists of three inputs and two outputs. Two of the input variables are denoted by A and
B represents the two significant bits to be added. The third input represents the carry from the
previous lower significant position.
Subtractor:
The subtraction consists of four possible elementary operations, namely
A
0
0
1
1
B
0
1
0
1
Difference Borrow
0
0
1
0
1
0
0
1
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In all operations each subtrahend bit is subtracted from the minuend bit. In case of second
operation the minuend bit is smaller than the subtrahend bit hence 1 is borrowed.
Binary to Gray Vice versa:
The binary coded decimal (BCD) code is one of the early computer codes. Each decimal
digit is independently converted to a 4 bit binary number. A binary code will have some
unassigned bit combinations if the number of elements in the set is not a multiple power of 2.
The 10 decimal digits form such a set. A binary code that distinguishes among 10 elements must
contain at least four bits, but 6 out of the 16 possible combinations remain unassigned. Different
binary codes can be obtained by arranging four bits in 10 distinct combinations. The code most
commonly used for the decimal digits is the straight binary assignment. This is called binary
coded decimal.
The gray code is used in applications where the normal sequence of binary numbers may
produce an error or ambiguity during the transition from one number to the next. If binary
numbers are used, a change from 0111 to 1100 may produce an intermediate erroneous number
1001 if the rightmost bit takes longer to change in value than the other three bits. The gray code
eliminates this problem since only one bit changes in value during any transition between two
numbers.
BCD to Excess 3 Vice versa:
Excess 3 code is a modified form of a BCD number. The excess 3 code can be derived from
the natural BCD code by adding 3 to each coded number. For example, decimal 6 can be
represented in BCD as 0110. Now adding 3 to the given number yield equivalent excess 3 code
i.e., 6 + 3 = 9 0110 + 0011 = 1001. Thus for the entire sequence of BCD value (i.e., 0 to 9)
excess 3 equivalent table should be made so that the realization of Boolean expression for the
circuit implementation is feasible. In the reverse process of designing a code converter from
excess 3 to BCD the same procedure is followed. Here are the general steps to be followed while
going for a code converter design,
start with the specification of the circuit to be designed.
Identify the inputs and outputs
Derive truth table
Obtain simplified Boolean equations
Draw the logic diagram
Check the design to verify correctness with the truth/verification table.
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CS6211Digital Lab
Truth Table (Binary to Gray):
Binary (Input)
Gray (Output)
B3
B2
B1
B0
G3
G2
G1
G0
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CS6211Digital Lab
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
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CS6211Digital Lab
Logic Diagram for Binary to Gray Code Converter:
Binary (Output)
G3
G2
G1
G0
B3
B2
B1
B0
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Truth Table(BCD to Excess 3):
Decimal
Value
BCD Input
Excess 3 output
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Circuit Diagram for BCD to Excess 3 Converter:
Decimal
Value
Excess 3 Input
BCD Output
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Realization of Boolean Expression for Excess 3 to BCD Converter:
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VIVA QUESTIONS:
1.Define Combinational Circuit.Give examples.
2.Define fan in and fan out.
3.Explain Kmap.
4.Define code converter.
5.What are the code converters used?
6.What is packed BCD?
7.What is the special feature of gray code?
8.List out the applications of gray code.
9.Obtain XS3 code for (458)10.
10.Encode the decimal number 46 to gray code.
APPLICATONS:
Gay code is used as encoders for position sensor.
An example of code converter is a simple handheld calculator,which is composed of an
input device called a keyboard.
Result:
Thus the combinational circuit for an arbitrary function, code converter using logic gates
was designed, implemented and tested its performance with truth table.
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CS6211Digital Lab
S (Sum)
0
0
1
0
1
0
0
1
1
C
(Carry)
0
0
0
Circuit Diagram:
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CS6211Digital Lab
EXPT NO. :3
DATE :
AIM:
To design and implement 4bit binary adder and subtractor using basic gates and MSI
devices.
APPARATUS REQUIRED:
Sl.No.
COMPONENT
1.
IC
2.
EXOR GATE
3.
NOT GATE
3.
IC TRAINER KIT
4.
PATCH CORDS
SPECIFICATION
IC 7483
IC 7486
IC 7404

QTY.
1
1
1
1
40
THEORY:
Adder:
Digital computers perform various arithmetic operations. The most basic operation is the
addition of two binary digits. The simple addition consists of four possible elementary operations,
namely
A B Sum Carry
0 0
0
0
0 1
1
0
1 0
1
0
1 1
0
1
The logic circuit which performs the addition of two binary digits which results a sum and carry
output is called a half adder. In the above operations the first three operations result with zero
carry but fourth operation has carry 1. The circuit which performs addition of three bits is called
a full adder. A full adder is a combinational circuit that forms the arithmetic sum of three input
bits. It consists of three inputs and two outputs. Two of the input variables are denoted by A and
B represents the two significant bits to be added. The third input represents the carry from the
previous lower significant position.
Subtractor:
The subtraction consists of four possible elementary operations, namely
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CS6211Digital Lab
Truth Table (Full Adder):
Cin
S (Sum)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
Circuit Diagram:
32
C
(Carry)
0
0
0
1
0
1
1
1
CS6211Digital Lab
A
0
0
1
1
In all operations each subtrahend
B Difference Borrow
0
0
0
1
1
0
0
1
0
1
0
1
bit is subtracted from the minuend bit. In case of second
operation the minuend bit is smaller than the subtrahend bit hence 1 is borrowed.
A half subtractor is a combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if 1 is borrowed. Let A and B are the input variables
for the half subtractor, then the result produced from the operation is difference and borrow.
A full subtractor is a combinational circuit that performs the subtraction between two bits,
taking into account borrow of the lower significant stage. Thus the full subtractors operate on
three inputs A, B and borrow from the lower significant stage and results in two outputs i.e.,
difference and borrow.
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Truth Table (Half Subtractor):
D(Difference)
B( Borrow)
Circuit diagram:
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CS6211Digital Lab
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CS6211Digital Lab
B
0
0
1
1
0
0
1
1
Cin D(Difference)
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
Circuit Diagram:
36
B( Borrow)
0
1
1
1
0
0
0
1
CS6211Digital Lab
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PIN DIAGRAM FOR IC 7483:
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TRUTH TABLE:
Input Data A
A4
Input Data B
A3
A2
A1
B3
B2
B1
B4
Addition
Subtraction
S4
S3
S2
S1
D4
D3
D2
D1
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CS6211Digital Lab
VIVA QUESTION :
1 .What is binary adder?Give its types.
2.What is priority encoder?.
3.What is parallel adder?.
4.Explain how single IC worked as a Adder/Subtractor.
5.How to perform the subtraction operation.
6.What is binary subtractor?Give its types.
7.What is look ahead carry adder?
8.What is half adder and full adder?Give their Boolean expression.
9.What is half subtractor and full subtractor?Give their Boolean expression.
10.What are the applications of full adder?
APPLICATIONS:
The Full adder acts as the building block of the 4bit/8bit binary/BCD adder ICs such as
7483.
It is used in the digital library.
It is used in digital computers.
It is used in arithmetic logic unit(ALU).
One major application of subtractor is it is used in computers.It is used in ALU.
RESULT:
Thus the 4bit binary adder/sub tractor is constructed using basic gates and MSI devices
and truth tables are verified.
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Truth Table for Parity Generator / Checker Using Basic Gates:
EP
OP
ODD PARITY
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CS6211Digital Lab
DESIGN AND IMPLEMENTATION OF PARITY GENERATOR /
EXPT NO. :4
DATE :
Aim:
To design and implement the parity generator/checker using basic gates and MSI devices
and verify its performance with the verification table.
Components Required:
S.NO
1
COMPONENTS
Digital IC Trainer
kit
IC
3
4
Connecting wires
Bread board
RANGE
QUANTITY
7486
74180
7404

2
2
1
As required
1
Theory:
A parity bit is used for detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the number is either even or
odd. The message including the parity bit is transmitted and then checked at the receiver ends
for errors. An error is detected if the checked parity bit doesnt correspond to the one
transmitted. The circuit that generates the parity bit in the transmitter is called a parity
generator and the circuit that checks the parity in the receiver is called a parity checker.
In even parity, the added parity bit will make the total number is even amount. In odd
parity, the added parity bit will make the total number is odd amount. The parity checker circuit
checks for possible errors in the transmission. If the information is passed in even parity, then
the bits required must have an even number of 1s. An error occur during transmission, if the
received bits have an odd number of 1s indicating that one bit has changed in value during
transmission.
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CS6211Digital Lab
FUNCTION TABLE:
INPUTS
OUTPUTS
PE
PO
EVEN
ODD
EVEN
ODD
X
X
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
0
1
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CS6211Digital Lab
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
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CS6211Digital Lab
Logic Diagram :
Truth Table:
I7 I6 I5 I4 I3 I2 I1 I0
Active
0 0 0 0 0 0 0 1
0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0
I7 I6 I5 I4 I3 I2 I1 I0
Active
1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0
Logic Diagram :
Truth Table:
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CS6211Digital Lab
Result:
Thus the Parity Generator/Checker was designed & implemented using logic gates and
MSI devices and its performance was verified.
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CS6211Digital Lab
Output
A1
A0
B1
B0
Ai = Bi
Ai > Bi
Ai < Bi
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CS6211Digital Lab
DESIGN AND IMPLEMENTATION OF MAGNITUDE
COMPARATOR
EXPT NO. :5
DATE :
AIM:
3
4.
ICs
Connecting Wires /
Patch Cords
Bread board
RANGE
7404
7486
7408
7432
QUANTITY
1
1
1
3
1
As required
THEORY:
The comparison of two numbers is an operation that determines if one number is greater
than, less than, or equal to the other number. A magnitude comparator is a combinational circuit
that compares the two numbers, A and B, and determines their relative magnitude.
The circuit for comparing two nbit numbers has 2n entries in the truth table and becomes
too cumbersome even with n=3. On the other hand comparator circuits possess a certain amount
of regularity. The algorithm is a direct application of the procedure a person uses to compare the
relative magnitudes of two numbers. Consider two numbers, A and B, with four digits each
consider
A=A3A2A1A0
B=B3B2B1B0
The two numbers are equal if all pairs of significant digits are equal: A 3=B3, A2=B2, A1=B1 and
A0=B0. When the numbers are binary, the digits are either 0 or 1, and the equality relation of
each pair of bits can be expressed logically with an EXOR function
xi =Ai Bi + Ai Bi
for i=0,1,2,3
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CS6211Digital Lab
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CS6211Digital Lab
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
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CS6211Digital Lab
Logic Diagram:
8 Bit Magnitude Comparator
Truth Table:
A>B
A=B
A<B
0000 0000
0000 0000
0001 0001
0000 0000
0000 0000
0001 0001
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CS6211Digital Lab
RESULT:
Thus the magnitude comparator was constructed using logic gates and verified with its
truth table.
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CS6211Digital Lab
Truth Table of Multiplexer:
Data Select
Lines
S1
S2
0
0
0
1
1
0
1
1
Circuit Diagram:
54
Output
Y
D0
D1
D2
D3
CS6211Digital Lab
DESIGN AND IMPLEMENTATION OF APPLICATION
USING MULTIPLEXERS/DEMULTIPLEXERS
EXPT NO. :6
DATE :
Aim:
To design and implement a 4 to 1 multiplexer and 1 to 4 demultiplexer using logic gates.
Components Required:
S.NO COMPONENTS
1
Digital Trainer kit
2
ICs
3
4
Connecting wires
Bread board
RANGE
7408
7432
7404

QUANTITY
1
3
1
1
As required
1
Theory:
Multiplexer:
The term multiplex means many into one. Multiplexing is the process of transmitting a
large number of information over a single line. A digital multiplexer is a combinational circuit
that selects one digital information from several sources and transmits the selected information
on a single output line. A multiplexer is also called a data selector since it selects one of many
inputs and steers the information to the output.
The 4 to 1 multiplexer has 4 input lines (D0D3), a single output line (Y) and two select
lines (S1 and S2) to select one of the four input lines. From the truth table, a logical expression for
the output in terms of the data input and the select inputs.
The data output Y = Data input D0, if S1 =0 and S2 =0
Therefore Y= D0 S1 S2
Similarly Y= D1 S1 S2; Y=D1 when S1=0 and S2 =1.
Demultiplexer:
A demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines. The selection of specific output line is controlled by
the values of n selection lines.
The single input variable Din has a path to all four outputs, but the information is directed
to only one of the output lines decided by the selection lines A and B.
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CS6211Digital Lab
Truth Table of Demultiplexer:
Enable
Selection
Lines
Data
Input
Output Line
Din
Y0
Y1
Y2
Y3
Circuit Diagram:
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CS6211Digital Lab
Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
VIVA QUESTIONS:
1.What is mux?Why mux is called data selector?
2.What is the necessity of mux?
3.What are the types of mux?
4.What are the features of 8:1 mux?
5.What is multiplexer tree?
6.What is demux?What are the types of demux?
7.What is demultiplexer tree?
8.What are the features of 4 line to 16 line Decoder/Demux?
9.Compare mux and demux.
10.What is the use of mux for logic design and combinational circuit design?
APPLICATIONS:
MULTIPLEXER:
It is used as a data selector to select one out of many data inputs.
It is used for simplification of logic design.
It is used in the data acquisition system.
It is used in designing the combinational circuits.
It is used in the D/A converters.
It is used to minimize the number of connections.
It is used in time division multiplexing at the sending end.
DEMULTIPLEXER:
We can implement some combinational circuit.
It is used in TDM system at receiving end.
Result:
Thus the combinational circuit, 4:1 multiplexer and 1:4 demultiplexer were designed,
implemented and verified with their truth table.
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PIN DIAGRAM:
LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE:
Serial in
Serial out
CLK
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CS6211Digital Lab
EXPT NO. :7
DATE :
Aim:
To design, implement and verify the functioning of shift right registers (all types) using D
flipflop.
Components Required:
S.NO
1
COMPONENTS
Digital IC trainer
kit
IC
3
4
Connecting wires
Bread Board
RANGE
QUANTITY
7474
7408
7404
7432

2
2
1
1
1
Theory:
A register that is used to store binary information is known as a memory register. A
register capable of shifting binary information either to the right or the left is called a shift
register. Shift registers are classified into four types,
1. Serialin Serialout (SISO)
2. Serialin Parallelout (SIPO)
3. Parallelin Serialout (PISO)
4. Parallelin Parallelout (PIPO)
Serialin Serialout (SISO):
This type of shift registers accepts data serially, i.e., one bit at a time on a single input
line. It produces the stored information on its single output also in serial output also in serial
form. Data may be shifted left (from low to high order bits) using shiftleft register or shifted
right (from high to low order bits) using shiftright register.
Serialin Parallelout (SIPO):
It consists of one serial input, and outputs are taken from all the flipflop simultaneously
in parallel. In this register, data is shifted in serially but shifted out in parallel. In order to shift
the data out in parallel, it is necessary to have all the data available at the outputs at the same
time. Once the data is stored, each bit appears on its respective output line and all the bits are
available simultaneously, rather than on a bit by bit basis as with the serial output.
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TRUTH TABLE:
OUTPUT
CLK
DATA
QA
QB
QC
QD
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TRUTH TABLE:
CLK
Q3
Q2
Q1
Q0
O/P
TRUTH TABLE:
DATA INPUT
OUTPUT
CLK
DA
DB
DC
DD
QA
QB
QC
QD
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VIVA QUESTIONS:
1.What is shift register?
2.What are the modes of operation of a shift register?
3.How many clock pulses required in SISO mode to store a nbit word?
4.What are the modes available in SISO and PISO?
5.What is bidirectional shift register and universal shift register?
6.What are the capabilities of a universal shift register?
7.What is delay line?
8.What are the features of serial adder?
9.What is sequence generator?
10.What is shift register counters?Why it is called so?Give examples.
APPLICATIONS:
It is used for temporary data storage.
It is used for multiplication and division.
It is used as a delay line.
It is used as serial to parallel converter.
It is used as parallel to serial converter.
It is used as ring counter.
It is used as Twisted ring counter or Johnson counter.
Result:
Thus the shift registers using D flipflop were implemented and studied their operation in
4 different modes.
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JK Excitation Table:
Qn
Qn+1
Present State
Next State
JK FlipFlop Inputs
A+
B+
C+
JA
KA
JB
KB
JC
KC
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EXPT NO. :8(a) DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS
DATE :
Aim:
To design and implement a 3bit synchronous binary up and down and up/down counter
using JK flipflop.
Components Required:
S.NO
1
COMPONENTS
Digital Trainer
Kit
ICs
3
4
Connecting wires
Bread Board
RANGE
QUANTITY
7476
7408
7432

2
1
1
As required
1
Theory:
A Synchronous counter is also called parallel counter. In this counter the clock inputs of
all the flipflops are connected together so that the input clock signal is applied simultaneously
to each flipflop. Also, only the LSB flipflop C has its J and K inputs connected permanently to
Vcc while the J and K inputs of the other flipflops are driven by some combination of flipflop
outputs.
3 Bit Synchronous Binary UP Counter:
The J and K inputs of the flipflop B are connected to with QC. The J and K inputs of the
flipflop A, are connected with AND operated output of QC and QB. The flipflop C changes its
state when with the occurrence of negative transition at each clock pulse. The flipflop B changes
its state when QC = 1 and when there is negative transition at clock input. Flipflop A changes its
state when QC = QB = 1 and when there is negative transition at clock input.
3 Bit Synchronous Binary DOWN Counter:
The J and K inputs of the flipflop B are connected to with QC. The J and K inputs of the
flipflop A, are connected with AND operated output of QC and QB. The flipflop C changes its
state when with the occurrence of negative transition at each clock pulse. The flipflop B changes
its state when QC = 1 and when there is negative transition at clock input. Flipflop A changes
its state when QC = QB = 1 and when there is negative transition at clock input.
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Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
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State Table (3 bit synchronous binary DOWN counter)
Present State
Next State
JK FlipFlop Inputs
A+
B+
C+
JA
KA
JB
KB
JC
KC
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Circuit Diagram Of 3 Bit Synchronous Binary Down Counter:
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A
JA
1
X
X
X
X
0
0
0
0
0
0
1
X
X
X
X
B
KA
X
0
0
0
1
X
X
X
X
X
X
X
0
0
0
1
JB
1
X
X
0
1
X
X
0
0
1
X
X
0
1
X
X
C
KB
X
0
1
X
X
0
1
X
X
X
0
1
X
X
0
1
JC
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
72
KC
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
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Circuit Diagram Bit Synchronous Up/Down Counter
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Result:
Thus the synchronous up, down and up/down counters were designed using JK flipflop
and verified with their state table.
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Verification Table (4 bit binary ripple up counter):
Clock
Pulse
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q3
Q2
Q1
Q0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Circuit Diagram:
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EXPT NO. :8(b) DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTERS
DATE :
Aim:
To design and implement a 4bit asynchronous binary up and down counter using JK flipflop.
Components Required:
S.NO
1
2
3
4
5
6
COMPONENTS
Digital IC trainer
kit
IC
Bread board
Connecting wires
RANGE
QUANTITY
7476
7400

2
1
1
1
As required
Theory:
A counter, by function, is a sequential circuit consisting of a set of flipflops connected in a
suitable manner to count the sequence of the input pulses presented to it digital form. An
asynchronous counter, each flipflop is triggered by the output from the previous flipflop which
limits its speed of operation. The settling time in asynchronous counters, is the cumulative sum
of the individual settling times of flipflops. It is also called a serial counter.
The asynchronous counter is the simplest in terms of logical operations, and is therefore
the easiest to design. In this counter, all the flipflops are not under the control of a single clock.
Here, the clock pulse is applied to the first flipflop, i.e. the least significant bit stage of the
counter, and the successive flipflop is triggered by the output is constructed using clocked JK
flipflops. The system clock, a square wave, drives flipflop A (LSB). The output of A drives flipflop B, the output of B drives flipflop C. all the J and K inputs connected to Vcc (High (1)), which
means that each flipflop toggles on the edge (ve) clock pulse.
Consider initially all flipflops to be in the logical 0 state (i.e. QA=QB=QC=QD=0). A
negative transition in the clock input which drives flipflop A causes QA to change from 0 to 1.
Flipflop B doesnt change its state since it is also requires negative transition at its clock input,
i.e. it requires its clock input (QA) to change from 1 to 0. With arrival of second clock pulse to flipflop A, QA goes from 1 to 0. This change of state creates the negative going edge needed to trigger
flipflop B, and thus QB goes from 0 to 1. Before the arrival of the 16th clock pulse, all the flipflops are in the logical 1 state. Clock pulse 16 causes Q A, QB, QC and QD to go logical 0 state in
turn.
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Verification Table (4 bit binary ripple down counter):
Clock
Pulse
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q3
Q2
Q1
Q0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Circuit Diagram:
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Procedure:
1. Test the individual ICs with its specified verification table for proper working.
2. Connections are made as per the circuit/logic diagram.
3. Make sure that the ICs are enabled by giving the suitable Vcc and ground connections.
4. Apply the logic inputs to the appropriate terminals of the ICs.
5. Observe the logic output for the inputs applied.
6. Verify the observed logic output with the verification/truth table given.
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CLK
QA
QB
QC
QD
10
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QA
QB
QC
QD
10
11
12
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Result:
Thus the asynchronous up, down and MOD counters were constructed and tested the
operations with the help of their verification tables.
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PROGRAM:
MULTIPLEXER:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux is
port( I3:
in std_logic_vector(2 downto 0);
I2: in std_logic_vector (2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S:
in std_logic_vector(1 downto 0);
O:
out std_logic_vector(2 downto 0)
);
end Mux;
architecture behv2 of Mux is
begin
O <=
I0 when
I1 when
I2 when
I3 when
"ZZZ";
S="00"
S="01"
S="10"
S="11"
else
else
else
else
end behv2;
ADDER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end adder;
architecture Behavioral of adder is
begin
s<=(a xor (b xor cin));
cout<=(b and cin) or (a and cin) or (a and b);
end Behavioral;
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EXPT NO. :9(a)
DATE :
Aim:
To design and implement combinational circuits using VHSIC Hardware Description
Language (VHDL).
Components Required:
S.NO COMPONENTS
1
Computer
2
ModelSim
RANGE
Software
QUANTITY
1
1
Theory:
The ModelSim debug environments broad set of intuitive capabilities for Verilog, VHDL,
and SystemC make it the choice for ASIC and FPGA design.
ModelSim eases the process of finding design defects with an intelligently engineered
debug environment. The ModelSim debug environment efficiently displays design data for
analysis and debug of all languages.
ModelSim allows many debug and analysis capabilities to be employed postsimulation on
saved results, as well as during live simulation runs. For example, the coverage viewer analyzes
and annotates source code with code coverage results, including FSM state and transition,
statement, expression, branch, and toggle coverage.
Signal values can be annotated in the source window and viewed in the waveform viewer,
easing debug navigation with hyperlinked navigation between objects and its declaration and
between visited files.
Race conditions, delta, and event activity can be analyzed in the list and wave windows.
Userdefined enumeration values can be easily defined for quicker understanding of simulation
results. For improved debug productivity, ModelSim also has graphical and textual dataflow
capabilities.
Procedure:
CS6211Digital Lab
WAVE FROMS:
MULTIPLEXER
ADDER
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Result:
Thus the combinational circuits are tested and implemented using VHDL.
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PROGRAM:
HALF ADDER
module ha(a,b,sum,carry);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule
FULL ADDER
module fa(a,b,cin ,s,cout);
input a;
input b;
input cin;
output s;
output cout;
wire s1,c1,c2;
xor(s1,a,b);
and(c1,a,b);
and(c2,cin,s1);
or(cout,c1,c2);
endmodule
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EXPT NO. :9(b)
DATE :
Aim:
To design and implement combinational circuits using Verilog Hardware Description
Language (HDL).
Components Required:
S.NO COMPONENTS
1
Computer
2
ModelSim
RANGE
Software
QUANTITY
1
1
Theory:
The ModelSim debug environments broad set of intuitive capabilities for Verilog, VHDL, and
SystemC make it the choice for ASIC and FPGA design.
ModelSim eases the process of finding design defects with an intelligently engineered
debug environment. The ModelSim debug environment efficiently displays design data for
analysis and debug of all languages.
ModelSim allows many debug and analysis capabilities to be employed postsimulation on
saved results, as well as during live simulation runs. For example, the coverage viewer analyzes
and annotates source code with code coverage results, including FSM state and transition,
statement, expression, branch, and toggle coverage.
Signal values can be annotated in the source window and viewed in the waveform viewer,
easing debug navigation with hyperlinked navigation between objects and its declaration and
between visited files.
Race conditions, delta, and event activity can be analyzed in the list and wave windows.
Userdefined enumeration values can be easily defined for quicker understanding of simulation
results. For improved debug productivity, ModelSim also has graphical and textual dataflow
capabilities.
Procedure:
CS6211Digital Lab
HALF SUBTRACTOR
module hs(a,b,s,diff,borrow);
input a,b;
output diff,borrow;
xor(diff,a,b);
not(nota,a);
and(borrow,nota,b);
endmodule
FULL SUBTRACTOR
module fs(a,b,c,diff,borrow);
input a,b,c;
output diff,borrow;
wire b1,b2,b3,abar;
not(abar,a);
xor(diff,a,b,c);
and(b1,b,c);
and(b2,abar,c);
and(b3,abar,b);
or(borrow,b1,b2,b3);
endmodule
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MULTIPLEXER: (2:1)
module mux2to1 (a,b,s,y);
input a,b,s;
output y;
assign y=s?a:b;
endmodule
DEMULTIPLEXER: (1:2)
module demux1to2(a,s,y1,y2);
input a,s;
output y1,y2
reg y1,y2;
always@(a,s)
begin
case(s)
0:y1=a;
default: y2=a;
endcase
end
endmodule
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APPLICATIONS:
VIVA QUESTIONS:
1. What is Verilog HDL?
2. What are the three basic description styles supported by Verilog HDL?
3. Define module.
4. What is logic synthesis in HDL?
5. What is gate level modeling?
6. Mention any two uses of HDL.
7. What is data flow modeling?
RESULT:
Thus the combinational circuits are tested and implemented using Verilog
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PROGRAM:
JK FLIP FLOP:
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk:in std_logic;q,q1,z:inout std_logic);
end jkff;
architecture arc of jkff is
begin
process(clk)
begin
if clk='1' then
z <=(j and (not q)) or ((not k) and q);
q <=z after 5ns;
q1 <=not z after 5ns;
end if;
end process;
end arc;
RING COUNTER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ring_counter is
port (
DAT_O : out unsigned(3 downto 0);
RST_I : in std_logic;
CLK_I : in std_logic
);
end ring_counter;
architecture Behavioral of ring_counter is
signal temp : unsigned(3 downto 0):=(others => '0');
begin
DAT_O <= temp;
process(CLK_I)
begin
if( rising_edge(CLK_I) ) then
if (RST_I = '1') then
temp <= (0=> '1', others => '0');
else
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SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
RANGE
Software
QUANTITY
1
1
Theory:
The ModelSim debug environments broad set of intuitive capabilities for Verilog, VHDL,
and SystemC make it the choice for ASIC and FPGA design.
ModelSim eases the process of finding design defects with an intelligently engineered
debug environment. The ModelSim debug environment efficiently displays design data for
analysis and debug of all languages.
ModelSim allows many debug and analysis capabilities to be employed postsimulation on
saved results, as well as during live simulation runs. For example, the coverage viewer analyzes
and annotates source code with code coverage results, including FSM state and transition,
statement, expression, branch, and toggle coverage.
Signal values can be annotated in the source window and viewed in the waveform viewer,
easing debug navigation with hyperlinked navigation between objects and its declaration and
between visited files.
Race conditions, delta, and event activity can be analyzed in the list and wave windows.
Userdefined enumeration values can be easily defined for quicker understanding of simulation
results. For improved debug productivity, ModelSim also has graphical and textual dataflow
capabilities.
Procedure:
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temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= temp(3);
end if;
end if;
end process;
end Behavioral;
WAVEFORM:
JK flip flop
Ring Counter
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Result:
Thus the Sequential circuits are tested and implemented using VHDL.
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RIPPLE CARRY COUNTER:
module counter(count,clk,clr);
input clk,clr;
output[3:0] count;
wire[3:0] q,qbar;
tflp ff1(count[0],q[0],clk,clr,1b1);
tflp ff1(count[1],q[1],count[0],clr,1b1);
tflp ff1(count[2],q[2],count[1],clr,1b1);
tflp ff1(count[3],q[3],count[2],clr,1b1);
endmodule
MOD 10 COUNTER:
module mod10(reset,clk,a,z);
input clk,reset;
input[3:0] a;
output[3:0] z;
reg[3:0] z;
reg[3:0] count;
always@(posedge clk,reset)
begin
if(reset==1b1)
begin
z=4b0000;
count=4b0000
end
else
begin
z=count;
count=count+4b0001;
if(count==4b1010)
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SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
RANGE
Software
QUANTITY
1
1
Theory:
The ModelSim debug environments broad set of intuitive capabilities for Verilog, VHDL, and
SystemC make it the choice for ASIC and FPGA design.
ModelSim eases the process of finding design defects with an intelligently engineered
debug environment. The ModelSim debug environment efficiently displays design data for
analysis and debug of all languages.
ModelSim allows many debug and analysis capabilities to be employed postsimulation on
saved results, as well as during live simulation runs. For example, the coverage viewer analyzes
and annotates source code with code coverage results, including FSM state and transition,
statement, expression, branch, and toggle coverage.
Signal values can be annotated in the source window and viewed in the waveform viewer,
easing debug navigation with hyperlinked navigation between objects and its declaration and
between visited files.
Race conditions, delta, and event activity can be analyzed in the list and wave windows.
Userdefined enumeration values can be easily defined for quicker understanding of simulation
results. For improved debug productivity, ModelSim also has graphical and textual dataflow
capabilities.
Procedure:
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count = 4b0000;
end
end
endmodule
SERIAL IN SERIAL OUT:
module siso(sout,sin,clk);
input sin,clk;
output sout;
reg sout;
always@(posedge clk)
begin
sout<=sin;
end
endmodule
SERIAL IN PARALLEL OUT:
module sipo(out,din,clk,clr);
input din,clk,clr;
output [3:0]out;
reg [3:0] out,t;
always@(negedge clk or clr)
begin
if(clr)
t<=4b0000;
else
begin
t<=t<<1;
t[0]<=din;
end
end
always@(*)
begin
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out<=t;
end
endmodule
PARALLEL IN SERIAL OUT:
module piso(out,din,clk,clr);
input clk,clr;
input [3:0] din;
output out;
reg[3:0] dint;
reg out;
reg[1:0]pst,nst;
always@(pst)
begin
case(pst)
2b00:begin dint<=din;out<=dint[0];nst<=2b01;end
2b01:begin out<=dint[1];nst<=2b10;end
2b10:begin out<=dint[2];nst<=2b11;end
2b11:begin out<=dint[3];
nst<=2boo;end
endcase
end
always@(negedge clr or clk)
begin
if(clr)
begin
out<=1b0;
pst<=2d0;
end
else
pst<=nst;
end
endmodule
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APPLICATIONS:
VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
7.
RESULT:
Thus the Sequential circuits are tested and implemented using Verilog
105