DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING

Coimbatore-641 105
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Course code
Semester / Year
Faculty Name

: EC6612 (C316)
:VI/III
:Mrs. Janeera.D.A

Course Name: VLSI Design Laboratory

Academic Year:2015-2016
Designation/ Dept.: Assistant Professor/ECE

Prerequisite:
1. Knowledge of Digital Electronics
2. Basic knowledge of VLSI design
Aim:
To implement VLSI circuits using HDL and design circuits on EDA platform.
Objective:
1. To learn Hardware Descriptive Language(Verilog/VHDL)
2. To learn the fundamental principles of VLSI circuit design in digital and analog domain
3. To familiarize fusing of logical modules on FPGAs
4. To provide hands on design experience with professional design (EDA) platforms.
Outcomes
Sl.
No.
1.
2.
3.
4.
5.

Code

Outcome

C316.1
C316.2
C316.3
C316.4
C316.5

Write HDL code for basic digital integrated circuits.

Write HDL code for advanced digital integrated circuits.
Import the logic modules into FPGA Boards.
Synthesize, Place and Route the digital IPs.
Design, Simulate and Extract the layouts of Analog IC Blocks using EDA tools.

PO-CO Mapping
CO
PO1
C316.1
2
C316.2
2
C316.3
2
C316.4
2
C316.5
2
C316
2

PO2
2
2
2
2
2
2

PO3
3
3
3
3
3
3

PO4
-

PO5
3
3
3
3
3
3

PO6
-

PO7
-

PO8
-

PO9
3
3
3
3
3
3

PO10
-

PO11
-

PO12
2
2
2
2
2
2

PSO1
3
3
3
3
3
3

PO-CO Mapping Justification

C316.1
PO1- The basic engineering knowledge is applied for basic digital integrated circuit coding
PO2- Performing the experiment allows easy analysis of problems.
PO3- Designing a system or process to meet the specific needs within the realistic constraints can be done.
PO5- Modern tools are used for the design & analysis of systems.
PO9- Experiments are done in teams to develop team work.
PO12- Practical knowledge inculcates inquisitiveness towards continuous learning.
PSO1- Hardware description coding for basic digital integrated circuits strengthens core engineering knowledge.
PSO2- Performing the experiments and Viva sessions allows effective communication of ideas.
C316.2
PO1- The basic engineering knowledge is applied for advanced digital integrated circuit coding
PO2- Performing the experiment allows easy analysis of problems.
PO3- Designing a system or process to meet the specific needs within the realistic constraints can be done.
PO5- Modern tools are used for the design & analysis of systems.
PO9- Experiments are done in teams to develop team work.
PO12- Practical knowledge inculcates inquisitiveness towards continuous learning.
PSO1- Hardware description coding for advanced digital integrated circuits strengthens core engineering knowledge.
PSO2- Performing the experiments and Viva sessions allows effective communication of ideas.
C316.3
PO1- The basic engineering knowledge is applied for importing the logic modules into FPGA Boards.
PO2- Performing the experiment allows easy analysis of problems.

PSO2
2
2
2
2
2
2

PO3- Designing a system or process to meet the specific needs within the realistic constraints can be done.
PO5- Modern tools are used for the design & analysis of systems.
PO9- Experiments are done in teams to develop team work.
PO12- Practical knowledge inculcates inquisitiveness towards continuous learning.
PSO1- Importing the logic modules into FPGA Boards strengthens core engineering knowledge.
PSO2- Performing the experiments and Viva sessions allows effective communication of ideas.
C316.4
PO1- The basic engineering knowledge is applied for synthesizing, placing and routing the digital IPs.
PO2- Performing the experiment allows easy analysis of problems.
PO3- Designing a system or process to meet the specific needs within the realistic constraints can be done.
PO5- Modern tools are used for the design & analysis of systems.
PO9- Experiments are done in teams to develop team work.
PO12- Practical knowledge inculcates inquisitiveness towards continuous learning.
PSO1- Synthesizing, placing and routing the digital IPs strengthens core engineering knowledge.
PSO2- Performing the experiments and Viva sessions allows effective communication of ideas.
C316.5
PO1- The basic engineering knowledge is applied for design, simulation and extraction of layouts of Analog IC Blocks using EDA
tools.
PO2- Performing the experiment allows easy analysis of problems.
PO3- Designing a system or process to meet the specific needs within the realistic constraints can be done.
PO5- Modern tools are used for the design & analysis of systems.
PO9- Experiments are done in teams to develop team work.
PO12- Practical knowledge inculcates inquisitiveness towards continuous learning.
PSO1- Design, simulation and extraction of layouts of Analog IC Blocks using EDA tools strengthens core engineering knowledge.
PSO2- Performing the experiments and Viva sessions allows effective communication of ideas.

Lab Schedule

Sl.
Cycle
No.

Topics

Planned
Date

Actual
Date

Knowledge
Level

Web Resources

Introduction to course and outcomes

Synthesis and Simulation of

a) Half adder, full adder, ripple
carry adder
b) Pipelined 12-bit serial and
parallel adder/subtractor
c) D-FF, T-FF and 4-bit Ripple
counter
d) Synchronous Up counter
using T-FF
e) 4 Bit Booths multiplier and
Shift and Add multiplier.
Analysis and Simulation of State
Machines

Synthesis, P&R and post P&R

simulation of counter circuits and
critical paths/ static timing analysis

a. Study of FPGA board and testing

on-board LEDs and switches
b. FPGA implementation and
verification of adder, multiplier

FPGA implementation of counter and

testing using Chip Scope Pro feature
P&R, power and clock routing, and
post P&R simulation of counter and
static timing analysis using TANNER
EDA tool
Layout generation and parasitic
extraction of Differential amplifier
circuit using TANNER EDA tool

28.01.2016
04.02.2016

K6

http://www.asicworld.com/vhdl/first1.html

03.03.2016

K6

http://www.iprogrammer.info/babbages-bag/223finite-state-machines.html

10.03.2016

K6

11.02.2016

18.02.2016

24.03.2016
K6
26.03.2016
31.03.2016

K6

02.04.2015

K6

07.04.2016

K6

10

11

Schematic entry and SPICE

simulation of CMOS using TANNER
EDA tool
Synthesis and standard cell based
design of counter circuit and power
using TANNER EDA tool
Static timing analysis using TANNER
EDA tool

Internal Assessments:
S.No
Test
1.
Model Practical Exam

23.04.2016

K6

28.04.2016

K6

30.04.2016

K6

Tentative dates
05.05.2016

Additional Activities Planned:

S.No
Activity
1.
VHDL coding tips and tricks tutorial

Mrs. Janeera.D.A
Faculty Incharge

http://tanner-tools-examples-andtutorials.software.informer.com/

Portions
All experiments

Tentative Date
28.01.2016

Dr.S.Malathy
HOD