Introduction to

CMOS VLSI
Design

Adders

Outline

Single-bit Addition
Carry-Ripple Adder
Carry-Skip Adder
Carry-Lookahead Adder
Carry-Select Adder
Carry-Increment Adder
Tree Adder

CMOS VLSI Design

Adders
Slide 2

Single-Bit Addition
A

Half Adder
S

Cout

Cout

Full Adder
S

Cout

A
Cout

Cout

C
S

CMOS VLSI Design

Cout S

Adders
Slide 3

Single-Bit Addition
A

Half Adder
S A B

Full Adder
S A B C

Cout

Cout AgB

Cout

Cout MAJ ( A, B, C )

C
S

Cout

Cout S

CMOS VLSI Design

Adders
Slide 4

PGK
For a full adder, define what happens to carries
Generate: Cout = 1 independent of C
G=
Propagate: Cout = C
P=
Kill: Cout = 0 independent of C
K=

CMOS VLSI Design

Adders
Slide 5

PGK
For a full adder, define what happens to carries
Generate: Cout = 1 independent of C
G =A B
Propagate: Cout = C
P = A B
Kill: Cout = 0 independent of C
K = ~A ~B

CMOS VLSI Design

Adders
Slide 6

Full Adder Design I

Brute force implementation from eqns

S A B C
Cout MAJ ( A, B, C )
A

S
MAJ

Cout

A
B
C
A
B
C

B
C

C
B
A

C
S

C
B

B
A

CMOS VLSI Design

A
B

Cout

Adders
Slide 7

Full Adder Design II

Factor S in terms of Cout
S = ABC + (A + B + C)(~Cout)
Critical path is usually C to Cout in ripple adder
MINORITY
A
B
C
Cout

Cout

CMOS VLSI Design

Adders
Slide 8

Layout
Clever layout circumvents usual line of diffusion
Use wide transistors on critical path
Eliminate output inverters

CMOS VLSI Design

Adders
Slide 9

Full Adder Design III

Complementary Pass Transistor Logic (CPL)
Slightly faster, but more area
B
B

A
A

A
S

S
A

Cout

Cout

B
B

CMOS VLSI Design

Slide
Adders
10

Full Adder Design IV

Dual-rail domino
Very fast, but large and power hungry
Used in very fast multipliers

C_h
A_h

B_h

Cout _h

A_h

C_l

B_h

A_l

B_l

B_l

S_l
C_h
B_h
A_h

C_l
B_l

Cout _l

A_l

S_h
C_h
B_h
A_l

CMOS VLSI Design

Slide
Adders
11

Carry Propagate Adders

N-bit adder called CPA
Each sum bit depends on all previous carries
How do we compute all these carries quickly?
AN...1 BN...1
Cout

Cout

+
SN...1

Cin

Cin

00000
1111
+0000
1111

CMOS VLSI Design

Cout

11111
1111
+0000
0000

Cin
carries
A4...1
B4...1
S4...1

Slide
Adders
12

Carry-Ripple Adder
Simplest design: cascade full adders
Critical path goes from Cin to Cout
Design full adder to have fast carry delay

A4

B4

Cout

A3

B3

C3
S4

A2

B2

C2
S3

A1

B1
Cin

C1
S2

CMOS VLSI Design

S1
Slide
Adders
13

Inversions
Critical path passes through majority gate
Built from minority + inverter
Eliminate inverter and use inverting full adder
A4

B4

Cout

A3

B3

C3
S4

A2

B2

C2
S3

A1

B1

Cin

C1
S2

CMOS VLSI Design

S1

Slide
Adders
14

Generate / Propagate
Equations often factored into G and P
Generate and propagate for groups spanning i:j
Gi: j
Pi: j

Base case
Gi:i Gi
Pi:i Pi

0 GCP

0:00:0 in

G0:0 G0
P0:0 P0

Sum:
Si
CMOS VLSI Design

Slide
Adders
15

Generate / Propagate
Equations often factored into G and P
Generate and propagate for groups spanning i:j
Gi: j Gi:k Pi:k gGk 1: j
Pi: j Pi:k gPk 1: j

Base case
Gi:i Gi Ai gBi
Pi:i Pi Ai Bi

0 GCP

0:00:0 in

G0:0 G0 Cin
P0:0 P0 0

Sum:
Si Pi Gi 1:0
CMOS VLSI Design

Slide
Adders
16

PG Logic
A4

B4

A3

B3

A2

B2

A1

B1

Cin

1: Bitwise PG logic
G4

P4

G3

P3

G2

P2

G1

P1

G0

P0

2: Group PG logic
G3:0

G2:0

G1:0

G0:0

C3

C2

C1

C0

3: Sum logic

C4
Cout

S4

S3

S2

S1

CMOS VLSI Design

Slide
Adders
17

Carry-Ripple Revisited
Gi:0 Gi Pi gGi 1:0
A4

B4

G4

P4

A3

B3

G3

P3

A2

B2

G2

P2

A1

B1

G1

P1

Cin

G0

G3:0

G2:0

G1:0

G0:0

C3

C2

C1

C0

P0

C4
Cout

S4

S3

S2

S1

CMOS VLSI Design

Slide
Adders
18

Carry-Ripple PG
Diagram
Bit Position

15

14

13

12

11

10

tripple

Delay

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
19

Carry-Ripple PG
Diagram
Bit Position

15

14

13

12

11

10

tripple t pg ( N 1)t AO txor

Delay

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
20

PG Diagram Notation
Black cell
i:k

Gray cell

k-1:j

i:k

i:j
Gi:k
Pi:k
Gk-1:j
Pk-1:j

Buffer

k-1:j

i:j

i:j

i:j
Gi:j

Gi:k
Pi:k
Gk-1:j

Pi:j

CMOS VLSI Design

Gi:j

Gi:j

Gi:j

Pi:j

Pi:j

Slide
Adders
21

Carry-Skip Adder
Carry-ripple is slow through all N stages
Carry-skip allows carry to skip over groups of n bits
Decision based on n-bit propagate signal

Cout

A16:13 B16:13

A12:9 B12:9

A8:5 B8:5

A4:1

P16:13

P12:9

P8:5

P4:1

1
0

C12
+
S16:13

1
0

C8
+

1
0

S12:9

CMOS VLSI Design

C4
+
S8:5

B4:1

1
0

Cin

S4:1

Slide
Adders
22

Carry-Skip PG Diagram
16

15

14

13

12

11

10

16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

For k n-bit groups (N = nk)

tskip
CMOS VLSI Design

Slide
Adders
23

Carry-Skip PG Diagram
16

15

14

13

12

11

10

16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

For k n-bit groups (N = nk)

tskip t pg 2 n 1 ( k 1) t AO txor
CMOS VLSI Design

Slide
Adders
24

Variable Group Size

16

15

14

13

12

11

10

16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Delay grows as O(sqrt(N))

CMOS VLSI Design

Slide
Adders
25

Carry-Lookahead Adder
Carry-lookahead adder computes Gi:0 for many bits
in parallel.
Uses higher-valency cells with more than two inputs.

A16:13 B16:13
Cout

G16:13
P16:13
+
S16:13

C12

A12:9 B12:9
G12:9
P12:9

A8:5 B8:5
C8

+
S12:9

CMOS VLSI Design

A4:1
C4

G8:5
P8:5

B4:1

G4:1
P4:1

S8:5

S4:1

Cin

Slide
Adders
26

CLA PG Diagram
16

15

14

13

12

11

10

16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
27

Higher-Valency Cells

i:k k-1:l l-1:m m-1:j

i:j

Gi:k
Pi:k
Gk-1:l
Pk-1:l
Gl-1:m
Pl-1:m
Gm-1:j

Gi:j

Pi:j

Pm-1:j

CMOS VLSI Design

Slide
Adders
28

Carry-Select Adder
Trick for critical paths dependent on late input X
Precompute two possible outputs for X = 0, 1
Select proper output when X arrives
Carry-select adder precomputes n-bit sums
For both possible carries into n-bit group
A16:13 B16:13

A12:9 B12:9

+
Cout
+

B8:5

C8

B4:1

C4
+

Cin

CMOS VLSI Design

+
1

S12:9

A4:1
0

S16:13

C12
1

A8:5

S8:5

S4:1

Slide
Adders
29

Carry-Increment Adder
Factor initial PG and final XOR out of carry-select
15

14

13

12

11

10

13:12

9:8

14:12
15:12

5:4

10:8
11:8

6:4
7:4

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

tincrement
CMOS VLSI Design

Slide
Adders
30

Carry-Increment Adder
Factor initial PG and final XOR out of carry-select
15

14

13

12

11

10

13:12

9:8

14:12
15:12

5:4

10:8
11:8

6:4
7:4

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

tincrement t pg n 1 (k 1) t AO txor
CMOS VLSI Design

Slide
Adders
31

Variable Group Size

Also buffer
noncritical
signals

15

14

13

12

11

10

12:11

8:7

13:11

5:4

9:7

14:11

3:2

6:4

10:7

15:11

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
15

14

13

12

11

10

12:11

8:7

13:11
14:11

9:7
10:7

5:4
6:4

3:2

1:0

3:0

6:0

15:11

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
32

Tree Adder
If lookahead is good, lookahead across lookahead!
Recursive lookahead gives O(log N) delay
Many variations on tree adders

CMOS VLSI Design

Slide
Adders
33

Brent-Kung
15 14 13 12 11 10

15:14

13:12

15:12

11:10

9:8

11:8

7:6

5:4

7:4

15:8

3:2

1:0

3:0

7:0

11:0
13:0

9:0

5:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
CMOS VLSI Design

Slide
Adders
34

Sklansky
15 14 13 12 11 10

15:14

13:12

11:10

15:12 14:12
15:8

14:8

11:8 10:8
13:8

9:8

7:6
7:4

5:4
6:4

3:2
3:0

1:0
2:0

12:8

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
35

Kogge-Stone
15 14 13 12 11 10

15:14 14:13 13:12 12:11 11:10 10:9

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

15:12 14:11 13:10

3:0

2:0

15:8

14:7

13:6

12:9

11:8 10:7

9:6

8:5

7:4

6:3

5:2

4:1

12:5

11:4 10:3

9:2

8:1

7:0

6:0

5:0

4:0

1:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
36

Tree Adder Taxonomy

Ideal N-bit tree adder would have
L = log N logic levels
Fanout never exceeding 2
No more than one wiring track between levels
Describe adder with 3-D taxonomy (l, f, t)
Logic levels:
L+l
Fanout:
2f + 1
Wiring tracks:
2t
Known tree adders sit on plane defined by
l + f + t = L-1
CMOS VLSI Design

Slide
Adders
37

Tree Adder Taxonomy

l (Logic Levels)

3 (7)
f (Fanout)

2 (6)
3 (9)

1 (5)

2 (5)
1 (3)
0 (2)

0 (4)
0 (1)

1 (2)

2 (4)

3 (8)

t (Wire Tracks)

CMOS VLSI Design

Slide
Adders
38

Tree Adder Taxonomy

l (Logic Levels)

3 (7)
f (Fanout)

Brent-Kung
2 (6)

Sklansky
3 (9)

1 (5)

2 (5)
1 (3)
0 (2)

0 (4)
0 (1)

1 (2)

2 (4)

Kogge-Stone
3 (8)

t (Wire Tracks)

CMOS VLSI Design

Slide
Adders
39

Han-Carlson
15 14 13 12 11 10

15:14

13:12

11:10

9:8

7:6

5:4

3:2

15:12

13:10

11:8

9:6

7:4

5:2

3:0

15:8

13:6

11:4

9:2

7:0

5:0

1:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
CMOS VLSI Design

Slide
Adders
40

Knowles [2, 1, 1, 1]
15 14 13 12 11 10

15:14 14:13 13:12 12:11 11:10 10:9

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

15:12 14:11 13:10

3:0

2:0

15:8

14:7

13:6

12:9

11:8 10:7

9:6

8:5

7:4

6:3

5:2

4:1

12:5

11:4 10:3

9:2

8:1

7:0

6:0

5:0

4:0

1:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
41

Ladner-Fischer
15 14 13 12 11 10

15:14

13:12

15:12

11:10

9:8

11:8

15:8

13:8

15:8

13:0

7:6

5:4

7:4

7:0

11:0

3:2

1:0

3:0

5:0

9:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
42

Taxonomy Revisited
(f)Ladner-Fischer
(b) Sklansky

15

15 14 13 12 11 10

14

15:14
15:14

13:12

11:10

15:12 14:12
15:8

14:8

9:8

7:6

11:8 10:8
13:8

7:4

5:4

3:2

6:4

3:0

l (Logic Levels)

2:0

15:0 14:0 13:0 12:0 11:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

15:14 14:13 13:12 12:11 11:10 10:9

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

15:12 14:11 13:10

9:6

8:5

7:4

6:3

5:2

4:1

3:0

2:0

15:8

14:7

13:6

12:9

12:5

11:8 10:7

11:4 10:3

9:2

8:1

7:0

6:0

5:0

15:14

0 (2)

9:8

7:6

5:4

3:2

13:0

7:4

1:0

0:0

1:0

3:0

7:0

11:0

5:0

9:0

9:0

8:0

7:0

6:0

5:0

4:0

3:0

2:0

13:12

11:10

9:8

7:6

11:8

5:4

3:2

7:4

15:8

1:0

3:0

7:0

11:0
9:0

5:0

1 (2)
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

HanCarlson

(d) Han-Carlson
15 14 13 12 11 10

(c) Kogge-Stone
15 14 13 12 11 10

13:6

13:8

15:8

15:12

HanCarlson

2 (4)

14:7

15:8

13:0

Knowles
[2,1,1,1]

15:8

11:8

New
(1,1,1)

Knowles
[4,2,1,1]

1:0

0 (4)
0 (1)

15:014:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

15:12 14:11 13:10

11:10

15 14 13 12 11 10

4:0

15:14 14:13 13:12 12:11 11:10 10:9

1 (5)
1 (3)

15:0 14:0 13:0 12:0 11:0 10:0

2 (5)

10

(a) Brent-Kung

2 (6)

(e) Knowles [2,1,1,1]

7

11

3 (7)

Sklansky
3 (9)

13:12

15:12

BrentKung

LadnerFischer

LadnerFischer

f (Fanout)

12

1:0

12:8

15 14 13 12 11 10

13

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

12:9

11:8 10:7

9:6

8:5

7:4

6:3

5:2

4:1

3:0

2:0

12:5

11:4 10:3

9:2

8:1

7:0

6:0

5:0

4:0

1:0

Kogge3 (8)
Stone

15:14

13:12

11:10

9:8

7:6

5:4

3:2

15:12

13:10

11:8

9:6

7:4

5:2

3:0

15:8

13:6

11:4

9:2

7:0

5:0

1:0

t (Wire Tracks)
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

15:0 14:0 13:0 12:0 11:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design

Slide
Adders
43

Summary
Adder architectures offer area / power / delay tradeoffs.
Choose the best one for your application.
Architecture

Classification Logic
Levels

Max
Tracks
Fanout

Cells

Carry-Ripple

N-1

Carry-Skip n=4

N/4 + 5

1.25N

Carry-Inc. n=4

N/4 + 2

2N

Brent-Kung

(L-1, 0, 0)

2log2N 1

2N

Sklansky

(0, L-1, 0)

log2N

N/2 + 1

0.5 Nlog2N

Kogge-Stone

(0, 0, L-1)

log2N

N/2

Nlog2N

CMOS VLSI Design

Slide
Adders
44