Compal La-7912p r0.2 Schematics

A
Compal Confidential
1
Model Name :Q5WV1/Q5WS1

Compal Project Name :
File Name : LA-7912P
Compal Confidential
2
Q5WV1 M/B Schematics Document

Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH
Nvidia N13P GS/GL
2011-12-24
REV:0.2
ZZZ2 1G@
ZZZ3 2G@
MB PCB
4
Part Number
Description
DA60000SV00
PCB 0N4 LA-7912P REV0 M/B
X76344BOL01
X76344BOL02
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Rev
4019ID
Sheet
Friday, January 06, 2012

E
of
60
Fan Control
page 42
100MHz
PEG(DIS)
PCI-E 2.0x16 5GT/s PER LANE
Nvidia
N13P GS/GL
Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Dual Channel
Intel
Sandy/Ivy Bridge
133MHz
page 11,12
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333
Processor
page22~30
eDP
rPGA989
page31
page 4~10
FDI x8
HDMI Conn.
page 33
CRT Conn.
LVDS Conn.
page 32
page 31
DMI x4
100MHz
100MHz
2.7GT/s
1GB/s x4
LVDS(UMA/OPTIMUS)
CRT(UMA/OPTIMUS)
TMDS(UMA/OPTIMUS)
Intel
Panther Point-M
USB 2.0 conn x2
Bluetooth
Conn
CMOS Camera
USB port 0,1 on

USB/B
page 38
USB port 13
USB port 10
page 38
USBx14
3.3V 48MHz
HD Audio
3.3V 24MHz
page 31
2
PCH
port 5
port 3
USB 3.0 conn x1

Fresco FL1009
with USB3.0 Conn.
MINI Card x1
WLAN
USB port 11 page 37
page 45
port 1
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
port 1
LAN(GbE) &
Card Reader
BCM57785
page
35,36
port 2
Card Reader
Conn. page 35,36
RJ45
USB port 8 page 34
page 36
port 0
ALC271X/281X
989pin BGA
100MHz
SATA HDD
Conn. page 34
MSATA(WWAN)
3
HDA Codec
100MHz
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
page 41
SPI
page 13~21
port 2
SPI ROM x1
Int. Speaker
page 13
SATA CDROM
Conn. page 34
page 41
Phone Jack x 2
page 41
LPC BUS
33MHz
ENE KB930/KB9012
page 39
RTC CKT.
page 13
Int.KBD
Touch Pad
page 40
Power On/Off CKT.

page 40
DC/DC Interface CKT.

4
page 40
Sub-board
LS-7911P
USB 2.0/B 2Port
USB Port0,1
BIOS ROM
page 39
page 40
page 43,44
LS-7912P
Power Circuit DC/DC
page 46~59
PWR/B
page 41
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

E
of
60
Voltage Rails
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.05VSDGPU
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.05VS_VTT
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
OFF
+1.05VS_PCH
+1.05VS_VCCP to +1.05VS_PCH power for PCH
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
Vcc
Ra/Rc/Re
+1.5VSDGPU
+1.5VS to +1.5VSDGPU switched power rail for GPU
ON
OFF
OFF
Board ID
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON
OFF
OFF
+1.8VSDGPU
+1.8VS to +1.8VSDGPU switched power rail for GPU
ON
OFF
OFF
+3VALW
+3VALW always on power rail
ON
ON
ON*
+3VALW_EC
+3VALW always to KBC
ON
ON
ON*
+3V_LAN
+3VALW to +3V_LAN power rail for LAN
ON
ON
ON*
+3VALW_PCH
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
ON
ON
ON*
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
0
1
2
3
4
5
6
7
+5VALW_PCH
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Full ON
Device
Address
Smart Battery
0001 011X b
Address
Clock Generator (9LVS3199AKLFT,

RTM890N-631-VB-GRT)
1101 0010b
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
+V
+VS
Clock
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
Board ID
0
1
2
3
4
5
6
7
Address
PCH SM Bus address

Device
+VALW
HIGH
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
BOARD ID Table
EC SM Bus2 address
Device
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
PCB Revision
0.1
0.2
0.3
0.4
USB Port Table

USB 2.0 USB 1.1 Port
UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
UHCI4
EHCI2
UHCI5
UHCI6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
2011/06/02
3 External
USB Port
USB3.0 colay USB2.0 Conn
USB/B (Right Side)
USB/B (Right Side)
BTO Item
UMA Only
Dis with OPTIMUS
Blue Tooth
Internal USB 3.0
eDP
VRAM
Connector
Unpop
N13P-GS
N13P-GL
Win8
Audio ALC271X
Audio ALC281X
PCH HM65
PCH HM76
BOM Structure
UMAO@
DIS@
BT@
PUSB@
eDP@
X76@
CONN@
@
GS@
GL@
Win8@
271X@
281X@
HM65@
HM76@
Camera
BlueTooth
4

2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Mini Card 1(WLAN)
Compal Secret Data
Issued Date
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
BTO Option Table
BT & USB30 & USB20 Config

N13P-GF108_ES4:GF108@
OPTMIUS SKU:DIS@ N13P-GL:GL@ N13P-GS:GS@
BT SKU:BT@
internal USB SKU: PUSB@
DIS USB30 SKU:DUSB@
eDP SKU: EDP@
LVDS SKU: LVDS@
EC 930 SKU: 930@ EC 9012 SKU: 9012@
PCH HM65: HM65@ PCH HM76: HM76@
Win8: WIN8@
Board ID / SKU ID Table for AD channel
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
SIGNAL
STATE
Rev
4019ID
Sheet

E
of
60
+1.05VS_VTT
1
R517
24.9_0402_1%
B27
B25
A25
B24
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
<15>
<15>
<15>
<15>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B28
B26
A24
B23
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
<15>
<15>
<15>
<15>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
<15>
<15>
<15>
<15>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
<15> FDI_FSYNC0
<15> FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
<15> FDI_INT
H20
FDI_INT
<15> FDI_LSYNC0
<15> FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
<31> EDP_AUXP
<31> EDP_AUXN
C15
D15
eDP_AUX
eDP_AUX#
<31> EDP_TXP0
<31> EDP_TXP1
C17
F16
C16
G15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
<31> EDP_TXN0
<31> EDP_TXN1
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
PCI EXPRESS* - GRAPHICS
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI
+1.05VS_VTT
R145
24.9_0402_1%
EDP_COMP
B
EDP_HPD#
Add eDP circuit
+1.05VS_VTT
PEG_COMP
PEG_ICOMPI and PEG_RCOMPO signals should be

shorted and routed,
max length = 500 mils,trace width=4mils
PEG_ICOMPO signals should be routed with - max
length = 500 mils,trace width=12mils
spacing =15mils
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0
C46
C49
C51
C53
C60
C71
C75
C82
C92
C93
C102
C111
C113
C125
C129
C144
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N15
PEG_GTX_HRX_N14
PEG_GTX_HRX_N13
PEG_GTX_HRX_N12
PEG_GTX_HRX_N11
PEG_GTX_HRX_N10
PEG_GTX_HRX_N9
PEG_GTX_HRX_N8
PEG_GTX_HRX_N7
PEG_GTX_HRX_N6
PEG_GTX_HRX_N5
PEG_GTX_HRX_N4
PEG_GTX_HRX_N3
PEG_GTX_HRX_N2
PEG_GTX_HRX_N1
PEG_GTX_HRX_N0
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0
C47
C50
C52
C56
C66
C68
C81
C86
C89
C100
C105
C106
C117
C119
C135
C138
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P15
PEG_GTX_HRX_P14
PEG_GTX_HRX_P13
PEG_GTX_HRX_P12
PEG_GTX_HRX_P11
PEG_GTX_HRX_P10
PEG_GTX_HRX_P9
PEG_GTX_HRX_P8
PEG_GTX_HRX_P7
PEG_GTX_HRX_P6
PEG_GTX_HRX_P5
PEG_GTX_HRX_P4
PEG_GTX_HRX_P3
PEG_GTX_HRX_P2
PEG_GTX_HRX_P1
PEG_GTX_HRX_P0
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0
C516
C520
C529
C534
C538
C540
C542
C544
C546
C548
C550
C552
C554
C556
C558
C560
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
0.22U_0402_10V6KPEG_HTX_C_GRX_N15
0.22U_0402_10V6K PEG_HTX_C_GRX_N9
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0
C515
C528
C533
C536
C539
C541
C543
C545
C547
C549
C551
C553
C555
C557
C559
C561
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
0.22U_0402_10V6KPEG_HTX_C_GRX_P15
0.22U_0402_10V6K PEG_HTX_C_GRX_P9
PEG_GTX_HRX_N[0..15] <22>
PEG_GTX_HRX_P[0..15] <22>
PEG_HTX_C_GRX_N[0..15] <22>
PEG_HTX_C_GRX_P[0..15] <22>
TYCO_2013620-2_IVY BRIDGE
CONN@
EDP@
R809
1K_0402_5%
eDP
eDP_COMPIO and ICOMPO signals should

be shorted near balls,
Trace Width for EDP_COMPIO=4mils,
EDP_ICOMPO=12mils,
and both length less than 500 mils...
should not be left floating
,even if disable eDP function...
Intel(R) FDI
JCPU1A
<15>
<15>
<15>
<15>
Typ- suggest 220nF. The change in AC capacitor

value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
<31> EDP_HPD#
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
of
60
AL33
CATERR#
Processor Pullups
+1.05VS_VTT
C
<18,40> H_PECI
R91 2
1 62_0402_5%
R92
56_0402_5%
1
2
H_PECI
AN33
PECI
H_PROCHOT#
<40,46> H_PROCHOT#
H_THRMTRIP#
<18> H_THRMTRIP#
H_PM_SYNC
<15> H_PM_SYNC
R84 2
H_PROCHOT#_R AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
1 10K_0402_5%
H_CPUPWRGD
<18> H_CPUPWRGD
UNCOREPWRGOOD:COREOK
PM_DRAM_PWRGD_R
V8
SM_DRAMPWROK
SM_DRAMPWROK:DRAM power ok
BUF_CPU_RST# AR33
RESET#
A28
A27
CLK_CPU_DMI
CLK_CPU_DMI#
DPLL_REF_CLK
DPLL_REF_CLK#
A16
A15
CLK_CPU_DPLL
CLK_CPU_DPLL#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
R8
SM_DRAMRST#
AK1
A5
A4
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>
For LVDS
CLK_CPU_DPLL <14>
For
CLK_CPU_DPLL# <14>
eDP
CLK_CPU_DPLL
CLK_CPU_DPLL#
R231
R566
R571
R516
R518
2 LVDS@ 1 1K_0402_5%
2 LVDS@ 1 1K_0402_5%
+1.05VS_VTT
If use External Graphic or

use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
SM_DRAMRST# <6>
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
2
2
2
DDR3 Compensation Signals
PRDY#
PREQ#
AP29
AP27
TCK
TMS
TRST#
AR26
AR27
AP30
TCK
TMS
TRST#
PAD
PAD
PAD
T66
T67
T68
TDI
TDO
AR28
AP26
TDI
TDO
PAD
PAD
T69
T70
@
@
@
+3VS
@
@
H_CATERR#
@
BCLK
BCLK#
R40
1K_0402_5%
2
PAD
THERMAL
T6
SKTOCC#
CLOCKS
AN34
DDR3
MISC
PROC_SELECT#
JTAG & BPM
C26
<17> H_SNB_IVB#
MISC
JCPU1B
PWR MANAGEMENT
SNB_IVB# had changed the name to

PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
DBR#
AL35
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_DBRESET#
XDP_DBRESET# <15>
CONN@
Buffered reset to CPU

+3VALW
+3VS
+1.5VS
PM_SYS_PWRGD_BUF
1
R204
2
130_0402_5%
PM_DRAM_PWRGD_R
1
5
B
@
R88
0_0402_5%
R203
39_0402_1%
C?
0.1U_0402_16V4Z
SN74LVC1G07DCKR_SC70-5
<15> PM_DRAM_PWRGD
BUF_CPU_RST#
200_0402_1%
<15> SYS_PWROK
R87
43_0402_1%
1
2
BUFO_CPU_RST#
U11
74AHC1G09GW_TSSOP5
5
2
PLT_RST#
Y
3
<17> PLT_RST#
R90
75_0402_1%
U7
NC
R205
+1.05VS_VTT
C162
0.1U_0402_16V4Z
C307
0.1U_0402_16V4Z
RESET#:okCPUreset
R04 modify
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
of
60
JCPU1D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AE10
AF10
V6
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
SA_CAS#
SA_RAS#
SA_WE#
<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_WE#
DDR SYSTEM MEMORY A
<11> DDR_A_D[0..63]
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
AB6
AA6
V9
SA_CLK_DDR0 <11> <12> DDR_B_D[0..63]

SA_CLK_DDR#0 <11>
DDRA_CKE0_DIMMA <11>
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
AA5
AB5
V10
SA_CLK_DDR1 <11>
SA_CLK_DDR#1 <11>
DDRA_CKE1_DIMMA <11>
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
AB4
AA4
W9
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
AB3
AA3
W10
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
AK3
AL3
AG1
AH1
DDRA_CS0_DIMMA# <11>
DDRA_CS1_DIMMA# <11>
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
AH3
AG3
AG2
AH2
SA_ODT0 <11>
SA_ODT1 <11>
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
C4
G6
J3
M6
AL6
AM8
AR12
AM15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
<11>
<11>
<11>
<12> DDR_B_BS0
<12> DDR_B_BS1
<12> DDR_B_BS2
<12> DDR_B_CAS#
<12> DDR_B_RAS#
<12> DDR_B_WE#
CONN@
2
1
R186
4.99K_0402_1%
C2065
0.1U_0402_16V4Z
for ESD
DIMM_DRAMRST#_R
1
Q12
S TR SSM3K7002F 1N SC59-3
<11,12,14> RST_GATE
1
AA9
AA7
R6
SB_BS[0]
SB_BS[1]
SB_BS[2]
AA10
AB8
AB9
SB_CAS#
SB_RAS#
SB_WE#
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
AE2
AD2
R9
SB_CLK_DDR0 <12>
SB_CLK_DDR#0 <12>
DDRB_CKE0_DIMMB <12>
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
AE1
AD1
R10
SB_CLK_DDR1 <12>
SB_CLK_DDR#1 <12>
DDRB_CKE1_DIMMB <12>
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
AB2
AA2
T9
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
AA1
AB1
T10
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
AD3
AE3
AD6
AE6
DDRB_CS0_DIMMB# <12>
DDRB_CS1_DIMMB# <12>
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
AE4
AD4
AD5
AE5
SB_ODT0 <12>
SB_ODT1 <12>
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
<12>
<12>
<12>
CONN@
C293
0.047U_0402_16V7K
R155
1K_0402_5%
2
DIMM_DRAMRST# <11,12>
S0
RST_GATE hgih ,MOS ON
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
S3
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
S4,5
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# low
Dimm reset
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
DDR_B_DQS#[0..7]
R217
1K_0402_5%
R02 modify
SM_DRAMRST#
2
<5> SM_DRAMRST#
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
@R184
@
R184
0_0402_5%
1
2
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
+1.5V
Follow CRB1.0
CPUDIMMreset
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR SYSTEM MEMORY B
JCPU1C
Rev
4019ID
Sheet

1
of
60
CFG Straps for Processor
CFG2
Ivy
VSS_DIE_SENSE
GND
JCPU1E
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
L7
AG7
AE7
AK2
RSVD32
W8
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
RSVD37
RSVD38
RSVD39
RSVD40
T8
J16
H16
G16
PAD
PAD
1: Normal Operation; Lane #

socket pin map definition
CFG2
T7
T74
CFG4
R813
@
49.9_0402_1%
R109
1K_0402_5%
CFG4
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
J20
B18
RSVD24
RSVD25
J15
RSVD27
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
0 : Enabled; An external Display Port device is

connected to the Embedded Display Port
RSVD5
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
EDP@
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
AR35
AT34
AT33
AP35
AR34
CFG6
CFG5
GM@
R107
1K_0402_5%
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
B34
A33
A34
B35
C35
@
2
AJ26
definition matches
0:Lane Reversed
RSVD28
RSVD29
RSVD30
RSVD31
@
@
Display Port Presence Strap
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
R812
@
49.9_0402_1%
1
AJ31
AH31
AJ33
AH33
AH27
AH26
R811
@
49.9_0402_1%
1
R810
@
49.9_0402_1%
RESERVED
+CPU_CORE +VGFX_CORE
VCC_DIE_SENSE
VSS_DIE_SENSE
CFG4
CFG5
CFG6
CFG7
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG2
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG0
R108
1K_0402_5%
PAD
@
PEG Static Lane Reversal - CFG2 is for the 16x
AH27 change to VCC_DIE_SENSE
CFG
T8
R112
1K_0402_5%
2
Sandy
AH26
PCIE Port Bifurcation Straps

RSVD51
RSVD52
AJ32
AK32
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
BCLK_ITP
BCLK_ITP#
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AN35
AM35
RSVD54 and RSVD55 had changed to

BCLK_ITP and BCLK_ITP#
AT2
AT1
AR1
CFG7
B1
KEY
*10: x8, x8 - Device 1 function 1 enabled ; function 2
R102
1K_0402_5%
@
2
CONN@
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB

de assertion
0: PEG Wait for BIOS for training
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
of
60
JCPU1F
QC 53A
DC 53A
PEG AND DDR
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
VCCIO40
J23
+1.05VS_VTT
+1.05VS_VTT
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
R447
75_0402_5%
2
R450
130_0402_1%
R448
43_0402_1%
1
2
R446 1
2 0_0402_5%
R449 1
2 0_0402_5%
VR_SVID_ALRT# <52>
VR_SVID_CLK <52>
VR_SVID_DAT <52>
Place the PU
resistors close to CPU
+CPU_CORE
R445
100_0402_1%
VCC_SENSE
VSS_SENSE
AJ35 VCCSENSE_R
AJ34 VSSSENSE_R
R444 1
R443 1
1
R910
VCCIO_SENSE
VSS_SENSE_VCCIO
CONN@
B10
A10
0_0402_5%
0_0402_5%
VCCSENSE <52>
VSSSENSE <52>
R442
100_0402_1%
VCCIO_SENSE <50>
VSSIO_SENSE <50>
VSSIO_SENSE
VSSIO_SENSE
change to
VSS_SENSE_VCCIO
2
2
2
+1.05VS_VTT
10_0402_5%
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
SVID
+1.05VS_VTT
8.5A
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
SENSE LINES
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
CORE SUPPLY
+CPU_CORE
POWER
R163
10_0402_5%
Should change to connect form

power cirucit & layout differential
with VCCIO_SENSE.
SV type CPU
Compal Secret Data
Issued Date
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
of
60
QC 46A
DC 33A
+V_SM_VREF
AL1
C688
0.1U_0402_16V4Z
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SA_DIMM_VREFDQ <11>
SB_DIMM_VREFDQ <12>
SA RAIL
A19
2
2
INTEL Recommend
1*330uF,3*10uF
from CR PDDG 0.8
@
2 0_0402_5%
+VCCSA_SENSE
1
+ C221
@
330U_D2_2V_Y
VCCSA
+VCCSA_SENSE <51>
H_VCCSA_VID0
H_VCCSA_VID1
VID0
VID1
Vout
Sandy
0.9V
Ivy
V
0.8V
0.725V
0.675V
H_VCCSA_VID0 <51>
H_VCCSA_VID1 <51>
1
MISC
VCCIO_SEL
R137 1
C829
10U_0603_6.3V6M
VCCSA_VID[0]
VCCSA_VID[1]
C22
C24
+VCCSA
C828
10U_0603_6.3V6M
H23
+VCCSA
M27
M26
L26
J26
J25
J24
H26
H25
VCCSA_SENSE
INTEL Recommend
1*330uF,6*10uF
from CR PDDG 0.8
+1.5VS
5A
6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
R575
1K_0402_1%
C355
330U_D2_2V_Y
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
B4
D1
C361
10U_0603_6.3V6M
DDR3 -1.5V RAILS
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
C365
10U_0603_6.3V6M
GRAPHICS
VREF
SM_VREF
SENSE
LINES
+V_SM_VREF should
have 20 mil trace width
C213
10U_0603_6.3V6M
VCCIO_SEL
R138
0_0402_5%
@
CONN@
R582
1K_0402_1%
10_0402_5%
C341
10U_0603_6.3V6M
+1.5VS
R904
C219
10U_0603_6.3V6M
VCCPLL1
VCCPLL2
VCCPLL3
VCC_AXG_SENSE <52>
VSS_AXG_SENSE <52>
C362
10U_0603_6.3V6M
C653
1U_0402_6.3V6K
C654
1U_0402_6.3V6K
C655
10U_0603_6.3V6M
C830
10U_0603_6.3V6M
B6
A6
A2
AK35
AK34
C605
10U_0603_6.3V6M
+VCCPLL
1
C831
10U_0603_6.3V6M
2
0_0805_5%
C664
330U_D2_2V_Y
1
R528
1.2A
VAXG_SENSE
VSSAXG_SENSE
C364
10U_0603_6.3V6M
+1.8VS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
C214
10U_0603_6.3V6M
INTEL Recommend
1*330uF,1*10uF and 2*1uF(0402)
from CR PDDG 0.8
10_0402_5%
C363
10U_0603_6.3V6M
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
R903
JCPU1G
POWER
1.8V RAIL
+VGFX_CORE
+VGFX_CORE
+3VALW
R909
10K_0402_5%
1/NC : (Default) +1.05VS_VTT
A19
For 2012 CPU support
0: +1.0VS_VTT
VCCIO_SEL
RSVD26 had changed the name to VCCIO_SEL

Need PH +3VALW 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select
R913
10K_0402_5%
@
A
VCCIO_SEL
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
of
60
JCPU1H
D
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPU1I
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
CONN@
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
CONN@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
10
of
60
+1.5V
R320
1K_0402_5%
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D24
DDR_A_D25
DDR_A0_DM3
<6> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
<6> DDR_A_WE#
<6> DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDRA_CS1_DIMMA#
<6> DDRA_CS1_DIMMA#
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A0_DM7
DDR_A_D58
DDR_A_D59
+3VS
2
1
R301
10K_0402_5%
R302
10K_0402_5%
DIMM_1 Reserve H:8mm
C416
2.2U_0603_6.3V6K
C404
0.1U_0402_16V4Z
<Address(SA1,SA0): 00>
+0.75VS
205
G1
G2
206
DDRA_CKE1_DIMMA
DDRA_CKE1_DIMMA <6>
DDR_A_MA15
DDR_A_MA14
+1.5V
DDR_A_MA6
DDR_A_MA4
CHG C407 to oscon
DDR_A_MA2
DDR_A_MA0
1
SA_CLK_DDR1
SA_CLK_DDR#1
SA_CLK_DDR1 <6>
SA_CLK_DDR#1 <6>
+1.5V
2
DDR_A_BS1
DDR_A_RAS#
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDRA_CS0_DIMMA#
SA_ODT0
DDRA_CS0_DIMMA# <6>
SA_ODT0 <6>
SA_ODT1
SA_ODT1 <6>
1
+
2
R267
1K_0402_5%
+VREF_CA
DDR_A_D36
DDR_A_D37
1
DDR_A0_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
+0.75VS
R266
1K_0402_5%
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
Layout Note:
Place near JDIMM1.203,204
DDR_A_D52
DDR_A_D53
DDR_A0_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A0_DM0
DDR_A0_DM1
DDR_A0_DM2
DDR_A0_DM3
DDR_A0_DM4
DDR_A0_DM5
DDR_A0_DM6
DDR_A0_DM7
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA <12,14,41>
D_CK_SCLK <12,14,41>
+0.75VS
FOX_AS0A626-U8SN-7F
CONN@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Date:
DDR_A_MA11
DDR_A_MA7
Custom
5
C388
1U_0402_6.3V6K
DDR_A_D42
DDR_A_D43
C394
1U_0402_6.3V6K
DDR_A0_DM5
DDR_A_D30
DDR_A_D31
C395
1U_0402_6.3V6K
DDR_A_D40
DDR_A_D41
+1.5V
DDR_A_DQS#3
DDR_A_DQS3
C393
1U_0402_6.3V6K
DDR_A_D34
DDR_A_D35
for ESD
C373
0.1U_0402_16V4Z
DDR_A_DQS#4
DDR_A_DQS4
R02 modify
DDR_A_D28
DDR_A_D29
C372
2.2U_0603_6.3V6K
DDR_A_D32
DDR_A_D33
DDR_A_D22
DDR_A_D23
C407
330U_D2_2V_Y
DDR_A_MA10
DDR_A_BS0
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A0_DM2
C383
10U_0603_6.3V6M
<6> DDR_A_BS0
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_A_D20
DDR_A_D21
C412
10U_0603_6.3V6M
SA_CLK_DDR0
SA_CLK_DDR#0
<6> SA_CLK_DDR0
<6> SA_CLK_DDR#0
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR_A_D14
DDR_A_D15
C413
10U_0603_6.3V6M
DDR_A_MA3
DDR_A_MA1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
C414
10U_0603_6.3V6M
DDR_A_BS2
+1.5V
DDR_A0_DM1
DDR3_DRAMRST#
C415
10U_0603_6.3V6M
DDRA_CKE0_DIMMA
<6> DDRA_CKE0_DIMMA
DDR_A_D12
DDR_A_D13
C378
10U_0603_6.3V6M
Layout Note:
Place near JDIMM1
C384
10U_0603_6.3V6M
DDR_A_D26
DDR_A_D27
DDR_A_D6
DDR_A_D7
C409
1U_0402_6.3V6K
DDR_A_D18
DDR_A_D19
DDR_A_DQS#0
DDR_A_DQS0
C410
1U_0402_6.3V6K
DDR_A_DQS#2
DDR_A_DQS2
<6>
DDR_A_MA[0..15] <6>
C385
1U_0402_6.3V6K
DDR_A_D16
DDR_A_D17
DDR_A_D[0..63]
DDR_A_D4
DDR_A_D5
C371
1U_0402_6.3V6K
DDR_A_D10
DDR_A_D11
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C2066
0.1U_0402_16V4Z
All VREF traces should

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
<6>
DDR_A0_DM0
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
<6>
DDR_A_DQS[0..7]
<6,12,14> RST_GATE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C411
0.1U_0402_16V4Z
R319
1K_0402_5%
1
Q46
DDR_A_D0
DDR_A_D1
+V_DDR_REFA
C408
2.2U_0603_6.3V6K
S
3
D
+1.5V
JDIMM1
<9> SA_DIMM_VREFDQ
DDR_A_DQS#[0..7]
+1.5V
@ R133
0_0402_5%
1
2
M3 support
Rev
4019ID
Sheet

1
11
of
60
+1.5V
+1.5V
DDR_B0_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
<6,11,14> RST_GATE
DDR_B_DQS#1
DDR_B_DQS1
All VREF traces should

DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_D26
DDR_B_D27
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_CS1_DIMMB#
<6> DDRB_CS1_DIMMB#
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
+3VS
R344
10K_0402_5%
DDR_B0_DM7
DDR_B_D58
DDR_B_D59
+3VS
DIMM_2 Reserve H:4mm
R345
10K_0402_5%
C436
2.2U_0603_6.3V6K
<Address(SA1,SA0): 10>
C435
0.1U_0402_16V4Z
+0.75VS
205
G1
G2
206
DDR_B_D30
DDR_B_D31
+1.5V
DDRB_CKE1_DIMMB
DDRB_CKE1_DIMMB <6>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
+1.5V
SB_CLK_DDR1
SB_CLK_DDR#1
SB_CLK_DDR1 <6>
SB_CLK_DDR#1 <6>
DDR_B_BS1
DDR_B_RAS#
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDRB_CS0_DIMMB#
SB_ODT0
DDRB_CS0_DIMMB# <6>
SB_ODT0 <6>
SB_ODT1
SB_ODT1 <6>
CHG C359 to oscon

+1.5V
1
R351
1K_0402_5%
1
+
2
+VREF_CC
DDR_B_D36
DDR_B_D37
1
DDR_B0_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
R350
1K_0402_5%
+0.75VS
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
Layout Note:
Place near JDIMM2.203,204
DDR_B0_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B0_DM0
DDR_B0_DM1
DDR_B0_DM2
DDR_B0_DM3
DDR_B0_DM4
DDR_B0_DM5
DDR_B0_DM6
DDR_B0_DM7
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA <11,14,41>
D_CK_SCLK <11,14,41>
+0.75VS
FOX_AS0A626-U4RN-7F
CONN@
Compal Secret Data
Issued Date
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Date:
DDR_B_DQS#3
DDR_B_DQS3
Custom
5
C428
1U_0402_6.3V6K
DDR_B_D42
DDR_B_D43
C439
1U_0402_6.3V6K
DDR_B0_DM5
DDR_B_D28
DDR_B_D29
C427
1U_0402_6.3V6K
DDR_B_D40
DDR_B_D41
DDR_B_D22
DDR_B_D23
C440
1U_0402_6.3V6K
DDR_B_D34
DDR_B_D35
DDR_B0_DM2
C446
0.1U_0402_16V4Z
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D20
DDR_B_D21
C451
2.2U_0603_6.3V6K
DDR_B_D32
DDR_B_D33
Layout Note:
Place near JDIMM2
+1.5V
C359
330U_2.5V_M
<6> DDR_B_WE#
<6> DDR_B_CAS#
DDR_B_D14
DDR_B_D15
C426
10U_0603_6.3V6M
<6> DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
DDR_B0_DM1
DDR3_DRAMRST#
C447
10U_0603_6.3V6M
SB_CLK_DDR0
SB_CLK_DDR#0
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_MA[0..15] <6>
C448
10U_0603_6.3V6M
<6> SB_CLK_DDR0
<6> SB_CLK_DDR#0
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
<6>
<6>
C449
10U_0603_6.3V6M
DDR_B_MA12
DDR_B_MA9
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR_B_D12
DDR_B_D13
C450
10U_0603_6.3V6M
<6> DDR_B_BS2
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_D[0..63]
C425
10U_0603_6.3V6M
DDR_B_BS2
<6>
DDR_B_DQS[0..7]
C424
10U_0603_6.3V6M
DDRB_CKE0_DIMMB
<6> DDRB_CKE0_DIMMB
C
DDR_B_DQS#[0..7]
DDR_B_D6
DDR_B_D7
C429
1U_0402_6.3V6K
DDR_B0_DM3
DDR_B_DQS#0
DDR_B_DQS0
C430
1U_0402_6.3V6K
DDR_B_D24
DDR_B_D25
DDR_B_D4
DDR_B_D5
C444
1U_0402_6.3V6K
DDR_B_D18
DDR_B_D19
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C445
1U_0402_6.3V6K
DDR_B_DQS#2
DDR_B_DQS2
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
1
Q47
@
DDR_B_D0
DDR_B_D1
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
S
3
R340
1K_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
1
C437
0.1U_0402_16V4Z
@R346
@
R346
0_0402_5%
1
2
C438
2.2U_0603_6.3V6K
M3 support
<9> SB_DIMM_VREFDQ
+1.5V
JDIMM2
+V_DDR_REFC
R341
1K_0402_5%
Rev
4019ID
Sheet

1
12
of
60
+RTCVCC
PCH_RTCX1
+3VS
+RTCBATT
+RTCBATT
SM_INTRUDER#
R585 1
2 330K_0402_5%
PCH_INTVRMEN
1
R568
PCH_SPKR
3 1
D13
SERIRQ
R275
1 10K_0402_5%
PCH_SATALED#
R640
1 10K_0402_5%
R624 1
2 4.7K_0402_5%
JBATT1
PCH_GPIO19
+RTCBATT_R
20mil
D
This part had been re-modified

be careful,if link symbol!!+3VS
+RTCVCC
20mil
R04 modify
1
HIGH= Enable ( No Reboot )

LOW= Disable (Default)
2 1K_0402_5%
CONN@
CHN202UPT_SC70-3
C471
+3VS
32.768KHZ_12.5PF_9H03200019
1
1
C686
C682
15P_0402_50V8J
15P_0402_50V8J
(INTVRMEN should always be pull high.)

D
+CHGRTC
Y3
HIntegrated VRM enable

LIntegrated VRM disable
R294 1
PCH_RTCX2
R375
1K_0402_5%
INTVRMEN
2
10M_0402_5%
2 1M_0402_5%
R567 1
SUYIN_060003HA002G202ZL
U36
PCH_SPI_CS0#_1
SPI_WP1#
SPI_HOLD1#
0.1U_0402_16V4Z
1
3
7
4
+3VALW_PCH
R556
1K_0402_5%
@
2
1
R557
0_0402_5%
2
1
R02 Modify
<40> ME_EN
SPI ROM FOR ME (4MB)

Footprint 200mil
K22
INTRUDER#
PCH_INTVRMEN
C17
INTVRMEN
HDA_BITCLK_PCH
N34
HDA_BCLK
HDA_SYNC_PCH
L34
HDA_SYNC
PCH_SPKR
T10
SPKR
HDA_RST_PCH#
K34
HDA_RST#
HDA_SDIN0
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
SRTCRST close RAM door

<42> PCH_SPKR
<42> HDA_SDIN0
HDA_SDOUT_PCH
Prevent back drive issue.

G
+3VS
B
HDA_SYNC_PCH_R
S
1
@ R674
51_0402_5%
2
1
Q36
1HDA_SYNC_PCH
@
R540
0_0402_5%
PAD
T75 @
PAD
T76 @
PAD
T77 @
PCH_JTAG_TCK
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
LPC_FRAME#
JTAG_TCK
PCH_JTAG_TMS
H7
JTAG_TMS
PCH_JTAG_TDI
K5
JTAG_TDI
PCH_JTAG_TDO
H1
JTAG_TDO
R04 modify
PCH_SPI_CLK_2
2 WIN8@ 1
R734
33_0402_5%
PCH_SPI_CLK_1
1
2 PCH_SPI_CLK
R681
33_0402_5%
PCH_SPI_CS0#_1
PCH_SPI_CS0#_2
PCH_SPI_MOSI_2 2 WIN8@ 1
R733
33_0402_5%
PCH_SPI_MOSI_1 1
2 PCH_SPI_MOSI
R684
33_0402_5%
PCH_SPI_MISO_1 1
2 PCH_SPI_MISO
R652
33_0402_5%
PCH_SPI_MISO_2 1 WIN8@ 2
R2050
33_0402_5%
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
U3
SPI_MOSI
SPI_MISO
+3VS
U42 WIN8@
PCH_SPI_CS0#_2
SPI_WP2#
SPI_HOLD2#
E36
K36
SERIRQ
V5
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
<34>
<34>
<34>
<34>
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AM10
AM8
AP11
AP10
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
<37>
<37>
<37>
<37>
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
<34>
<34>
<34>
<34>
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
HDD
MSATA
PCH_SPI_CLK_2
ODD
C2049
33P_0402_50V8K
+3VS
B
SATAICOMPO
Y11
SATAICOMPI
Y10
SATA_COMP
AB12
R260
37.4_0402_1%
1
2
SATA3COMPI
AB13
SATA3RBIAS
AH1
PCH_SATALED#
SATA0GP / GPIO21
SGEN#
SATA1GP / GPIO19
P1
PCH_GPIO19
R259
10K_0402_5%
+1.05VS_VTT
+1.05VS_VTT
R241
49.9_0402_1%
SATA3_COMP1
2
R625
750_0402_1%
RBIAS_SATA3 1
2
P3
SGEN#
R258
10K_0402_5%
@
GPIO21
PCH_SATALED# <41>
SGEN#
Switchable GPU
* Non-Switchable
COUGARPOINT_FCBGA989~D
HM65@
SA00004EEY0
SA00005AGE0
2011/06/02
Compal Secret Data
0
1
Boot BIOS Strap

Boot BIOS
GPIO51 GPIO19
0
0
LPC
1
0
Reserved
0
1
1
1
* SPI
U33
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Modify R04
Delete Co-lay NPCE885N
BD82HM77 QPRG C1 BGA 989P

HM77@
PCH_SPI_VCC
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_MISO_2
8
6
5
2
@1 R2048 2
22_0402_5%
Modify R03
Co-lay NPCE885N
VCC
SCLK
SI
SO
SPI_HOLD2#
R703 1 WIN8@ 2
3.3K_0402_5%
SPI_WP2#
R704 1
WIN8@
2
3.3K_0402_5%
+3VS
V14
Issued Date
CS#
WP#
HOLD#
GND
MX25L1606EM2I-12G_SO8
AM3
AM1
AP7
AP5
SATALED#
1
3
7
4
Modify R02
SERIRQ <40>
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA3RCOMPO
R792
1M_0402_5%
Rserve the 2M ROM for Win8
LPC_FRAME# <40>
SM_INTRUDER#
D36
<40>
<40>
<40>
<40>
SRTCRST#
FWH4 / LFRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
G22
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
2
@
@
22_0402_5% 33P_0402_50V8K
RTCRST#
C38
A38
B37
C37
LPC
D20
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
SATA 6G
PCH_RTCRST#
RTC
1
2
RTCX2
SATA
<42> HDA_RST_AUDIO#
<42> HDA_SDOUT_AUDIO
RTCX1
C20
IHDA
<42> HDA_SYNC_AUDIO
A20
PCH_RTCX2
JTAG
<42> HDA_BITCLK_AUDIO
R544
33_0402_5%
1
2 HDA_BITCLK_PCH
R542
33_0402_5%
1
2 HDA_SYNC_PCH_R
R545
33_0402_5%
1
2 HDA_RST_PCH#
R555
33_0402_5%
1
2 HDA_SDOUT_PCH
C356
1U_0603_10V6K
On Die PLL VR Select is supplied by

1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
PCH_RTCX1
SPI
PCH_SRTCRST#
C360
1U_0603_10V6K
2
1
2
R248 20K_0402_1%
1
2
R243 20K_0402_1% 1
U33A
JME1
SHORT PADS
JCMOS1
SHORT PADS
This signal has a weak internal pull-down
2 3.3K_0402_5% SPI_WP1#
2 3.3K_0402_5% SPI_HOLD1#
R866
C893
PCH_SPI_CLK_1
+RTCVCC
1 1K_0402_5% HDA_SYNC_PCH
R654 1
R667 1
+3VS
RTCRST close RAM door
+3VALW_PCH
2
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
32M W25Q32BVSSIG_SO8
ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
R539
8
6
5
2
VCC
SCLK
SI/SIO0
SO/SIO1
HDA_SDOUT_PCH
HDA_SDO as Capella ME override (GPIO33)
CS#
WP#
HOLD#
GND
Rev
4019ID
Sheet

1
13
of
60
+3VALW_PCH
U33B
PERN3
PERP3
PETN3
PETP3
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
+3VS
2
1 10K_0402_5%
MINI1_CLKREQ#
R273
1 10K_0402_5%
USB30_CLKREQ#
+3VALW_PCH
1 10K_0402_5%
PCH_GPIO73
1 10K_0402_5%
LAN_CLKREQ#
1 10K_0402_5%
MINI2_CLKREQ#
R238
1 10K_0402_5%
PCH_GPIO44
R293
1 10K_0402_5%
PCH_GPIO45
R295
1 10K_0402_5%
PCH_GPIO46
R618
R630
R653
Y40
Y39
PCH_GPIO73
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
<37> CLK_PCIE_MINI1#
<37> CLK_PCIE_MINI1
Mini Card 1(WLAN)
MINI1_CLKREQ#
<37> MINI1_CLKREQ#
J2
AB49
AB47
PCH_SMBCLK
C9
PCH_SMBDATA
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SML1ALERT# / PCHHOT# / GPIO74
C13
PCH_GPIO74
SML1CLK / GPIO58
E14
PCH_SML1CLK
SML1DATA / GPIO75
M16
PCH_SML1DATA
R608
1 1K_0402_5%
PCH_SMBDATA <37>
PCH_SMBCLK
R677
2.2K_0402_5%
PCH_SMBDATA
R662
RST_GATE <6,11,12>
2.2K_0402_5%
PCH_GPIO74
R647
10K_0402_5%
PCH_SML1CLK
R642
2.2K_0402_5%
PCH_SML1DATA
R643
2.2K_0402_5%
PCH_GPIO47
R280
10K_0402_5%
M1
AA48
AA47
CL_DATA1
CL_RST1#
M7
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
P10
M10
PCIECLKRQ2# / GPIO20
CLK_PCIE_LAN#
CLK_PCIE_LAN
Y37
Y36
CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCH_GPIO44
PEG_CLKREQ#_R
PCH_GPIO45
PCH_GPIO46
A8
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM12
AM13
CLK_CPU_DPLL#
CLK_CPU_DPLL
CLKIN_DMI_N
CLKIN_DMI_P
BF18
BE18
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R233 1
R234 1
2 10K_0402_5%
2 10K_0402_5%
CLKIN_DMI2_N
CLKIN_DMI2_P
BJ30
BG30
CLKIN_GND1#
CLKIN_GND1
R563 1
R561 1
2 10K_0402_5%
2 10K_0402_5%
CLKIN_DOT_96N
CLKIN_DOT_96P
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R220 1
R221 1
2 10K_0402_5%
2 10K_0402_5%
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
AK7
AK5
CLK_BUF_PCIE_SATA# R264 1
CLK_BUF_PCIE_SATA R265 1
2 10K_0402_5%
2 10K_0402_5%
REFCLK14IN
K45
CLK_BUF_ICH_14M
2 10K_0402_5%
CLKIN_PCILOOPBACK
H45
CLK_PCI_LPBACK
XTAL25_IN
XTAL25_OUT
V47
V49
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
Y47
XCLK_RCOMP
Y43
Y45
CLKOUT_PCIE4N
CLKOUT_PCIE4P
L12
V45
V46
CLKOUT_PCIE5N
CLKOUT_PCIE5P
L14
AB42
AB40
E6
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
CLK_CPU_DPLL# <5>
CLK_CPU_DPLL <5>120
R175 1
MHz for eDP
PCH_SML1DATA 6
CLKOUT_PCIE6N
CLKOUT_PCIE6P
T13
V38
V37
CLKOUT_PCIE7N
CLKOUT_PCIE7P
K12
Pull down 10K ohm

for using internal Clock
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
XTAL25_OUT
R527 1
K43
CLK_FLEX0
F47
CLK_FLEX1
CLKOUTFLEX2 / GPIO66
H47 CLK_FLEX2
K49
T9
PAD
T73
PAD
T29
PAD
2 1M_0402_5%
+1.05VS_VTT
3
GND
2
2
@R530
@
R530
33_0402_5%
2
1
DGPU_PRSNT#
+3VS
1
UMAO@
R159
10K_0402_5%
GPIO67
0
1
DIS@
R160
10K_0402_5%
PEG_CLKREQ#_R
1
@
R668
2.2K_0402_5%
for safe
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
@
R644
2.2K_0402_5%
Custom
Date:
DGPU_PRSNT#
DGPU_PRSNT#
DIS,OPTIMUS
UMA
R663
10K_0402_5%
DIS@ 1
R631
0_0402_5%
@C642
@
C642
22P_0402_50V8J
1
2
Reserve for EMI please close to U33
<22> PEG_CLKREQ#
Pull high @ VGA side
C631
10P_0402_50V8J
R02 modify
+3VALW_PCH
DIS@
Q39
2N7002H_SOT23-3
1
GND
HM65@
DIS@
R632
10K_0402_5%
EC_SMB_CK2 <22,40>
Y2 25MHZ 10PF 7V25000014
CLK_PCI_LPBACK
EC_SMB_CK2
XTAL25_IN
C630
10P_0402_50V8J
EC_SMB_DA2 <22,40>
Q38B
DMN66D0LDW-7_SOT363-6
R526
90.9_0402_1%
1
2
EC_SMB_DA2
Q38A
CLK_PCI_LPBACK <17>
PEG_B_CLKRQ# / GPIO56
V40
V42
AK14
AK13
<17,25,44,51,53> VGA_ON
D_CK_SCLK <11,12,41>
Pull up at EC side.
For VGA,EC
+3VS
FLEX CLOCKS
CLK_PEG_VGA#
CLK_PEG_VGA
D_CK_SCLK
AB37
AB38
<22> CLK_PEG_VGA#
<22> CLK_PEG_VGA
D_CK_SDATA <11,12,41>
R670
4.7K_0402_5%
1
2 +3VS
Q40B
PCH_GPIO47
CLK_CPU_DMI#
CLK_CPU_DMI
CLKOUT_PCIE2N
CLKOUT_PCIE2P
V10
MINI2_CLKREQ#
D_CK_SDATA
Q40A
PCH_SMBCLK
USB30_CLKREQ#
LAN_CLKREQ#
<35> LAN_CLKREQ#
R669
4.7K_0402_5%
1
2
+3VS
PCH_SMBDATA 6
T11
PCH_SML1CLK
<35> CLK_PCIE_LAN#
<35> CLK_PCIE_LAN
PCIE LAN
For DDR
+3VS
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
RST_GATE
G12
CL_CLK1
10K_0402_5%
C8
SML0DATA
PEG_A_CLKRQ# / GPIO47
PCH_SMBCLK <37>
RST_GATE
A12
R638
PERN2
PERP2
PETN2
PETP2
BG36
BJ36
AV34
AU34
R02 Modify
BE34
BF34
BB32
AY32
H14
R240
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
SMBCLK
PCH_GPIO11
2 .1U_0402_16V7K
2 .1U_0402_16V7K
PCH_GPIO11
1
1
SMBALERT# / GPIO11
E12
C675
C677
SMBUS
2 .1U_0402_16V7K
2 .1U_0402_16V7K
PERN1
PERP1
PETN1
PETP1
Link
1
1
BG34
BJ34
AV32
AU32
Controller
<37> PCIE_PRX_DTX_N2
<37> PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
<37> PCIE_PTX_C_DRX_P2
Mini Card 1 (WLAN) <37>
C672
C669
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
CLOCKS
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1
PCI-E*
PCIE LAN
<35>
<35>
<35>
<35>
Rev
4019ID
Sheet

1
14
of
60
1 10K_0402_5%
SUSWARN#
R218
1 200K_0402_5%
PCH_ACIN
R247
1 10K_0402_5%
PCH_GPIO72
R610
1 10K_0402_5%
RI#
R597
1 200_0402_1%
PM_DRAM_PWRGD
R559
1 10K_0402_5%
PCH_RSMRST#
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
BC24
BE20
BG18
BG20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
<4>
<4>
<4>
<4>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
<4>
<4>
<4>
<4>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
<4>
<4>
<4>
<4>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
+1.05VS_VTT
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%
1
R223
1
R578
DMI
R607
<4>
<4>
<4>
<4>
FDI
U33C
+3VALW_PCH
4mil width and place

within 500mil of the PCH
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
FDI_INT
AW16
FDI_INT
FDI_FSYNC0
AV12
FDI_FSYNC0
FDI_FSYNC1
BC10
FDI_FSYNC1
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSWVRMEN
A18
FDI_INT <4>
FDI_FSYNC0
+RTCVCC
<4>
FDI_FSYNC1
<4>
FDI_LSYNC0
<4>
FDI_LSYNC1
<4>
DSWODVREN
@ PAD
<5> XDP_DBRESET#
not support AMT APWROK can mux

with PWROK (check list1.0 P.40)
T78
R678
PCH_PWROK
R635
SUSACK#_R
2 XDP_DBRESET#_R
0_0402_5%
C12
K3
P12
SYS_PWROK
L22
PWROK
PCH_RSMRST#
<40> PCH_RSMRST#
SUSWARN#
PBTN_OUT#
<40> PBTN_OUT#
<40,44,47,48> ACIN
D9
SYS_RESET#
PCH_PWROK_R
0_0402_5%
PM_DRAM_PWRGD
<5> PM_DRAM_PWRGD
SUSACK#
SYS_PWROK
L10
PCH_ACIN
2
CH751H-40PT_SOD323-2
B13
C21
System Power Management
APWROK
DRAMPWROK
RSMRST#
PCH_RSMRST#
B9
PCH_PCIE_WAKE#
CLKRUN# / GPIO32
N3
PCH_GPIO32
SUS_STAT# / GPIO61
G8
SUS_STAT#
WAKE#
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
E20
PWRBTN#
ACPRESENT / GPIO31
BATLOW# / GPIO72
RI#
A10
RI#
Ring Indicator CRB1.0 PH 10K +3VALW
tell PCH all power ok

but cpu core
N14
T22
SUSCLK
D10
H4
F4
SLP_A#
G10
SLP_SUS#
G16
SUSCLK <40>
PM_SLP_S5#
PMSYNCH
T21
PAD @
T20
PAD @
SLP_LAN# / GPIO29
PM_SLP_S3# <40>
T47
K14
PCH_GPIO29
PCH_GPIO29
R235
PCH_GPIO32
R622
2 10K_0402_5%
@
2 10K_0402_5%
+3VS
H_PM_SYNC
R613
2 10K_0402_5%
PM_SLP_S4# <40>
PM_SLP_S3#
AP14
PCH_PCIE_WAKE#
PAD @
PM_SLP_S5# <40>
PM_SLP_S4#
PAD
PAD @
Can be left NC
when IAMT is not
support on the
platfrom
not support
Deep S4,S5 can NC
PCH EDS1.2 P.74
PAD
H_PM_SYNC <5>
HM65@
+3VS
5
Y
A
SYS_PWROK
MC74VHC1G08DFT2G_SC70-5
SYS_PWROK <5>
1
ALL power OK
U35
2 B
R629
10K_0402_5%
2
<40,52> VGATE
<40> PCH_PWROK
1 330K_0402_5%
DSWODVREN - On Die DSW VR Enable

HEnable
LDisable
PCH_PCIE_WAKE# <35,37>
T16
E10
1 330K_0402_5%
@
not support Deep S4,S5 DPWROK mux with PWROK

check list1.0 P.42
T23
SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#
PCH_GPIO72
+3VALW_PCH
K16
H20
R581
DSWODVREN
E22
DPWROK
R577
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
15
of
60
Pull high at LVDS conn side.

U33D
R532
1 0_0402_5%
IGPU_BKLT_EN
L_BKLTEN
L_VDD_EN
<31> DPST_PWM
P45
L_BKLTCTL
T40
K47
L_DDC_CLK
L_DDC_DATA
T45
P39
L_CTRL_CLK
L_CTRL_DATA
<31> PCH_LCD_CLK
<31> PCH_LCD_DATA
@
C2043
10P_0402_50V8J
CTRL_CLK
CTRL_DATA
@
C2044
10P_0402_50V8J
2
1
R189
2.37K_0402_1%
LVDS_IBG
AF37
AF36
LVD_IBG
LVD_VBG
LVD_VREF
AE48
AE47
LVD_VREFH
LVD_VREFL
RF request
+3VS
R174
2 2.2K_0402_5%
CTRL_CLK
R158
2 2.2K_0402_5%
CTRL_DATA
R156
2 2.2K_0402_5%
PCH_LCD_CLK
R157
2 2.2K_0402_5%
PCH_LCD_DATA
1
R177
0_0402_5%
<31> PCH_TXCLK<31> PCH_TXCLK+

<31> PCH_TXOUT0<31> PCH_TXOUT1<31> PCH_TXOUT2<31> PCH_TXOUT0+
<31> PCH_TXOUT1+
<31> PCH_TXOUT2+
PCH_TXCLKPCH_TXCLK+
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
+3VS
R521
2 2.2K_0402_5%
PCH_CRT_CLK
R522
2 2.2K_0402_5%
PCH_CRT_DATA
R534
2 150_0402_1%
PCH_CRT_B
R533
2 150_0402_1%
PCH_CRT_G
R535
2 150_0402_1%
PCH_CRT_R
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
PCH_CRT_CLK
PCH_CRT_DATA
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
M47
M49
CRT_HSYNC
CRT_VSYNC
T43
T42
DAC_IREF
CRT_IRTN
<32> PCH_CRT_HSYNC
<32> PCH_CRT_VSYNC
CRT_IREF
R02 Modify
2
1U_0402_6.3V6K
SDVO_INTN
SDVO_INTP
AP39
AP40
SDVO_CTRLDATA strap pull high

at level shift page
P38
M39
SDVO_SCLK
SDVO_SDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
AT49
AT47
AT40
PCH_DPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
SDVO_SCLK <33>
SDVO_SDATA <33>
PCH_DPB_HPD <33>
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
<33>
<33>
<33>
<33>
<33>
<33>
<33>
<33>
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
P46
P42
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
B
M43
M36
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
HM65@
R178
1K_0402_0.5%
PCH_DPB_HPD
AM42
AM40
C2076 1
SDVO_STALLN
SDVO_STALLP
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
<32> PCH_CRT_CLK
<32> PCH_CRT_DATA
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
AP43
AP45
<32> PCH_CRT_B
<32> PCH_CRT_G
<32> PCH_CRT_R
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_CTRLCLK
SDVO_CTRLDATA
Digital Display Interface
ENBKL
<40> ENBKL
J47
M45
LVDS
IGPU_BKLT_EN
<31> PCH_ENVDD
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
16
of
60
1
1
1
1
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
PCH_GPIO55
PCH_GPIO51
PCH_GPIO5
PCH_GPIO52
R166
R169
R170
R172
1
1
1
1
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
PCH_GPIO2
VGA_ON
PCH_GPIO4
PCH_GPIO3
R165
2 8.2K_0402_5%
1 DIS@
2 8.2K_0402_5%
PCH_GPIO53
<39> PCH_USB3_RX1_N
PCH_USB3_RX1_N
<39> PCH_USB3_RX1_P
PCH_USB3_RX1_P
DGPU_HOLD_RST#
PCH_USB3_TX1_N
<39> PCH_USB3_TX1_N
C
PCH_USB3_TX1_P
<39> PCH_USB3_TX1_P
GPIO51 Internal pull high

<14,25,44,51,53> VGA_ON
Boot BIOS Strap bit1 BBS1

Boot BIOS
Bit11 Bit10 Destination
Reserved
PCI
SPI
LPC
PAD
T18
CLK_PCI_LPBACK
CLK_PCI_LPC
R531
R529
1
C633
22P_0402_50V8J @
1
@
2
1
PAD
PAD
PAD
B21
M20
AY16
BG46
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
DGPU_HOLD_RST#
PCH_GPIO52
VGA_ON
C46
C44
E40
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
PCH_GPIO51
PCH_GPIO53
PCH_GPIO55
D47
E42
F46
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
1 22_0402_5%
2 22_0402_5%
T30 @
T10 @
T12 @
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
C6
H49
H43
J48
K42
H40
C632
22P_0402_50V8J
NV_DQS0
NV_DQS1
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
NV_ALE
NV_CLE
AV5
AY1
DF_TVS
DMI Termination Voltage
AV10
NV_RB#
AT8
NV_RE#_WRB0
NV_RE#_WRB1
AY5
BA2
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
Set to Vss when LOW
DG 1.2 CRB1.0 PH 2.2K series 1K
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USBRBIAS#
C33
USBRBIAS
USBRBIAS
B33
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
A14
K20
B17
C16
L16
A16
D14
C14
+1.8VS
R05 Modify
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
<39>
<39>USB Conn. Colay USB3.0
<39>
<39>USB/B (Right side)
<39>
<39>USB/B (Right side)
R633
2.2K_0402_5%
DF_TVS
R626
1
1K_0402_5%
H_SNB_IVB# <5>
CLOSE TO THE BRANCHING POINT
Some PCH config not support USB port 6 & 7.

USB20_N8
USB20_P8
USB20_N8 <37>
USB20_P8 <37>
Mini Card 1 (WLAN)

+3VALW_PCH
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N10
USB20_P10
USB20_N11
USB20_P11
<31>
<31>
<39>
<39>
CMOS Camera (LVDS)

BlueTooth
R05 Modify
USB_OC0#
USB_OC2#
USB_OC7#
USB_OC5#
R596
R588
R595
R590
1
1
1
1
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
USB_OC1#
USB_OC4#
USB_OC3#
SMIB
R773
R612
R592
R616
1
1
1
1 PUSB@
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Within 500 mils

1
R558
2
22.6_0402_1%
R05 Modify
PME#
PLTRST#
Set to Vcc when HIGH
DF_TVS
AT12
BF3
NV_WE#_CK0
NV_WE#_CK1
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PLT_RST#
AY7
AV7
AU3
BG4
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
K40
K38
H38
G38
K10
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_RCOMP
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
<5> PLT_RST#
<14> CLK_PCI_LPBACK
<40> CLK_PCI_LPC
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
R152
R153
R161
R162
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
NVRAM
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
USB
2
2
2
2
RSVD
1
1
1
1
PCI
R173
R180
R181
R183
GNT1#/
GPIO51
U33E
+3VS
R188
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
SMIB
USB_OC7#
USB_OC0# <39>
SMIB
HM65@
For RF request
C2067
C2068
C2075
PLT_RST#
0.1U_0402_16V4Z
PLTRST_VGA#
0.1U_0402_16V4Z
PLTRST_VGA#
0.1U_0402_16V4Z
R02 modify
R297
100K_0402_5%
Compal Secret Data

2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
PLT_RST_BUF# <35,37,40>
1
VCC
OUT
U15
GND
IN2
IN1
Issued Date
PLT_RST#
PLTRST_VGA# <22>
DIS@ R281
100K_0402_5%
DIS@ U14
A
DIS@ R296
100_0402_1%
1
2
4
1
for ESD
IN2
OUT
R02 modify
IN1
VCC
DGPU_HOLD_RST#
GND
PLT_RST#
+3VALW
+3VS
Rev
4019ID
Sheet

1
17
of
60
HDA_SYNC PH(PLL =+1.5VS)
GPIO28
On-Die PLL Voltage Regulator

This signal has a weak internal pull up
HOn-Die voltage regulator enable

LOn-Die PLL Voltage Regulator disable
+3VALW_PCH
+3VS
1
2
R768
4.7K_0402_5%
@
R272
1K_0402_5%
C40
PCH_GPIO68
TACH1 / GPIO1
TACH5 / GPIO69
B41
PCH_GPIO69
PCH_GPIO6
H36
TACH2 / GPIO6
TACH6 / GPIO70
C41
PCH_GPIO70
EC_SCI#
E38
TACH3 / GPIO7
TACH7 / GPIO71
A40
PCH_GPIO71
<40> EC_SMI#
EC_SMI#
C10
GPIO8
LAN_PHY_PWR_CTRL / GPIO12
EC_LID_OUT#
G2
GPIO15
OPTIMUS_EN#
2 10K_0402_5%
GPIO38
OPTIMUS_EN#
OPTIMUS
DIS Only
0
1
<37> WL_OFF#
D40
SATA4GP / GPIO16
TACH0 / GPIO17
PCH_GPIO22
T5
SCLOCK / GPIO22
PCH_GPIO24
E8
GPIO24 / MEM_LED
PCH_GPIO27
E16
GPIO27
PCH_GPIO28
P8
GPIO28
BT_ON#
K1
STP_PCI# / GPIO34
K4
GPIO35
PCH_GPIO36
V8
WWAN_OFF#
M5
2 10K_0402_5%
MSATA_DET#
2 10K_0402_5%
PCH_GPIO22
2 10K_0402_5%
PCH_GPIO39
R619
2 10K_0402_5%
BT_ON#
R292
2 10K_0402_5%
PCH_GPIO48
R274
2 10K_0402_5%
WL_OFF#
2 200K_0402_5% PCH_GPIO36
DIS@
Q2001A
DIS@
5
Q2001B
R291
C2051
1U_0402_6.3V6K
R649
DIS@
R290
DGPU_PWROK
R641
B
+3VSDGPU
PCH_GPIO6
2 10K_0402_5%
DIS@
R191
WL_EN#
2 10K_0402_5%
R2053
10K_0402_5%
DIS@
R546
+3VS
R2054
10K_0402_5%
PCH_GPIO0
R2055
100K_0402_5%
2 10K_0402_5%
R276
2 200K_0402_5% WWAN_OFF#
DIS@
C2050
0.1U_0402_16V4Z
GATEA20 <40>
AU16
PCH_PECI_R
P5
EC_KBRST#
PROCPWRGD
AY11
THRMTRIP#
AY10
INIT3_3V#
T14
NC_1
AH8
NC_2
AK11
NC_3
AH10
NC_4
SATA3GP / GPIO37
AK10
OPTIMUS_EN#
N2
SLOAD / GPIO38
PCH_GPIO39
M3
SDATAOUT0 / GPIO39
NC_5
P37
PCH_GPIO48
V13
SATA2GP / GPIO36
SDATAOUT1 / GPIO48
VSS_NCTF_15
BG2
WL_OFF#
V3
SATA5GP / GPIO49
VSS_NCTF_16
BG48
PCH_GPIO57
D6
GPIO57
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
+3VS
R277
RCIN#
P4
1
2
0_0402_5% @ R239
PECI CPU-EC
H_PECI <5,40>
CTRL+ALT+DEL
EC_KBRST# <40>
H_CPUPWRGD
PCH_THRMTRIP#_R 1
R627
non CPU power ok
<5>
H_THRMTRIP#
2
390_0402_5%
INIT3_3V
A4
VSS_NCTF_1
VSS_NCTF_19
BJ4
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
A46
VSS_NCTF_4
VSS_NCTF_22
BJ46
A5
VSS_NCTF_5
VSS_NCTF_23
BJ5
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
NCTF
+3VS
U2
PECI
H_THRMTRIP# <5>
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
130 degree
shut sown
Checklist1.0 P.59
This signal has weak internal

PU, can't pull low,leave NC
TS_VSS1~4
PD to GND
+3VS
+3VS
R554
10K_0402_5%
2 10K_0402_5%
<37,39> BT_ON#
R548
10K_0402_5%
@
PCH_GPIO69
PCH_GPIO70
R553
10K_0402_5%
2 10K_0402_5%
1 DIS@
R549
10K_0402_5%
@
1
MSATA_DET#
A20GATE
R279
C4
+3VS
R639
EC_KBRST#
R278
10K_0402_5%
PCH_GPIO12
DGPU_PWROK
R623
2 10K_0402_5%
+3VS
PCH_GPIO71 <31>
<37> MSATA_DET#
TACH4 / GPIO68
A42
<40> EC_SCI#
<40> EC_LID_OUT#
PCH_GPIO27
2 10K_0402_5%
BMBUSY# / GPIO0
WL_EN#
T7
<39> WL_EN#
Deep S4,S5 wake event signal

RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70
1
R771
U33F
PCH_GPIO0
R661
PCH_GPIO68
PCH_GPIO28
CPU/MISC
GPIO
Project ID
Q5WE0
Q7YE0
*Q5Wxx-QC
x
GPIO69 GPIO70
0
0
0
0
1
0
1
1
HM65@
+3VALW_PCH
R262
2 10K_0402_5%
PCH_GPIO24
R620
2 10K_0402_5%
PCH_GPIO12
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.
R672
2 1K_0402_5%
EC_LID_OUT#
CRB1.0 PH10K to +3VALW
R263
2 10K_0402_5%
PCH_GPIO57
R911
2 10K_0402_5%
PCH_GPIO36
R912
2 10K_0402_5%
WWAN_OFF#
GPIO36/GPIO37 is Strap functionality

that requires internal pull down to be sampled at rising PWROK.
When uses as SATA2GP/SATA3GP for mechanical presence detect
-use a external pull up 150K-200K ohm to Vcc3_3
When used as GP input
Compal Secret Data
-ensure GPI is not driven high during strap sampling window
Title
2011/06/02
2012/06/02
Issued Date
Deciphered Date
When Unused as GPIO or SATA*GP
SCHEMATIC,MB A7912
-use 8.2K-10K pull-down
check list page 47
Custom
Rev
4019ID
Date:
Sheet

1
18
of
60
+VCCADAC should be powered up during S0

system state.Note that Thermal Sensor
shares the same power supply rail with DAC
+1.05VS_VTT
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
CRT
40mA
VSSADAC
U47
VCCALVDS
AK36
VSSALVDS
AK37
VCCTX_LVDS[1]
AM37
VCCTX_LVDS[2]
AM38
VCCTX_LVDS[3]
AP36
VCCTX_LVDS[4]
AP37
1mA
LVDS
1mA
VCCADAC
+1.05VS_VTT
C
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
C332
1U_0402_6.3V6K
C342
1U_0402_6.3V6K
C325
1U_0402_6.3V6K
C353
1U_0402_6.3V6K
C314
10U_0603_6.3V6M
R02 Modify
T19 @
VCCIO[23]
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
+VCCAFDI_VRM
AP16
+1.05VS_VCCAPLL_FDI
BG6
VCCFDIPLL
AU20
VCCDMI[2]
FDI
Trace 20mil
+1.8VS
L16
0.1UH_MLF1608DR10KT_10%_1608
2
1
1
C305
0.01U_0402_16V7K
1
C310
0.01U_0402_16V7K
C300
22U_0805_6.3V6M
0.1uH inductor, 200mA
PCH Power Rail Table

I/O Buffer Voltage
Voltage Rail
1
VCC3_3[7]
C313
.1U_0402_16V7K
V34
2
VCCVRM[3]
AT16
VCCDMI[1]
AT20
VCCIO[1]
AB36
V_PROC_IO
R02 Modify
Internal PLL and VRM(+1.5VS)
+VCCAFDI_VRM
V5REF_Sus
Processor I/F
0.001
PCH Core Well Reference Voltage

Suspend Well Reference Voltag
0.266
I/O Buffer Voltage
47mA
VccADAC
3.3
0.001
Display DAC Analog Power. This power is

supplied by the core well.
VccADPLLA
1.05
0.08
Display PLL A power
VccADPLLB
1.05
0.08
Display PLL B power
VccCore
1.05
1.3
Internal Logic Voltage
VccDMI
1.05
0.042
DMI Buffer Voltage
VccIO
1.05
2.925
Core Well I/O buffers
VccASW
1.05
1.01
1.05 V Supply for Intel R Management

Engine and Integrated LAN
+3VS
VccSPI
3.3
0.02
3.3 V Supply for SPI Controller Logic
VccDSW
3.3
0.003
3.3v supply for Deep S4/S5 well
VccpNAND
1.8
0.19
1.8V power supply for DF_TVS
VccRTC
3.3
6 uA
Battery Voltage
3.3
0.266
Suspend Well I/O Buffer Voltage
VCCPNAND[1]
AG16
VCCPNAND[2]
AG17
VCCPNAND[3]
AJ16
VCCPNAND[4]
AJ17
10mA
C344
1U_0402_6.3V6K
place near AT20
C308
1U_0402_6.3V6K
place near AB36
Core Well I/O Buffer
+1.8VS
VccDFTERM should PH +1.8VS or +3VS
C349
.1U_0402_16V7K
VCCSPI
DMI buffer logic
R02 Modify
V1
C703
1U_0402_6.3V6K
For SPI control logi
VccSus3_3
HOn-Die PLL voltage regulator enable

+VCCAFDI_VRM
+1.5VS
0.001
0.001
1.05
GPIO28
R257
S0 Iccmax
Current(A)
3.3
2 1U_0402_6.3V6K HM65@
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
V5REF
Voltage
Vcc3_3
C347
B
R02 Modify
+3VS
190mA
VCCVRM[2]
VCCIO[27]
C2064
22U_0805_6.3V6M
+3VS
V33
+1.05VS_VTT
AP17
C322
.1U_0402_16V7K
PAD
VCCIO[22]
AP26
VCC3_3[6]
+1.05VS_VTT
VCCIO[21]
AP24
AT24
+3VS
3711mA
HVCMOS
,VCCAPLLSATA
VCCIO[15]
DMI
AN16
NAND / SPI
+VCCTX_LVDS
1
228mA
VCCIO
+VCCAPLLEXP
T48 @
R149
0_0603_5%
+VCCA_LVDS 1
2
2
PAD
C629
10U_0603_6.3V6M
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
1
U48
C644
.1U_0402_16V7K
C320
1U_0402_6.3V6K
C319
1U_0402_6.3V6K
C346
1U_0402_6.3V6K
C334
10U_0603_6.3V6M
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
C640
0.01U_0402_16V7K
+1.05VS_VTT
POWER
+3VS
L31
4.7UH_LQM18FN4R7M00D_20%
2
1
+VCCADAC
C2063
0.01U_0402_16V7K
1700mA
VCC CORE
U33G
+1.05VS_VTT
0_0603_5%
+VCCAFDI_VRM
VCCVRM==>1.5V FOR MOBILE

VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec
HDA_SYNC PH(PLL =+1.5VS)
VccSusHDA
3.3 / 1.5 0.01
VccVRM
1.8 / 1.5 0.16
VccCLKDMI
High Definition Audio Controller Suspend

Voltage
1.8 V Internal PLL and VRMs (1.8 V for
Desktop)
1.05
0.02
DMI Clock Buffer Voltage
VccSSC
1.05
0.095
Spread Modulators Power Supply
VccDIFFCLKN
1.05
0.055
Differential Clock Buffers Power Supply
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.06
Analog power supply for LVDS (Mobile

Only)
Analog power supply for LVDS (Mobile
Only)
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
19
of
60
+3VS
L14
10UH_LB2012T100MR_20%
1
2
VCC3_3 = 266mA detal waiting for newest spec
DCPSUSBYP
+3VS_VCC_CLKF33
T38
VCC3_3[5]
+VCCAPLL_CPY_PCH
BH23
AL29
PAD
T13 @
+VCCSUS1
AL24
T24
VCCIO[14]
VCCSUS3_3[9]
V23
DCPSUS[3]
VCCSUS3_3[10]
V24
VCCSUS3_3[6]
P24
C348
.1U_0402_16V7K
@
3
Place near
P24
1
Q2006 @
AO3413L_SOT23-3
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
+VCCAFDI_VRM
Y49
T26
V5REF_SUS
M26
+PCH_V5REF_SUS
DCPSUS[4]
AN23
+VCCA_USBSUS
+3VALW_PCH
VCCSUS3_3[1]
AN24
<35,44> PCH_PWR_EN#
1mA
+PCH_V5REF_RUN
VCCSUS3_3[2]
N20
+3V_VCCPSUS
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
VCC3_3[1]
AA16
VCC3_3[8]
W16
VCC3_3[4]
T34
Place
near AF33,
AF34,AG34
VCCVRM[4]
PAD
VCCADPLLB
AF17
AF33
AF34
AG34
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[11]
+VCCSST
1
2 C354
.1U_0402_16V7K
R02 Modify
+1.05VM_VCCSUS
80mA
80mA
R202
100_0402_1%
C352
1U_0402_6.3V6K
VCCIO[5]
VCCIO[12]
AH13
VCCIO[13]
AH14
VCCIO[6]
AF14
D8
+PCH_V5REF_SUS
+3VS
2
C704
.1U_0402_16V7K
Place near
2
AJ2
C343
.1U_0402_16V7K
Place near
2
AA16,W16
Place near
T34
+5VS
+3VS
R148
100_0402_1%
+PCH_V5REF_RUN
C318
0.1U_0603_25V7K
C309
.1U_0402_16V7K
+1.05VS_VTT
AJ2
VCCVRM[1]
D7
C350
1U_0402_6.3V6K
C244
1U_0603_10V6K
AK1
AF11
@ T62 PAD
+VCCAFDI_VRM
,VCCAPLLSATA
+VCCAFDI_VRM
55mA
VCCIO[10]
DCPSST
T17
V19
DCPSUS[1]
DCPSUS[2]
BJ8
V_PROC_IO
130mA
1mA
VCCIO[2]
AC16
VCCIO[3]
AC17
VCCIO[4]
AD17
C351
1U_0402_6.3V6K
2
+1.05VS_VTT
VCCASW[22]
T21
VCCASW[23]
V21
VCCASW[21]
T19
10mAVCCSUSHDA
P32
+3VALW_PCH
R02 Modify
C687
.1U_0402_16V7K
GPIO28
+VCCSATAPLL
+1.05VS_VTT
V16
A22
C685
.1U_0402_16V7K
R02 Modify
VCCAPLLSATA
+RTCVCC
C331
1U_0402_6.3V6K
Place
near BJ8
C693
.1U_0402_16V7K
C694
.1U_0402_16V7K
C700
4.7U_0603_6.3V6K
SATA
BF47
AG33
T15 @
VCCADPLLA
+1.05VS_VTT
+3VALW_PCH
+3VALW_PCH
1
AF13
DCPRTC
VCCRTC
HDA
suppied by internal
1.05V VR Must NC
1 C317
1U_0402_6.3V6K
2
PAD
suppied by internal
1.05V VR Must NC
+5VALW_PCH
P34
VCC3_3[2]
CPU
Place
near AG33
@ T14
R02 Modify
RTC
PCH_PWR_EN#
R03 Modify
V5REF
1mA
MISC
BD47
+1.05VS_VCCA_B_DPL
1 C312
1U_0402_6.3V6K
R02 Modify
VCCIO[34]
903mA
VCCASW[12]
AD31
N16
+1.05VS_VTT
VCCASW[2]
+1.05VS_VTT
Need +3VALW and 0.1U close PCH

1
HM65@
C315
0.1U_0402_16V4Z
Close P32
Compal Secret Data
Issued Date
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
VCCASW[1]
AA21
AD29
+1.05VS_VCCA_A_DPL
R197 2
0_0603_5%
AA19
Place
near AF17
Place near
P24
C333
.1U_0402_16V7K
R02 Modify
C330
.1U_0402_16V7K
+VCCRTCEXT
1 C311
1U_0402_6.3V6K
1
1
T23
VCCSUS3_3[8]
+5VALW_PCH
SGA00001700
220U 2.5V M B2
ESR 35mohm@100Khz
C295
1U_0402_6.3V6K
VCCSUS3_3[7]
+5VALW
+3VALW_PCH
2
1
+1.05VS_VCCA_B_DPL
L11
10UH_LB2012T100MR_20%
T29
+5VALW TO +5VALW_PCH(PCH AUX Power)
C316
1U_0402_6.3V6K
R808
0_0603_5%
C327
1U_0402_6.3V6K
C326
1U_0402_6.3V6K
C278
330U_D2_2V_Y
C296
1U_0402_6.3V6K
1
C
C335
22U_0805_6.3V6M
2
+1.05VS_VCCA_A_DPL
C336
22U_0805_6.3V6M
L12
10UH_LB2012T100MR_20%
1
2
95mA
VCCAPLLDMI2
PCI/GPIO/LPC
+1.05VS_VTT
+1.05VS_VTT
VCCIO[33]
C321
1U_0402_6.3V6K
,VCCAPLLSATA
VCCIO[32]
T27
2
R2090
20K_0402_1%
T11 @
V12
PAD
P28
1mA
+PCH_VCCDSW
+1.05VS_VTT
P26
VCCIO[31]
C2062
0.1U_0402_16V4Z
suppied by internal
1.05V VR must NC
VCCIO[30]
VCCDSW3_3
T17 @
VCCIO[29]
VCCACLK
PAD
T16
N26
C340
.1U_0402_16V7K
2 R02 Modify
VCCDMI = 42mA detal waiting for newest spec
+1.05VS_VTT
USB
Not support Deep S4,S5

connect to +3VALW
GPIO28
AD49
POWER
U33J
Clock and Miscellaneous
Have internal VRM
+3VALW_PCH
C304
1U_0402_6.3V6K
2
D
+3VS_VCC_CLKF33
1
C277
10U_0603_6.3V6M
Rev
4019ID
Sheet

1
20
of
60
U33I
U33H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
HM65@
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
HM65@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
21
of
60
04/06 : Add 6bit VID Function.

for GS4, the boot voltage is 0.975V
for GV4, the boot voltage is 0.85V
U1001A
1 DIS@
2
<14> CLK_PEG_VGA
10K_0402_5%
<14> CLK_PEG_VGA#
PEX_TSTCLK_OUT+
PEX_TSTCLK_OUT2
1
R1015 DIS@ 200_0402_1%
<17> PLTRST_VGA#
PEX_TREMP
2
1
R1016 DIS@ 2.49K_0402_1%
@ 1
2
R1017
10K_0402_5%
@ 1
2
R1018
10K_0402_5%
GL@ 1
2
R1019
10K_0402_5%
GL@ 1
2
R1020
10K_0402_5%
GS@ 1
2
R1021
10K_0402_5%
2 DIS@ 1
R1022
10K_0402_5%
+3VSDGPU
GPIO8
GPIO9
R1000 2 DIS@
R1001 2 DIS@
VID_0
GPU_ACIN
VID_5
1 10K_0402_5%
1 10K_0402_5%
GPU_ACIN <40>
GPU_GPIO16
GPU_GPIO16
R1025
2 0_0402_5%
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
R1026
R1027
R1028
R1030
R1031
R1032
1
1
1
1
1
1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
GPU_VID0
GPU_VID1
GPU_VID2
GPU_VID3
GPU_VID4
GPU_VID5
DACA_RED
DACA_GREEN
DACA_BLUE
AK9
AL10
AL9
DACA_HSYNC
DACA_VSYNC
AM9
AN9
DACA_VDD
DACA_VREF
DACA_RSET
AG10
AP9
AP8
R1003 2 DIS@
1 10K_0402_5%
R02 Modify
EC control ACIN
R4
R5
I2CB_SCL
I2CB_SDA
R7
R6
I2CC_SCL
I2CC_SDA
R2
R3
I2CS_SCL
I2CS_SDA
T4
T3
VGA_DDC_CLK
VGA_DDC_DATA
I2CB_SCL
I2CB_SDA
VGA_LCD_CLK
VGA_LCD_DATA
+3VSDGPU
I2CS_SCL
I2CS_SDA
under GPU
close to ball : AD8
C1000 1
DIS@
PLLVDD
SP_PLLVDD
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
AJ26
AK26
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
AJ12
AP29
PEX_RST_N
PEX_TERMP
VID_PLLVDD
add ADPS function

follow Acer Request
I2CA_SCL
I2CA_SDA
GPIO8
AL13
AK13
AK12
<53>
<53>
<53>
<53>
<53>
<53>
2 DIS@ 1
10K_0402_5%
R1033
2 GSGL@ 1
10K_0402_5%
R1034
GS@ 1
2
10K_0402_5%
R1035
GS@ 1
2
10K_0402_5%
R1036
GL@ 1
2
10K_0402_5%
R1037
@ 1
2
10K_0402_5%
R1038
GPIO
PEX_WAKE_N
VID_1
VID_2
GPIO20,21
N13P/M = NC;
N13P-PES = GPIO20,21
DACs
AJ11
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
+3VSDGPU
2
0.1U_0402_16V4Z
DIS@ Q2005A
AD8 +PLLVDD
AD7
1
XTAL_IN
XTAL_OUT
H3
H2
XTALIN
XTALOUT
XTAL_OUTBUFF
XTAL_SSIN
J4
H1
XTAL_OUTBUFF
XTAL_SSIN
GPIO9
I/O
GPIO0
GPU_VID4
GPIO1
GPU_VID3
GPIO2
LCD_BL_PWM
GPIO3
LCD_VCC
GPIO4
LCD_BLEN
GPIO5
GPU_VID1
GPIO6
GPU_VID2
GPIO7
3D Vision
GPIO8
I/O
OVERT
GPIO9
I/O
ALERT
GPIO10
MEM_VREF_CTL
GPIO11
GPIO12
PWR_LEVEL
GPIO13
THERM_LOAD_STEP_DOWN
GPIO14
HPD_AB
GPIO15
HPD_C
GPIO16
THERM_LOAD_STEP_UP
GPIO17
HPD_D
GPIO18
HPD_E
GPIO19
HPD_F
GPU_THERMAL_ALERT# <40>
Q2005B DIS@
MEM_VDD_CTL(PES)
GPU_VID0(Real N13P)
Reserved
Reserved
GPIO22
I/O
SLI_RASTER_SYNC
GPIO23
SLI_SWAPRDY
3
GPIO24
R02 Modify
U1001
under GPU
close to ball : AE8,AD7
N13P-PES-A1_FCBGA908
GF108@
USAGE
GPIO21
+3VSDGPU
AE8 +GPU_PLLVDD
GPIO
GPIO20
GPU_OVERT <40>
R1014
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
VID_4
VID_3
DIS@ C1002
0.1U_0402_16V4Z
+3VSDGPU
<14> PEG_CLKREQ#
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
Part 1 of 7
DIS@ C1001
0.1U_0402_16V4Z
PEG_GTX_HRX_P0
PEG_GTX_HRX_N0
PEG_GTX_HRX_P1
PEG_GTX_HRX_N1
PEG_GTX_HRX_P2
PEG_GTX_HRX_N2
PEG_GTX_HRX_P3
PEG_GTX_HRX_N3
PEG_GTX_HRX_P4
PEG_GTX_HRX_N4
PEG_GTX_HRX_P5
PEG_GTX_HRX_N5
PEG_GTX_HRX_P6
PEG_GTX_HRX_N6
PEG_GTX_HRX_P7
PEG_GTX_HRX_N7
PEG_GTX_HRX_P8
PEG_GTX_HRX_N8
PEG_GTX_HRX_P9
PEG_GTX_HRX_N9
PEG_GTX_HRX_P10
PEG_GTX_HRX_N10
PEG_GTX_HRX_P11
PEG_GTX_HRX_N11
PEG_GTX_HRX_P12
PEG_GTX_HRX_N12
PEG_GTX_HRX_P13
PEG_GTX_HRX_N13
PEG_GTX_HRX_P14
PEG_GTX_HRX_N14
PEG_GTX_HRX_P15
PEG_GTX_HRX_N15
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
I2C
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
CLK
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15
PCI EXPRESS
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
N13P-GS-A2 FCBGA 908P

GS@
SA000051880
L1003
BLM18PG330SN1_2P
1
2
DIS@
GND
Y1000
DIS@ 4
1
DIS@ C1008
10P_0402_50V8J
+3VSDGPU
27MHZ 10PF 7V27000050

1
GND
I2CS_SCL
DIS@ C1009
10P_0402_50V8J
EC_SMB_DA2 <14,40>
VGA_DDC_CLK R1004 1 DIS@

VGA_DDC_DATA R1005 1 DIS@
2 2.2K_0402_5%
2 2.2K_0402_5%
I2CB_SCL
I2CB_SDA
R1006 1 DIS@
R1007 1 DIS@
2 2.2K_0402_5%
2 2.2K_0402_5%
VGA_LCD_CLK R1008 1 DIS@

VGA_LCD_DATA R1009 1 DIS@
2 2.2K_0402_5%
2 2.2K_0402_5%
I2CS_SCL
I2CS_SDA
2 2.2K_0402_5%
2 2.2K_0402_5%
R1010 1 DIS@
R1011 1 DIS@
N13P-GL-A1 FCBGA 908P

GL@
SA000051A00
U1001
N13M-GS FCBGA 908P GPU

GM@
Q1000BDIS@
R1029
10K_0402_5%
DIS@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
SA000057F20
1
R1023
10K_0402_5%
DIS@
2
XTAL_SSIN
XTAL_OUTBUFF
N13X Design Guide page173

= 180R@100MHz(ESR=0.2)
DIS@ C1007
22U_0805_6.3V6M
DIS@ C1006
22U_0805_6.3V6M
DIS@ C1005
4.7U_0603_6.3V6K
150mA
EC_SMB_CK2 <14,40>
+3VSDGPU
R02 modify
L1001
BLM18PG181SN1D_2P
1
2
DIS@
6
Q1000ADIS@
I2CS_SDA
+GPU_PLLVDD
33ohm (ESR:0.05)
4
U1001
1M_0402_5%
DIS@ C1061
22U_0805_6.3V6M
+PLLVDD
R1024
+1.05VSDGPU
+3VSDGPU
XTALIN
XTALOUT
Rev
4019ID
Sheet

E
22
of
60
VRAM Interface
MDA[15..0]
<27> MDA[15..0]
<27> MDA[31..16]
<28> MDA[47..32]
<28> MDA[63..48]
MDA[31..16]
<29> MDC[15..0]
MDA[47..32]
<29> MDC[31..16]
MDA[63..48]
<30> MDC[47..32]
MDC[15..0]
MDC[31..16]
MDC[47..32]
MDC[63..48]
<30> MDC[63..48]
U1001C
<28> DQMA[7..4]
<27> DQSA[3..0]
<28> DQSA[7..4]
<27> DQSA#[3..0]
<28> DQSA#[7..4]
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
M31
G31
E33
M33
AE31
AK30
AN33
AF33
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
M30
H30
E34
M34
AF30
AK31
AM34
AF32
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
FBA_CMD_RFU0
FBA_CMD_RFU1
R32
AC32
MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
+1.5VSDGPU
FBA_DEBUG0
FBA_DEBUG1
R28 FBA_DEBUG0
AC28 FBA_DEBUG1
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
R30
R31
AB31
AC31
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
FB_CLAMP
2
2
DIS@ 1 60.4_0402_1%
DIS@ 1 60.4_0402_1%
CLKA0 <27>
CLKA0# <27>
CLKA1 <28>
CLKA1# <28>
<29> DQMC[3..0]
<30> DQMC[7..4]
<29> DQSC[3..0]
E1
FB_DLL_AVDD
K27
FBA_PLL_AVDD
U27
FB_VREF
R1039
R1041
Under GPU
close to ball : K27
+FB_PLLAVDD
C1010 DIS@
1
2
0.1U_0402_16V4Z
+FB_PLLAVDD
<30> DQSC[7..4]
100mA
H26
1
2
C1011 0.1U_0402_16V4Z
DIS@
CMDC[30..0]
Part 3 of 7
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
<29> DQSC#[3..0]
<30> DQSC#[7..4]
Under GPU
close to ball : U27
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
E11
E3
A3
C9
F23
F27
C30
A24
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7
D10
D5
C3
B9
E23
E28
B30
A23
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7
D9
E4
B2
A9
D22
D28
A30
B23
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7
GF108@
MEMORY INTERFACE B
P30
F31
F34
M32
AD31
AL29
AM32
AF34
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
FBB_CMD_RFU0
FBB_CMD_RFU1
C12
C20
FBB_DEBUG0
FBB_DEBUG1
G14
G20
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
D12
E12
E20
F20
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
F8
E8
A5
A6
D24
D25
B27
C27
FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
D6
D7
C6
B6
F26
E26
A26
A27
FBB_PLL_AVDD
H17
+1.5VSDGPU
FBB_DEBUG0 R1040 2
FBB_DEBUG1 R1042 2
Issued Date
+FB_PLLAVDD
100mA
1
N13P-PES=1.05V
N13P/M=1.0V
+1.05VSDGPU
CV48 Under GPU

close to ball : H17
Deciphered Date
DIS@
L1000
300mA
2
1
BLM18PG330SN1_2P
33ohm
(ESR:0.05)
1
1
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
+FB_PLLAVDD
+FB_PLLAVDD
Compal Secret Data

2011/06/02
DIS@ 1 60.4_0402_1%
DIS@ 1 60.4_0402_1%
CLKC0 <29>
CLKC0# <29>
CLKC1 <30>
CLKC1# <30>
GF108@
<29,30>
CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30
1U_0402_6.3V6K
DIS@ C1013
<27> DQMA[3..0]
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
DIS@ C1012
0.1U_0402_16V4Z
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
MEMORY INTERFACE
A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
22U_0805_6.3V6M
DIS@ C1014
CMDA[30..0] <27,28>
Part 2 of 7
1U_0402_6.3V6K
DIS@ C1015
U1001B
Rev
4019ID
Sheet
23
of
60
STRAP2
STRAP1
R1045
R1057
MULTI LEVEL STRAPS

+3VSDGPU
Straps
D
+3VSDGPU
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
@ 1
2
R1048
4.99K_0402_1%
GS@ 1
2
R1049
10K_0402_1%
GS@ 1
2
R1050
4.99K_0402_1%
2
1
R1054 GL@
10K_0402_5%
GL@ 1
2
R1055
15K_0402_5%
2
1
R1052 GS@
10K_0402_1%
2
1
R1059 GS@
4.99K_0402_1%
2 X76@ 1
R1053
34.8K_0402_1%
2
1
R1047
@
10K_0402_1%
2
1
R1046
@
34.8K_0402_1%
GL@ 1
2
R1045
10K_0402_1%
GM@ 1
2
R1044
10K_0402_1%
ROM_SO
STRAP3
R1049
10K_0402_1%
GM@
R04 modify
ROM_SCLK
SD034453280
SD034100280
R1059
10K_0402_1%
GM@
SD034100280
SD034100280
STRAP4
R1055
R1052
VDD_SENSE
L4
VCCSENSE_VGA_R
1 DIS@ 2
R1056
0_0402_5%
VCCSENSE_VGA <53>
GND_SENSE
L5
VSSSENSE_VGA_R
1 DIS@ 2
R1060
0_0402_5%
VSSSENSE_VGA <53>
10K_0402_1%
GM@
10K_0402_1%
GM@
SD034100280
SD034100280
TEST
TESTMODE
AK11
R1061 1
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
AM10
AM11
AP12
AP11
AN11
JTAG_TCK R1062 1
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
AB3
AB4
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
DIS@
DIS@
2 10K_0402_5%
2 10K_0402_5%
PAD T2
PAD T3
PAD T4
PAD T5
@
@
@
@
1 DIS@ 2
R1063 10K_0402_5%
SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
H6
H4
H5
H7
ROM_CS#
R1064 1 DIS@
ROM_SCLK
ROM_SI
ROM_SO
For N13P-GS(ES) strap table

GPU
+3VSDGPU
2 10K_0402_5%
Frenq.
N13P-GS
900 MHz
N13P-GS
900 MHz
Memory Size
Memory Config
strap0
strap1
strap2
strap3
strap4
ROM_SI
ROM_SO
128M* 16* 8
2GB
Hynix
SA00003YO20
R
PU 45K
R
PD 35K
R
PD 15K
R
PD 5K
R
PD 10K
R
PD 35K
R
PU 10K
R
PU 5K
64M* 16* 8
1GB
Hynix
SA000041S40
R
PU 45K
R
PD 35K
R
PD 15K
R
PD 5K
R
PD 10K
R
PD 15K
R
PU 10K
R
PU 5K
strap0
strap1
strap2
strap3
strap4
ROM_SI
ROM_SO
R
PD 10K
R
PD 15K
R
PD 15K
ROM_SCLK
For N13P-GL(QS) strap table
GENERAL
BUFRST_N
L2
CEC
L3
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
AK3
AK2
AF3
AF2
ROM_SI
ROM_SO
ROM_SCLK
STRAP3
STRAP4
45.3K_0402_1%
GL@
10K_0402_1%
GM@
R04 modify
MULTI_STRAP_REF0_GND
AG3
AG2
STRAP0
STRAP1
STRAP2
GS@ 1
2
R1058
15K_0402_5%
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
GM@ 1
2
R1051
10K_0402_1%
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
LVDS/TMDS
AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
GS@ 1
2
R1057
34.8K_0402_1%
Part 4 of 7
2 GSGL@ 1
R1043
45.3K_0402_1%
U1001D
J1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
J2
J7
J6
J5
J3
THERMDP
THERMDN
K3
K4
R1065
1 @
R1066 1 DIS@
2 10K_0402_5%
2 10K_0402_5%
MULTI_STRAP_REF0_GND
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
GPU
Frenq.
Memory Size
Memory Config
900 MHz
128M* 16* 8
2GB
Hynix
SA00003YO20
R
PU 45K
R
PD 45K
R
PU 10K
n/a
n/a
R
PD 35K
900 MHz
64M* 16* 8
1GB
Hynix
SA000041S40
R
PU 45K
R
PD 45K
R
PU 10K
n/a
n/a
R
PD 15K
R
PD 10K
ROM_SCLK
B
+3VSDGPU
1 GSGL@ 2
R1067
40.2K_0402_1%
R04 modify
N13P-GS
N13P-GS
For N13M-GS(QS) strap table

GPU
N13M-GS
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
Frenq.
900 MHz
Memory Size
Memory Config
strap0
strap1
strap2
strap3
strap4
ROM_SI
ROM_SO
128M* 16* 8
2GB
Hynix
SA00003YO20
R
PD 10K
R
PU 10K
R
PU 10K
R
PD 10K
R
PD 10K
R
PD 10K
R
PU 10K
ROM_SCLK
R
PD 10K
GF108@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
24
of
60
+3VS to +3VSDGPU for GPU

+3VS
+3VSDGPU
5
4
2
1
DIS@
Q35B
1 DIS@
C612
0.1U_0603_25V7K
DIS@
R511
470_0603_5%
DIS@
DIS@
Q35A
23VSdelay_gate
2
1
DIS@
C603
0.1U_0603_25V7K
6 1
1
2
2
R1072
FB_GND_SENSE
1
DIS@ 10_0402_5%
F2
FB_GND_SENSE
FB_CAL_PD_VDDQ J27
DIS@ 1
2
R1075
40.2_0402_1%
AG26
FB_CAL_TERM_GND
GF108@
DIS@
C1022
22U_0805_6.3V6M
DIS@
C1021
22U_0805_6.3V6M
DIS@ C1020
10U_0603_6.3V6M
DIS@ C1031
22U_0805_6.3V6M
DIS@ C1030
10U_0603_6.3V6M
DIS@ C1036
22U_0805_6.3V6M
DIS@ C1018
4.7U_0603_6.3V6K
DIS@ C1019
10U_0603_6.3V6M
DIS@ C1035
10U_0603_6.3V6M
2
0.1U_0402_16V4Z
DIS@ C1044
4.7U_0603_6.3V6K
370mA
+PEX_PLL_HVDD
+1.05VSDGPU
DIS@ 1
2
C1050 0.1U_0402_16V4Z
+PEX_PLLVDD
Under GPU
150mA
120mA
+VDD33
IFPAB_PLLVDD
IFPAB_RSET
AH8
AJ8
+IFPAB_PLLVDD
R1130 1 DIS@
R1069 1 @
2 10K_0402_5%
2 1K_0402_5%
IFPA_IOVDD
IFPB_IOVDD
AG8
AG9
+IFPAB_IOVDD
R1131 1 DIS@
2 10K_0402_5%
Design guide no define
AF7
AF8
+IFPC_PLLVDD
IFPC_IOVDD
AF6
+IFPC_IOVDD
R1074 1 DIS@
AG7
AN2
+IFPD_PLLVDD
R1076 1 DIS@ 2 10K_0402_5%

R1078 1
@ 2 1K_0402_5%
IFPD_IOVDD
AG6
+IFPD_IOVDD
R1079 1 DIS@
IFPEF_PLVDD
IFPEF_RSET
AB8
AD6
+IFPEF_PLLVDD
R1081 1 DIS@ 2 10K_0402_5%

R1082 1
@ 2 1K_0402_5%
IFPE_IOVDD
IFPF_IOVDD
AC7
AC8
+IFPEF_IOVDD
R1083 1 DIS@
L1004
Near GPU
1
1
L1002
BLM18PG121SN1D_0603
GL@N13P
Reference Sch = 300R@100MHz

Design Guide page69
2 10K_0402_5%
2 DIS@
0_0603_5%
GS@
SD013000080 SD013000080
R1068
0_0603_5%
2 10K_0402_5%
2 10K_0402_5%
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
0_0603_5%
GM@
+3VSDGPU
R1071 1 DIS@ 2 10K_0402_5%

R1073 1
@ 2 1K_0402_5%
Issued Date
L1005
Under GPU (one per pin)
IFPC_PLLVDD
IFPC_RSET
DIS@ C1043
4.7U_0603_6.3V6K
150mA
FB_CAL_TERM_GND H25
2 DIS@ 1
R1080
51.1_0402_1%
+3VSDGPU
J8
K8
L8
M8
IFPD_PLLVDD
IFPD_RSET
FB_CAL_PU_GND
Near GPU
FB_CAL_PD_VDDQ
FB_CAL_PU_GND H27
2 DIS@ 1
R1077
42.2_0402_1%
DIS@ C1029
4.7U_0603_6.3V6K
DIS@ C1034
1U_0402_6.3V6K
+1.05VSDGPU
DIS@ C1053
4.7U_0603_6.3V6K
PEX_PLLVDD
DIS@ C1060
4.7U_0603_6.3V6K
FB_VDDQ_SENSE
AG12
Under GPU
PEX_SVDD_3V3
DIS@ C1059
1U_0402_6.3V6K
F1
DIS@ C1058
1U_0402_6.3V6K
+1.5VSDGPU
FB_VDDQ_SENSE
1
DIS@ 10_0402_5%
DIS@ 1
C1049
VDD33_0
VDD33_1
VDD33_2
VDD33_3
+1.5VSDGPU
2
R1070
PEX_PLL_HVDD
AH12
Near GPU
DIS@ C1057
0.1U_0402_16V4Z
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
DIS@ C1052
1U_0402_6.3V6K
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
2700 mA
total 2700mA
Design guide page.68
+1.05VSDGPU
DIS@ C1056
0.1U_0402_16V4Z
DIS@ C1048
22U_0805_6.3V6M
DIS@ C1047
22U_0805_6.3V6M
DIS@ C1046
10U_0603_6.3V6M
DIS@ C1045
10U_0603_6.3V6M
Near GPU
AG19
AG21
AG22
AG24
AH21
AH25
DIS@ C1042
1U_0402_6.3V6K
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
DIS@ C1051
0.1U_0402_16V4Z
DIS@ C1041
0.1U_0402_16V4Z
DIS@ C1040
0.1U_0402_16V4Z
DIS@ C1033
0.1U_0402_16V4Z
DIS@ C1032
0.1U_0402_16V4Z
DIS@ C1039
1U_0402_6.3V6K
DIS@ C1038
4.7U_0603_6.3V6K
Under GPU
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
DIS@ C1054
0.1U_0402_16V4Z
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
POWER
DIS@ C1037
0.1U_0402_16V4Z
DIS@ C1027
0.1U_0402_16V4Z
DIS@ C1026
0.1U_0402_16V4Z
DIS@ C1025
0.1U_0402_16V4Z
DIS@ C1024
1U_0402_6.3V6K
DIS@ C1023
4.7U_0603_6.3V6K
Under GPU
DIS@ C1017
1U_0402_6.3V6K
1
Part 5 of 7
7200mA
DIS@ C1028
1U_0402_6.3V6K
U1001E
Under GPU
+1.5VSDGPU
DIS@ C1016
1U_0402_6.3V6K
Near GPU
Design guide no define
DIS@ C1055
0.1U_0402_16V4Z
<14,17,44,51,53> VGA_ON
Modify R03
100mil(1.5A)
C590
4.7U_0603_6.3V6K
DIS@
R515
100K_0402_5%
AP2301GN-HF_SOT23-3
3VSdelay_gate
C602
4.7U_0603_6.3V6K
DIS@ R514
1K_0402_5%
1
2
DIS@
1 DIS@ 2
R519
4.7K_0402_5%
+3VALW
D
Q33
DIS@
Rev
4019ID
Sheet

1
25
of
60
U1001F
Part 6 of 7
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
+VGA_CORE
50A
Part 7 of 7
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
U1
U2
U3
U4
U5
U6
U7
U8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
V1
V2
V3
V4
V5
V6
V7
V8
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
W2
W3
W4
W5
W7
W8
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
GF108@
Issued Date
Compal Secret Data
GF108@
+VGA_CORE
U1001G
POWER
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
26
of
60
VRAM DDR3 chips (1GB)
Mode D
Address
0..31
CMD0
64Mx16 DDR3 *8==>1GB

128Mx16 DDR3 *8==>2GB
CMD1
R02 modify
Swap MDA13 and MDA14
DQSA[7..0]
<23,28> DQSA[7..0]
U1002
+MEM_VREF0
M8
H1
VREFCA
VREFDQ
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDA12
CMDA27
CMDA26
M2
N8
M3
BA0
BA1
BA2
CLKA0
CLKA0#
CMDA3
J7
K7
K9
CK
CK
CKE/CKE0
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSA1
DQSA2
DQMA[7..0]
<23,28> DQMA[7..0]
MDA[63..0]
<23,28> MDA[63..0]
CMDA[30..0]
<23,28> CMDA[30..0]
+1.5VSDGPU
DIS@
R1084
240_0402_1%
DIS@
R1085
240_0402_1%
C1069
DIS@
0.1U_0402_16V4Z
+MEM_VREF0
+1.5VSDGPU
DIS@
R1086
240_0402_1%
C1070
DIS@
0.1U_0402_16V4Z
DIS@
R1087
240_0402_1%
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
Group1
MDA17
MDA21
MDA18
MDA23
MDA19
MDA22
MDA16
MDA20
D7
C3
C8
C2
A7
A2
B8
A3
Group2
+1.5VSDGPU
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDA12
CMDA27
CMDA26
M2
N8
M3
BA0
BA1
BA2
CLKA0
CLKA0#
CMDA3
J7
K7
K9
CK
CK
CKE/CKE0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
F3
C7
DQSA0
DQSA3
F3
C7
DQSL
DQSU
DQMA1
DQMA2
E7
D3
DML
DMU
E7
D3
DML
DMU
G3
B7
DQSL
DQSU
DQSA#0
DQSA#3
G3
B7
DQSL
DQSU
CMDA5
T2
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA0
DQMA3
DQSA#1
DQSA#2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CMDA5
T2
RESET
L8
ZQ/ZQ0
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
RESET
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
Group0
MDA27
MDA29
MDA25
MDA30
MDA24
MDA28
MDA26
MDA31
D7
C3
C8
C2
A7
A2
B8
A3
Group3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
ODT_L
CMD3
CKE
CMD4
A14
CMD5
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
CMD16
A14
CAS*
CS0_H#
CMD17
CMD18
ODT_H
CMD19
+1.5VSDGPU
CKE_H
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
Not Available
L8
ZQ1
MDA3
MDA4
MDA2
MDA7
MDA0
MDA5
MDA1
MDA6
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VSDGPU
ODT/ODT0
CS/CS0
RAS
CAS
WE
+1.5VSDGPU
1
2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
K1
L2
J3
K3
L3
DIS@
R1089
243_0402_1%
VREFCA
VREFDQ
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
R1097
@
80.6_0402_1%
+MEM_VREF1 M8
H1
A1
A8
C1
C9
D2
E9
F1
H2
H9
CLKA0 1
2
R1088
@
80.6_0402_1%
DIS@
R1092
160_0402_1%
CLKA0# 1
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
MDA12
MDA13
MDA8
MDA15
MDA9
MDA11
MDA10
MDA14
E3
F7
F2
F8
H3
H8
G2
H7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
ZQ0
X76@
B2
D9
G7
K2
K8
N1
N9
R1
R9
<23> CLKA0#
U1003
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
+MEM_VREF1
<23> CLKA0
X76@
DQSA#[7..0]
<23,28> DQSA#[7..0]
CMD2
@
C1071
0.01U_0402_16V7K
DIS@
R1090
243_0402_1%
2
32..63
CS0_L#
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
NV recommand 0720
CMDA2
CMDA3
CMDA5
CMDA18
CMDA19
R1091 1
R1093 1
R1094 1
R1095 1
R1096 1
DIS@
DIS@
DIS@
DIS@
DIS@
2
2
2
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Command Bit
Default Pull-down
ODTx
10k
10k
CKEx
DDR3
RST
CS*
10k
No Termination
96-BALL
SDRAM DDR3
+1.5VSDGPU
+1.5VSDGPU
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Issued Date
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
Compal Secret Data
R04 modify for EMI
DIS@ C1090
0.1U_0402_16V4Z
DIS@ C1089
0.1U_0402_16V4Z
DIS@ C1088
0.1U_0402_16V4Z
DIS@ C1087
0.1U_0402_16V4Z
DIS@ C1086
0.1U_0402_16V4Z
DIS@ C1085
1U_0402_6.3V6K
DIS@ C1084
1U_0402_6.3V6K
DIS@ C1083
1U_0402_6.3V6K
DIS@ C1082
1U_0402_6.3V6K
DIS@ C1081
0.1U_0402_16V4Z
DIS@ C1080
0.1U_0402_16V4Z
DIS@ C1079
0.1U_0402_16V4Z
DIS@ C1078
0.1U_0402_16V4Z
DIS@ C1077
0.1U_0402_16V4Z
DIS@ C1076
0.1U_0402_16V4Z
DIS@ C1075
1U_0402_6.3V6K
DIS@ C1074
1U_0402_6.3V6K
DIS@ C1073
1U_0402_6.3V6K
C2089
0.01U_0402_16V7K
C2088
0.01U_0402_16V7K
C2087
0.01U_0402_16V7K
C2086
0.01U_0402_16V7K
DIS@ C1072
1U_0402_6.3V6K
+1.5VSDGPU
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
27
of
60
Mode D
Address
64Mx16 DDR3 *8==>1GB

128Mx16 DDR3 *8==>2GB
+MEM_VREF2
CMDA[30..0]
VREFCA
VREFDQ
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQSA#[7..0]
DQSA[7..0]
MDA[63..0]
+1.5VSDGPU
DIS@
R1098
240_0402_1%
CMDA12
CMDA27
CMDA26
M2
N8
M3
BA0
BA1
BA2
CLKA1
CLKA1#
CMDA19
J7
K7
K9
CK
CK
CKE/CKE0
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
DQSA4
DQSA7
CLKA1
CLKA1#
CMDA19
J7
K7
K9
CK
CK
CKE/CKE0
E7
D3
DML
DMU
E7
D3
DML
DMU
G3
B7
DQSL
DQSU
DQSA#5
DQSA#6
G3
B7
DQSL
DQSU
CMDA5
T2
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA5
DQMA6
DQSA#4
DQSA#7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CMDA5
T2
RESET
L8
ZQ/ZQ0
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
RESET
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
MDA45
MDA40
MDA46
MDA41
MDA47
MDA43
MDA44
MDA42
D7
C3
C8
C2
A7
A2
B8
A3
MDA53
MDA49
MDA55
MDA50
MDA52
MDA48
MDA54
MDA51
Group5
Group6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
B2
D9
G7
K2
K8
N1
N9
R1
R9
32..63
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DIS@
R1103
243_0402_1%
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
CMD2
ODT_L
CMD3
CKE
CMD4
A14
CMD5
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
CAS*
A14
CMD16
CS0_H#
CMD17
+1.5VSDGPU
CMD18
ODT_H
CMD19
CKE_H
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
Not Available
L8
ZQ3
96-BALL
SDRAM DDR3
@
C1093
0.01U_0402_16V7K
DIS@ C1112
0.1U_0402_16V4Z
DIS@ C1111
0.1U_0402_16V4Z
DIS@ C1110
0.1U_0402_16V4Z
DIS@ C1109
0.1U_0402_16V4Z
DIS@ C1108
0.1U_0402_16V4Z
DIS@ C1107
1U_0402_6.3V6K
+1.5VSDGPU
DIS@ C1106
1U_0402_6.3V6K
+1.5VSDGPU
DIS@ C1105
1U_0402_6.3V6K
2
NV recommand 0720
BA0
BA1
BA2
DQMA4
DQMA7
DIS@ C1096
1U_0402_6.3V6K
M2
N8
M3
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VSDGPU
DQSL
DQSU
CLKA1# 1
2
R1106
@
80.6_0402_1%
<23> CLKA1#
CMDA12
CMDA27
CMDA26
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
F3
C7
DIS@ C1095
1U_0402_6.3V6K
R1104
@
DIS@
80.6_0402_1%
R1105
160_0402_1%
DIS@ C1094
1U_0402_6.3V6K
<23> CLKA1
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQSA5
DQSA6
ZQ2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
F3
C7
DIS@
R1102
243_0402_1%
CLKA1 1
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
DIS@ C1104
1U_0402_6.3V6K
+1.5VSDGPU
VREFCA
VREFDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODT/ODT0
CS/CS0
RAS
CAS
WE
DIS@
C1098
0.1U_0402_16V4Z
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DIS@
R1101
240_0402_1%
C1092
DIS@
0.1U_0402_16V4Z
+MEM_VREF3
Group7
M8
H1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
+1.5VSDGPU
DIS@
R1100
240_0402_1%
Group4
X76@
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
DIS@ C1097
1U_0402_6.3V6K
C1091
DIS@
0.1U_0402_16V4Z
D7
C3
C8
C2
A7
A2
B8
A3
MDA61
MDA59
MDA60
MDA57
MDA63
MDA56
MDA62
MDA58
+MEM_VREF3
+1.5VSDGPU
+MEM_VREF2
DIS@
R1099
240_0402_1%
MDA39
MDA35
MDA37
MDA33
MDA38
MDA32
MDA36
MDA34
DIS@
C1103
0.1U_0402_16V4Z
<23,27> MDA[63..0]
E3
F7
F2
F8
H3
H8
G2
H7
DIS@
C1102
0.1U_0402_16V4Z
<23,27> DQSA[7..0]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DIS@
C1101
0.1U_0402_16V4Z
<23,27> DQSA#[7..0]
U1005
DIS@
C1100
0.1U_0402_16V4Z
<23,27> CMDA[30..0]
X76@
M8
H1
DQMA[7..0]
<23,27> DQMA[7..0]
0..31
CS0_L#
CMD1
U1004
DIS@
C1099
0.1U_0402_16V4Z
CMD0
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
28
of
60
Mode D
Address
0..31
CMD0
32..63
CS0_L#
CMD1
64Mx16 DDR3 *8==>1GB

128Mx16 DDR3 *8==>2GB
CMD2
DQSC[7..0]
DQSC#[7..0]
DQMC[7..0]
+MEM_VREF4
M8
H1
VREFCA
VREFDQ
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDC12
CMDC27
CMDC26
M2
N8
M3
BA0
BA1
BA2
MDC[63..0]
CMDC[30..0]
+1.5VSDGPU
GSGL@
R1107
240_0402_1%
+1.5VSDGPU
GSGL@
R1109
240_0402_1%
J7
K7
K9
CMDC2
CMDC0
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSC1
DQSC2
F3
C7
DQSL
DQSU
DQMC1
DQMC2
E7
D3
DML
DMU
DQSC#1
DQSC#2
G3
B7
DQSL
DQSU
CMDC5
T2
RESET
ZQ4
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
Group2
M2
N8
M3
BA0
BA1
BA2
MDC3
MDC7
MDC1
MDC4
MDC2
MDC6
MDC0
MDC5
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC26
MDC31
MDC25
MDC30
MDC27
MDC28
MDC24
MDC29
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Group3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
CMDC2
CMDC0
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
DQSC0
DQSC3
F3
C7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMC0
DQMC3
E7
D3
DML
DMU
DQSC#0
DQSC#3
G3
B7
DQSL
DQSU
CMDC5
T2
RESET
L8
ZQ/ZQ0
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CK
CK
CKE/CKE0
A14
CMD5
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
A14
CAS*
CS0_H#
CMD17
CMD18
ODT_H
CMD19
+1.5VSDGPU
CKE_H
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
Not Available
ODT/ODT0
CS/CS0
RAS
CAS
WE
CKE
CMD4
CMD16
+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
ZQ5
Group0
ODT_L
CMD3
GSGL@
R1112
243_0402_1%
CMDC2
CMDC3
CMDC5
CMDC18
CMDC19
R1113 1
R1114 1
R1115 1
R1116 1
R1117 1
GSGL@
GSGL@
GSGL@
GSGL@
GSGL@
2
2
2
2
2
Command Bit
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Default Pull-down
10k
ODTx
DDR3
10k
CKEx
RST
CS*
10k
No Termination
96-BALL
SDRAM DDR3
GSGL@ C1134
0.1U_0402_16V4Z
GSGL@ C1125
0.1U_0402_16V4Z
GSGL@ C1124
0.1U_0402_16V4Z
GSGL@ C1123
0.1U_0402_16V4Z
GSGL@ C1122
0.1U_0402_16V4Z
GSGL@ C1121
0.1U_0402_16V4Z
GSGL@ C1119
1U_0402_6.3V6K
GSGL@ C1118
1U_0402_6.3V6K
GSGL@ C1117
1U_0402_6.3V6K
+1.5VSDGPU
@
C1115
0.01U_0402_16V7K
GSGL@ C1120
0.1U_0402_16V4Z
+1.5VSDGPU
1
2
NV recommand 0720
CMDC12
CMDC27
CMDC26
E3
F7
F2
F8
H3
H8
G2
H7
J7
K7
K9
+1.5VSDGPU
CLKC0# 1
2
@R1120
@
R1120
80.6_0402_1%
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
96-BALL
SDRAM DDR3
GSGL@ C1116
1U_0402_6.3V6K
1
2
CLKC0 1
2
@R1118
@
R1118
80.6_0402_1%
GSGL@
R1119
160_0402_1%
<23> CLKC0#
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
GSGL@
R1111
243_0402_1%
<23> CLKC0
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
CLKC0
CLKC0#
CMDC3
CK
CK
CKE/CKE0
MDC18
MDC20
MDC17
MDC22
MDC16
MDC23
MDC19
MDC21
Group1
VREFCA
VREFDQ
GSGL@ C1133
0.1U_0402_16V4Z
C1114 GSGL@
0.1U_0402_16V4Z
GSGL@
R1110
240_0402_1%
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
+MEM_VREF5 M8
H1
+1.5VSDGPU
CLKC0
CLKC0#
CMDC3
+MEM_VREF5
MDC8
MDC12
MDC11
MDC13
MDC9
MDC14
MDC10
MDC15
GSGL@ C1132
0.1U_0402_16V4Z
E3
F7
F2
F8
H3
H8
G2
H7
GSGL@ C1131
0.1U_0402_16V4Z
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
X76@
GSGL@ C1130
0.1U_0402_16V4Z
GSGL@
R1108
240_0402_1%
C1113 GSGL@
0.1U_0402_16V4Z
+MEM_VREF4
1
U1007
GSGL@ C1129
1U_0402_6.3V6K
<23,30> MDC[63..0]
<23,30> CMDC[30..0]
X76@
GSGL@ C1128
1U_0402_6.3V6K
<23,30> DQMC[7..0]
U1006
GSGL@ C1127
1U_0402_6.3V6K
<23,30> DQSC[7..0]
<23,30> DQSC#[7..0]
GSGL@ C1126
1U_0402_6.3V6K
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
29
of
60

64Mx16 DDR3 *8==>1GB
128Mx16 DDR3 *8==>2GB
R02 modify
Swap MDC37 and MDC38
DQMC[7..0]
<23,29> DQMC[7..0]
DQSC#[7..0]
<23,29> DQSC#[7..0]
U1008
DQSC[7..0]
<23,29> DQSC[7..0]
+MEM_VREF6
+1.5VSDGPU
GSGL@
R1121
240_0402_1%
VREFCA
VREFDQ
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDC12
CMDC27
CMDC26
M2
N8
M3
BA0
BA1
BA2
C1135 GSGL@
0.1U_0402_16V4Z
+MEM_VREF6
GSGL@
R1122
240_0402_1%
+1.5VSDGPU
GSGL@
R1123
240_0402_1%
X76@
M8
H1
MDC[63..0]
<23,29> MDC[63..0]
Mode D
Address
CMDC[30..0]
<23,29> CMDC[30..0]
U1009
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDC39
MDC33
MDC37
MDC32
MDC36
MDC34
MDC38
MDC35
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC44
MDC43
MDC47
MDC40
MDC45
MDC42
MDC46
MDC41
+MEM_VREF7
Group4
Group5
+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
CLKC1
CLKC1#
CMDC19
J7
K7
K9
CK
CK
CKE/CKE0
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSC4
DQSC5
F3
C7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DQMC4
DQMC5
E7
D3
DML
DMU
DQSC#4
DQSC#5
G3
B7
DQSL
DQSU
CMDC5
T2
RESET
X76@
M8
H1
VREFCA
VREFDQ
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDC12
CMDC27
CMDC26
M2
N8
M3
BA0
BA1
BA2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDC63
MDC58
MDC62
MDC59
MDC60
MDC61
MDC57
MDC56
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC54
MDC48
MDC52
MDC50
MDC53
MDC51
MDC55
MDC49
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
J7
K7
K9
CK
CK
CKE/CKE0
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSC7
DQSC6
F3
C7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
Group6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMC7
DQMC6
E7
D3
DML
DMU
DQSC#7
DQSC#6
G3
B7
DQSL
DQSU
CMDC5
T2
RESET
L8
ZQ/ZQ0
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
+1.5VSDGPU
C1136 GSGL@
0.1U_0402_16V4Z
ZQ6
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
ZQ7
1
2
ODT_L
CMD3
CKE
CMD4
A14
CMD5
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
A14
CMD14
A15
A15
CMD15
CAS*
CAS*
CS0_H#
CMD18
ODT_H
CMD19
CKE_H
CMD20
A13
A13
CMD21
A8
A8
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
B1
B9
D1
D8
E2
E8
F9
G1
G9
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
Not Available
96-BALL
SDRAM DDR3
+1.5VSDGPU
GSGL@ C1156
0.1U_0402_16V4Z
GSGL@ C1155
0.1U_0402_16V4Z
GSGL@ C1154
0.1U_0402_16V4Z
GSGL@ C1153
0.1U_0402_16V4Z
GSGL@ C1152
0.1U_0402_16V4Z
GSGL@ C1151
1U_0402_6.3V6K
GSGL@ C1150
1U_0402_6.3V6K
GSGL@ C1149
1U_0402_6.3V6K
GSGL@ C1148
1U_0402_6.3V6K
GSGL@ C1147
0.1U_0402_16V4Z
GSGL@ C1146
0.1U_0402_16V4Z
GSGL@ C1145
0.1U_0402_16V4Z
GSGL@ C1144
0.1U_0402_16V4Z
+1.5VSDGPU
GSGL@ C1142
0.1U_0402_16V4Z
96-BALL
SDRAM DDR3
@
C1137
0.01U_0402_16V7K
GSGL@ C1141
1U_0402_6.3V6K
NV recommand 0720
GSGL@ C1140
1U_0402_6.3V6K
CLKC1# 1
2
@R1129
@
R1129
80.6_0402_1%
GSGL@ C1139
1U_0402_6.3V6K
<23> CLKC1#
GSGL@ C1138
1U_0402_6.3V6K
GSGL@
R1128
160_0402_1%
GSGL@ C1143
0.1U_0402_16V4Z
2
@ R1127
80.6_0402_1%
GSGL@
R1125
243_0402_1%
CLKC1 1
<23> CLKC1
GSGL@
R1126
243_0402_1%
CMD2
CMD17
L8
32..63
CMD16
+MEM_VREF7
GSGL@
R1124
240_0402_1%
0..31
CS0_L#
CMD1
Group7
+1.5VSDGPU
CLKC1
CLKC1#
CMDC19
+1.5VSDGPU
CMD0
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
30
of
60
LCD POWER CIRCUIT
+LCDVDD
+3VS
+3VALW
R02 Modify
1
W=60mils
R6
10K_0402_5%
R5
200_0603_1%
C479
4.7U_0603_6.3V6K
B+
Place closed to JLVDS1
+LCDVDD
+3VS
2
G
LCDVDD_ON
C2
1U_0402_6.3V6K
C484
Q28
+LCDVDD
0.1U_0402_16V4Z
C485
10U_0603_6.3V6M
0.1U_0402_16V4Z
@
C2040
47P_0402_50V8J
C6
SM010014520 3000ma
68P_0402_50V8J
220ohm@100mhz
2
DCR 0.04
W=60mils
C9
680P_0402_50V7K
RF request
C562
4.7U_0603_6.3V6K
C11
Q1
SSM3K7002F_SC59-3
2
G
3
<16> PCH_ENVDD
1
AP2301GN-HF_SOT23-3
Q2
SSM3K7002F_SC59-3
R2
10K_0402_5%
2
1
+INVPWR_B+
L2
FBMA-L11-201209-221LMA30T_0805
1
2
L1
W=60mils
FBMA-L11-201209-221LMA30T_0805
1
2
C10
0.1U_0402_16V4Z
R4
C
LCD/LED PANEL Conn.
100K_0402_5%
W=60mils
+INVPWR_B+
JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
W=60mils
+LCDVDD
+3VS
+3VS
U13
1 R783
2
100K_0402_5%
@
<16> DPST_PWM
OE#
VCC
IN
GND
OUT
INVTPWM
<40> BKOFF#
220P_0402_50V7K 1
C5
BKOFF#
220P_0402_50V7K 1
C8
<16> PCH_LCD_CLK
<16> PCH_LCD_DATA
2 10K_0402_5%
PCH_TXOUT0PCH_TXOUT0+
<16> PCH_TXOUT0<16> PCH_TXOUT0+

1
2
0_0402_5%
INVTPWM
R18
74AHC1G125GW_SOT353-5
@
1
R85
INVTPWM
BKOFF#
PCH_LCD_CLK
PCH_LCD_DATA
PCH_TXCLKPCH_TXCLK+
<16> PCH_TXCLK<16> PCH_TXCLK+
R86
10K_0402_5%
TZOUT0TZOUT0+
TZOUT1TZOUT1+
TZCLKTZCLK+
EDP_HPD
+3VS
eDP
For Camera
USB20_N10
USB20_P10
<17> USB20_N10
<17> USB20_P10
+3VS
<4> EDP_HPD#
Q29
SSM3K7002F_SC59-3
EDP@
D
Q22
SSM3K7002F_SC59-3
EDP@
2
G
S
EDP_HPD
EDP@
R480
100K_0402_5%
R02 modify
<4> EDP_TXP0
<4> EDP_TXN0
.1U_0402_16V7K 1
.1U_0402_16V7K 1
2EDP@ C910
2EDP@ C911
TZOUT0+
TZOUT0-
<4> EDP_TXP1
<4> EDP_TXN1
.1U_0402_16V7K 1
.1U_0402_16V7K 1
2EDP@ C912
2EDP@ C913
TZOUT1+
TZOUT1-
.1U_0402_16V7K 1
.1U_0402_16V7K 1
2EDP@ C914
2EDP@ C915
TZCLK+
TZCLK-
<4> EDP_AUXP
<4> EDP_AUXN
C480
22P_0402_50V8J
@
C481
22P_0402_50V8J
2 @
G1
G2
G3
G4
G5
G6
41
42
43
44
45
46
I-PEX_20143-040E-20F
D15 @
EDP_HPD 2
G
PCH_GPIO71 <18>
PCH_GPIO71
D
R550
10K_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O1
I/O3
USB20_N10
GND
VDD
+3VS
I/O4
GPIO71
USB20_P10
PCH_GPIO71
eDP
LVDS
I/O2
Modify R02
AZC099-04S.R7G_SOT23-6
0
1
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
31
of
60
+5VS
R04 modify
W=40mils
+R_CRT_VCC
D5
PCH_CRT_G
PCH_CRT_B
CRT_B_2
C597
10P_0402_50V8J
SM010012010 300ma 120ohm@100mhz DCR 0.4

+CRT_VCC
R147 2
R428 2
1
33_0402_5%
CRT_HSYNC
1 10K_0402_5%
U10
Y
1
L13
2
MBC1608121YZF_0603
CRT_HSYNC_2
1
L10
2
MBC1608121YZF_0603
CRT_VSYNC_2
1
1
C230
10P_0402_50V8J
CRT_HSYNC_1
C589
100P_0402_50V8J
JCRT1
6
JCRT1.11 11
@ T71
1
7
12
2
8
13
3
9
14
G 16
4
G 17
10
15
JCRT1.5 5
@ T72
PAD
C-H_13-12201513CP
CONN@
DSUB_12
C220
10P_0402_50V8J
DSUB_15
C623 2
68P_0402_50V8J 1
PCH_CRT_HSYNC
<16> PCH_CRT_HSYNC
2 0.1U_0402_16V4Z
OE#
C243 1
CRT Connector
PAD
CRT_G_2
C614
10P_0402_50V8J
C215
0.1U_0402_16V4Z
CRT_R_2
C637
10P_0402_50V8J
C588
22P_0402_50V8J
CRT_B_1
C601
22P_0402_50V8J
CRT_G_1
CH491DPT_SOT23-3
L33
BLM18BA470SN1D_2P
1
2
L30
BLM18BA470SN1D_2P
1
2
L28
BLM18BA470SN1D_2P
1
2
CRT_R_1
C621
22P_0402_50V8J
2
2
C596
10P_0402_50V8J
R510
150_0402_1%
C613
10P_0402_50V8J
R524
R520
150_0402_1% 150_0402_1%
C636
10P_0402_50V8J
<16> PCH_CRT_B
<16> PCH_CRT_G
PCH_CRT_R
<16> PCH_CRT_R
CRB1.0 use 47ohm@100Mhz Bead
L32
BLM18BA470SN1D_2P
1
2
L29
BLM18BA470SN1D_2P
1
2
L27
BLM18BA470SN1D_2P
1
2
@
D18
L30ESDL5V0C3-2
1
@
D17
L30ESDL5V0C3-2
+CRT_VCC
F1
1.1A_6V_SMD1812P110TFW=40mils
1
2
74AHCT1G125GW_SOT353-5
C586
68P_0402_50V8J
+CRT_VCC
P
R426 2
1
33_0402_5%
CRT_VSYNC
U9
Y
CRT_VSYNC_1
PCH_CRT_VSYNC
<16> PCH_CRT_VSYNC
2 0.1U_0402_16V4Z
OE#
C228 1
74AHCT1G125GW_SOT353-5
+CRT_VCC
+3VS
PCH_CRT_DATA
1
5
<16> PCH_CRT_DATA
PCH_CRT_CLK
<16> PCH_CRT_CLK
R142
4.7K_0402_5%
2
R146
4.7K_0402_5%
DSUB_12
6
Q11A
DSUB_15
Q11B
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

E
32
of
60
SM070001310 400ma 90ohm@100mhz DCR 0.3

HDMI_CLK-
R574 1
1
L38
WCM-2012-900T_0805
@
4
D
@ R242
0_0603_5%
1
2
HDMI_TX0-
R565 1
1 +HDMI_5V
L36
WCM-2012-900T_0805
@
4
+HDMI_5V_OUT
F2
2
3
2
W=40mils
D10
+5VS
R579 1
0_0402_5%
HDMI_R_CK+
0_0402_5%
HDMI_R_D0-
R569 1
HDMI_TX1-
R584 1
HDMI_TX0+
HDMI_R_CK-
HDMI_CLK+
0_0402_5%
0_0402_5%
HDMI_R_D0+
0_0402_5%
HDMI_R_D1-
1
1.1A_6V_SMD1812P110TF
CH491DPT_SOT23-3
C345
0.1U_0402_16V4Z
1
L39
WCM-2012-900T_0805
@
4
HDMI_TX1+
R586
0_0402_5%
HDMI_R_D1+
HDMI_TX2-
R591
0_0402_5%
HDMI_R_D2-
+3VS
1
L40
WCM-2012-900T_0805
@
4
<16> PCH_DPB_N2
<16> PCH_DPB_P2
C287
C286
2
2
1 .1U_0402_16V7K
1 .1U_0402_16V7K
HDMI_TX0HDMI_TX0+
<16> PCH_DPB_N3
<16> PCH_DPB_P3
C285
C284
2
2
1 .1U_0402_16V7K
1 .1U_0402_16V7K
HDMI_CLKHDMI_CLK+
HDMI_HPD
1
HDMI_TX2+
Q14
SSM3K7002F_SC59-3
1
4
R593 1
3
2
0_0402_5%
HDMI_R_D2+
C
PCH_DPB_HPD <16>
R219
100K_0402_5%
HDMI_TX2- R589 1
HDMI_TX2+ R594 1
2 680_0402_5%
2 680_0402_5%
HDMI_TX1- R583 1
HDMI_TX1+ R587 1
2 680_0402_5%
2 680_0402_5%
HDMI_TX0- R564 1
HDMI_TX0+ R570 1
2 680_0402_5%
2 680_0402_5%
HDMI_CLK- R573 1
HDMI_CLK+ R580 1
2 680_0402_5%
2 680_0402_5%
HDMI_GND
HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+
1 .1U_0402_16V7K
1 .1U_0402_16V7K
1 .1U_0402_16V7K
1 .1U_0402_16V7K
2
2
2
2
C283
C282
C280
C281
<16> PCH_DPB_N1
<16> PCH_DPB_P1
<16> PCH_DPB_N0
<16> PCH_DPB_P0
C324
220P_0402_50V7K
2
G
R198
1M_0402_5%
Q37
2
G
SSM3K7002F_SC59-3 S
+3VS
+3VS
SDVO_SCLK
R253
2 2.2K_0402_5%
SDVO_SDATA
+HDMI_5V_OUT
+3VS
2
Q16
SSM3K7002F_SC59-3
JHDMI1
HDMI_HPD
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
HDMI_SCLK
RF request
HDMI_SDATA
C357
47P_0402_50V8J
@
1
D
SDVO_SDATA
HDMI_R_CK+
HDMI_R_D0-
<16> SDVO_SDATA
Q17
SSM3K7002F_SC59-3
C358
47P_0402_50V8J
2 @
Place closed to JHDMI1
HDMI_R_CK-
SDVO_SCLK
<16> SDVO_SCLK
HDMI connector
D11
RB751V40_SC76-2
1
2 1
R256
2.2K_0402_5%
D12
RB751V40_SC76-2
R785
0_0402_5%
2 2.2K_0402_5%
1
2 1
R255
2.2K_0402_5%
R250
HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
ACON_HMR2E-AK120D
CONN@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
33
of
60
SATA HDD1 Conn.

CL 4.0 mm
JHDD1
<13> SATA_PTX_DRX_P0
<13> SATA_PTX_DRX_N0
<13> SATA_PRX_DTX_N0
<13> SATA_PRX_DTX_P0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
C708 1
C711 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C712 1
C713 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+3VS
+5VS
R2051
10_0805_5%2
+5VS_HDD1
+3VS
1
C453
0.1U_0402_16V4Z
+5VS_HDD1
C
100mils
1
OCTEK_SAT-22DD1G
CONN@
C742
1000P_0402_50V7K
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
GND
GND
C743
0.1U_0402_16V4Z
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C740
1U_0402_6.3V6K
GND
RX+
RXGND
TXTX+
GND
C744
10U_0603_6.3V6M
1
2
3
4
5
6
7
R02 Modify
SATA ODD Conn.

JODD1
SATA_PTX_DRX_P2 C643 1
SATA_PTX_DRX_N2 C639 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
SATA_PRX_DTX_N2 C628 1
SATA_PRX_DTX_P2 C624 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
PAD
+5VS_ODD
DP
+5V
+5V
MD
GND
GND
80mils
T79
1
GND
GND
GND
GND
17
16
15
14
OCTEK_SLS-13SB1G_RV
CONN@
C199
10U_0603_6.3V6M
R2052
10_0805_5%2
C192
1000P_0402_50V7K
8
9
10
11
12
13
+5VS_ODD
+5VS
C200
0.1U_0402_16V4Z
GND
A+
AGND
BB+
GND
C201
1U_0402_6.3V6K
1
2
3
4
5
6
7
R02 Modify
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
34
of
60
+1.2V_LAN
R03 modify
R02 modify
for ESD
C2069 1
39
45
51
AVDDL
AVDDL
AVDDL
+LAN_GPHYPLLVDDL
36
GPHY_PLLVDDL
+LAN_PCIEPLLVDD
32
PCIE_PLLVDDL
29
PCIE_PLLVDDL
2 0.1U_0402_16V4Z PLT_RST_BUF#
+LAN_AVDDH
TRD3_N
TRD3_P
49
50
LAN_MIDI3LAN_MIDI3+
TRD2_N
TRD2_P
47
46
LAN_MIDI2LAN_MIDI2+
TRD1_N
TRD1_P
43
44
LAN_MIDI1LAN_MIDI1+
TRD0_N
TRD0_P
41
40
LAN_MIDI0LAN_MIDI0+
Q2007 @
AO3413L_SOT23-3
LAN_MIDI3- <36>
LAN_MIDI3+ <36>
SO_LINKLED#
20mil
LAN_MIDI1- <36>
LAN_MIDI1+ <36>
+LAN_XTALVDDH
C323
LAN_MIDI0- <36>
LAN_MIDI0+ <36>
65
20mil
R201 1
<37,40> EC_PME#
+3V_LAN
2 C670
2 C673
<15,37> PCH_PCIE_WAKE#
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
TRAFFICLED#_SERIALDI
67
2 0_0402_5%
R209 1
2 4.7K_0402_5%
R213 1
2 0_0402_5%
R225 1
<17,37,40> PLT_RST_BUF#
<14> CLK_PCIE_LAN
<14> CLK_PCIE_LAN#
PCIE_PRX_C_DTX_P1 28
PCIE_PRX_C_DTX_N1 27
33
34
LAN_PME#
<36>
<36>
<36>
<36>
<36>
<36>
<36>
<36>
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
1
1
1
1
1
1
1
1
CR_DATA0_R
CR_DATA1_R
CR_DATA2_R
CR_DATA3_R
CR_DATA4_R
CR_DATA5_R
CR_DATA6_R
CR_DATA7_R
R200 2
1 0_0402_5%
+VDDO_CR_R
R214 1
2 0_0603_5%
GPIO_0
CR_5IN1_LED#_R
R229 2
64
63
SPROM_DOUT
SPROM_CLK
PREST#
PCIE_REFCLK_P
PCIE_REFCLK_N
25
24
23
22
52
53
54
55
LAN_ACTIVITY# <36>
+VDDO_CR
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
2 1K_0402_5% 58
VMAIN_PRSNT
0.1U_0402_16V4Z
0_0402_5%
CR_5IN1_LED#
R228 1
2 4.7K_0402_5% 6
TEST1
10
TEST2
<36> CR_PWR_XD_ALE
LAN_XTALI
LAN_XTALO_R
CR_XD_WE#_SD_DETECT_R
R576
1 0_0402_5%
CR_XD_WE#_SD_DETECT
CR_XD_DETECT#_R
R572
1 0_0402_5%
CR_XD_DETECT#
3
GND
2
C681
15P_0402_50V8J
2
3LAN_XTALO
GND
MS_INS#/XD_CE#
59
CR_XD_CE#_MS_INS#_R
R192
2 33_0402_5% CR_XD_CE#_MS_INS#
CR_XD_CE#_MS_INS# <36>
CR_XD_RE#_R
R227
1 0_0402_5%
CR_XD_RE#
CR_XD_RE# <36>
CR_WP#/XD_WP#
57
CR_WP#_XD_WP#_R
R185
1 0_0402_5%
CR_WP#_XD_WP#
CR_LED_CR_BUS_PWR/XD_ALE
60
CR_PWR_EN_R
R196
1 0_0402_5%
CR_PWR_EN
CR_CLK/XD_RY_BY#
21
CR_CLK_XD_RY_BY#_R
R216
2 0_0402_5%
CR_CLK_XD_RY_BY#
CR_CMD_XD_CLE
26
CR_CMD_XD_CLE_R R195
LOW_PWR
19
18
<14> LAN_CLKREQ#
2 22_0402_5%
4
2
C679
15P_0402_50V8J
+3V_LAN
16
SR_VFB
13
40mil
L37
+1.2V_LAN_OUT 1
2
4.7UH_PG031B-4R7MS_1.1A_20%
C689
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CR_CMD_XD_CLE
CR_XD_DETECT# <36>
CR_WP#_XD_WP# <36>
For EMI request
CR_PWR_EN <36>
CR_CLK_XD_RY_BY#
38
RDAC
12
CLK_REQ#
2 R?
1
10K_0402_5%
SR_VDDP
SR_VDD
+1.2V_LAN
1
EMI Request...2010/07/27
C691
10U_0603_6.3V6M
SM010005500 500ma 600ohm@100mhz DCR 0.38
20mil
+3V_LAN
1 0.1U_0402_16V4Z
C684
C329
0.01U_0402_16V7K
@
40mil
1
40mil
15
14
<36>
CR_CMD_XD_CLE <36>
R02 Modify
BCM57785XA0KMLG_QFN68_8X8
SR_LX
XTALO
XTALI
15mil
2 LAN_RDAC
1.24K_0402_1%
1
R541
1
2
BLM18AG601SN1D_2P
CR_XD_WE#_SD_DETECT <36>
R562
200_0402_1%
25MHZ 10PF 7V25000014
C294
68
GND PLANE
1
1
1 0_0402_5%
LAN_XTALO_R
LAN_XTALI
Y4
R208 2
4.7K_0402_5%
L18
1
2
BLM18AG601SN1D_2P
+LAN_PCIEPLLVDD
4.7U_0603_6.3V6K
C692
C306
0.1U_0402_16V4Z
+1.2V_LAN
C303
4.7U_0603_6.3V6K
69
CR_PWR_XD_ALE
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
CR_5IN1_LED# <41>
+3V_LAN
L34
+VDDO_CR
GPIO2_MEDIA_SENSE/XD_RE#
R190 1
R226
+3V_LAN
L15
SR_DISABLE/XD_DETECT#
+3VS
R824 (CP_PWR_XD_ALE)
for B0 version
WAKE#
11
31
30
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
2
2
2
2
2
2
2
2
20mil
SD_DETECT/XD_WE#
CR_DATA0 R199
CR_DATA1 R207
CR_DATA2 R211
CR_DATA3 R215
CR_DATA4 R168
CR_DATA5 R171
CR_DATA6 R179
CR_DATA7 R182
+LAN_AVDDH
GPIO1_LR_OUT
SI_EEDATA
CS#_EECLK
2 0_0402_5%
L20
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
C299
.1U_0402_16V7K 1
.1U_0402_16V7K 1
LAN_LINK# <36>
66
SPD100LED#_SERIALDO
PCH_PWR_EN# <20,44>
LAN_MIDI2- <36>
LAN_MIDI2+ <36>
C657
SCLK_SPD1000LED#
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1
PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
+LAN_BIASVDDH
R02 Modify
<14>
<14>
<14>
<14>
60mil
C666
0.1U_0402_16V4Z
48
42
+3V_LAN
1
C662
4.7U_0603_6.3V6K
AVDDH
AVDDH
VDDO
VDDO
VDDO
R02 Modify
+LAN_AVDDL
+LAN_XTALVDDH
C667
0.1U_0402_16V4Z
7
56
62
17
C680
0.1U_0402_16V4Z
+3V_LAN
XTALVDDH
C690
0.1U_0402_16V4Z
VDDC
VDDC
+3V_LAN
R2097
10_0805_5%2
C683
4.7U_0603_6.3V6K
35
61
+3VALW
VDDO_CR
+LAN_BIASVDDH
20
+1.2V_LAN
37
BIASVDDH
U32
+VDDO_CR
C2077
4.7U_0603_6.3V6K
C668
0.1U_0402_16V4Z
C298
0.1U_0402_16V4Z
C671
0.1U_0402_16V4Z
C301
0.1U_0402_16V4Z
C674
0.1U_0402_16V4Z
C302
0.1U_0402_16V4Z
C678
4.7U_0603_6.3V6K
+VDDO_CR
PLACE NEXT P14
20mil
L35
1
2
BLM18AG601SN1D_2P
+LAN_GPHYPLLVDDL
C658
R02 modify
0.1U_0402_16V4Z
+1.2V_LAN
C659
4.7U_0603_6.3V6K
+3V_LAN
L17
1
2
BLM18AG601SN1D_2P
VCC
WP
SCL
SDA
A0
A1
A2
GND
0.1U_0402_16V4Z
1
2
3
4
4.7U_0603_6.3V6K
A
AT24C04BN-SH-T_SO8
SA00004QG00
2011/06/02
Issued Date
Compal Secret Data
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
+1.2V_LAN
C297
U31 @
8
7
6
5
2
R525
1K_0402_5%
2
1
20mil
C656
SPROM_CLK
SPROM_DOUT
R538
1K_0402_5%
2 0.1U_0402_16V4Z
+LAN_AVDDL
AT24C02
C634 1
1
2
R536
1K_0402_5%
SPROM_DOUT
(EEDATA)
2
R537
1K_0402_5%
On chip
SPROM_CLK
(EECLK)
Rev
4019ID
Sheet

1
35
of
60
LAN Connector
C474,C475 and D14

ME interefer,do not pop!!
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
RJ45_MIDI1+
RJ45_MIDI1-
<35> LAN_MIDI0<35> LAN_MIDI0+
LAN_MIDI0LAN_MIDI0+
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
RJ45_MIDI0RJ45_MIDI0+
+3V_LAN
RJ45_GND
LAN_ACTIVITY#
LAN_LINK#
Place close to TCT pin

BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00
2
R385
1
1K_0402_5%1
D14
L30ESDL5V0C3-2
2
@
1
2
40mil
CR_CLK_XD_RY_BY#
CR_CMD_XD_CLE
CR_XD_WE#_SD_DETECT
CR_WP#_XD_WP#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
<35> CR_CLK_XD_RY_BY#
SD_VCC
MS_VCC
XD_VCC
8
16
1
2
4
3
21
19
SD_CLK
SD_CMD
SD_CD
SD_WP
SD/MMC_DAT0
SD/MMC_DAT1
SD/MMC_DAT2
SD/MMC_DAT3
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7
31
32
33
34
35
36
37
38
XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP-IN
22
23
24
25
26
27
28
29
SD_GND
SD_GND
MS_GND
MS_GND
XD_GND
XD_GND
GND
GND
6
13
5
20
30
40
41
42
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
CR_XD_DETECT#
CR_CLK_XD_RY_BY#_23
CR_XD_RE#
CR_PWR_XD_ALE
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
PR1-
RJ45_MIDI1+
PR2+
RJ45_MIDI2+
PR3+
RJ45_MIDI2-
PR3-
RJ45_MIDI1-
PR2-
RJ45_MIDI3+
PR4+
RJ45_MIDI3-
PR4-
C478 1
2 10P_0402_50V8J
C2097 1
B88069X9231T203_4P5X3P2-2
JP2
@
CR_XD_DETECT# <35>
+3VALW
2
G
Q31
SSM3K7002F_SC59-3
GND
VIN
VIN
EN
EPAD
1
2
3
4
<35> CR_PWR_EN
TAITW_R013-P17-HM_NR
CONN@
RJ45_GND
R03 Modify
R04 modify
@
2
R303
0_0805_5%
VOUT
VOUT
VOUT
FLG
8
7
6
5
C421
4.7U_0603_6.3V6K
1
C2092
0.1U_0402_16V4Z
C2091
0.1U_0402_16V4Z
Yellow LED-
+XDPWR_SDPWR_MSPWR
40mil
AP2301MPG-13_MSOP8
+3VALW
12
40mil
U16
R304
300_0603_5%
C381
0.1U_0402_16V4Z
+3VS
MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS
R04 modify
10
9
12
15
17
14
7
Yellow LED+
+VDDO_CR
CR_XD_RE# <35>
CR_XD_CE#_MS_INS# <35>
CR_CMD_XD_CLE <35>
CR_PWR_XD_ALE <35>
CR_XD_WE#_SD_DETECT <35>
CR_WP#_XD_WP# <35>
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_CLK_XD_RY_BY#_17
CR_XD_CE#_MS_INS#
CR_CMD_XD_CLE
11
LANGND
2 120P_1206_2KV8J
@
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
14
13
EMI Request
1
J10
JUMP_43X118
@
SHLD1
SHLD2
SANTA_130451-K
CONN@
11
18
39
C475
JREAD1
+XDPWR_SDPWR_MSPWR
PR1+
RJ45_MIDI0-
RJ45_GND
Card Reader Connector
Green LED-
68P_0402_50V8J
2
@ JP1
B88069X9231T203_4P5X3P2-2
2
1
R04 modify for EMI
10
1
LAN_ACTIVITY#
<35> LAN_ACTIVITY#
Green LED+
RJ45_MIDI0+
@ C832
100P_0402_50V8J
C476
220P_0402_50V7K
LAN_LINK#
<35> LAN_LINK#
2
R491
75_0603_1%
2
1
R490
75_0603_1%
IH-160
SP050006F00
JRJ45
9
LAN_MIDI1+
LAN_MIDI1-
C474 68P_0402_50V8J
@
2
1
<35> LAN_MIDI1+
<35> LAN_MIDI1-
RJ45_MIDI2RJ45_MIDI2+
D36
L30ESDL5V0C3-2
21
20
19
B88069X9231T203_4P5X3P2-2
MCT2
MX2+
MX2-
C434
0.1U_0402_16V4Z
TCT2
TD2+
TD2-
4
5
6
JP3
LAN_MIDI2LAN_MIDI2+
<35> LAN_MIDI2<35> LAN_MIDI2+
RJ45_MIDI3+
RJ45_MIDI3-
C433
0.1U_0402_16V4Z
24
23
22
1
1K_0402_5%
2
1
R493
75_0603_1%
2
1
R492
75_0603_1%
1
MCT1
MX1+
MX1-
C620
0.1U_0402_16V4Z
TCT1
TD1+
TD1-
C619
0.1U_0402_16V4Z
1
2
3
C618
0.1U_0402_16V4Z
LAN_MIDI3+
LAN_MIDI3-
C617
0.1U_0402_16V4Z
<35> LAN_MIDI3+
<35> LAN_MIDI3-
2
R384
1
2
L53
100UH_SSC0301101MCF_0.18A_20%
+3V_LAN
C473
220P_0402_50V7K
T28
R02 modify for SD3.0 issue

CR_CLK_XD_RY_BY#
1
R2088
2
10_0402_5%
CR_CLK_XD_RY_BY#_17
R2102 1
2 0_0402_5%
C2094
R2101
1
22_0402_5%
CR_CLK_XD_RY_BY#_23
C2096
6P_0402_50V8D
@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
6.8P_0402_50V8C
Custom
Date:
Rev
4019ID
Sheet

1
36
of
60
For Wireless LAN or MSATA

+3VS
2
R352
1
0_0805_5%
2
R2040 @
+1.5VS
+3VS_FULL
C455
4.7U_0603_6.3V6K
60mil
1
0_0805_5%
+1.5VS_FULL
+1.5VS_FULL
R02 Modify
+3VS_FULL
1
1
C467
C442
C441
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C443
@
@
4.7U_0603_6.3V6K
2
2
2
@
2
R02 Modify
C466
0.1U_0402_16V4Z
<14> PCIE_PRX_DTX_N2
<14> PCIE_PRX_DTX_P2
<14> PCIE_PTX_C_DRX_N2
<14> PCIE_PTX_C_DRX_P2
R2044
R2045
1 PCIE@ 2 0_0402_5%
1 PCIE@ 2 0_0402_5%
WWAN_PRX_C_DTX_P1
WWAN_PRX_C_DTX_N1
R2046
R2047
1 PCIE@ 2 0_0402_5%
1 PCIE@ 2 0_0402_5%
WWAN_PTX_C_DRX_N1
WWAN_PTX_C_DRX_P1
SATA_PRX_DTX_P1 mSATA@ 2
C2045
SATA_PRX_DTX_N1 mSATA@ 2
C2046
SATA_PTX_DRX_N1 mSATA@ 2
C2047
SATA_PTX_DRX_P1 mSATA@ 2
C2048
<40> WLAN_PME#
@R?
@
R?
0_0402_5%
1
2
<35,40> EC_PME#
WWAN_PRX_C_DTX_P1
0.01U_0402_16V7K
1 WWAN_PRX_C_DTX_N1
0.01U_0402_16V7K
1 WWAN_PTX_C_DRX_N1
0.01U_0402_16V7K
1 WWAN_PTX_C_DRX_P1
0.01U_0402_16V7K
+1.5VS_FULL
<15,35> PCH_PCIE_WAKE#
@ R702
0_0402_5%
1
2
R2060
1 PCIE@ 2 0_0402_5%
MINI1_CLKREQ#_R
R2061
R2062
1 PCIE@ 2 0_0402_5%
1 PCIE@ 2 0_0402_5%
CLK_PCIE_MINI1#_R
CLK_PCIE_MINI1_R
<14> MINI1_CLKREQ#
<14> CLK_PCIE_MINI1#
<14> CLK_PCIE_MINI1
R?
0_0402_5%
1
2PCH_PCIE_WAKE#_R
MSATA_DET#
E51RXD_P80CLK_R
2 mSATA@1
R2058
0_0402_5%
<18> MSATA_DET#
WWAN_PRX_C_DTX_P1
WWAN_PRX_C_DTX_N1
WWAN_PTX_C_DRX_N1
WWAN_PTX_C_DRX_P1
BT
on module
Enable
Disable
SUSP#
<40,44,47,49,50> SUSP#
BT_CTRL
2
R288
1
1K_0402_5%
E51TXD_P80DATA_R
E51RXD_P80CLK_R
2 0_0402_5%
2 0_0402_5%
R300
100K_0402_5%
+3VALW
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
53
GNDGND
54
WL_OFF#
PLT_RST_BUF#
WL_OFF# <18>
PLT_RST_BUF# <17,35,40>
+3VS_FULL
MINI1_SMBCLK R337 1
MINI1_SMBDATA R335 1
@
@
2 0_0402_5%
2 0_0402_5%
PCH_SMBCLK <14>
PCH_SMBDATA <14>
USB20_N8 <17>
USB20_P8 <17>
MINI1_LED#
MINI1_LED# <40>
(9~16mA)
R305
100K_0402_5%
ACES_51711-0520W-001
+3VS_FULL
CONN@
BT_ON#
R299 1
R287 1
<40> E51TXD_P80DATA
<40> E51RXD_P80CLK
Q57
2
G
SSM3K7002F_SC59-3 S
<18,39> BT_ON#
BT_CTRL
BT_CTRL
@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
BT
on module
WLAN&BT Combo module circuits
+3VS_FULL
D32
+3VS_FULL
JMINI1
+3VS_FULL
60mil
+3VS_FULL
@
2
R2111
1
0_0805_5%
Q?
AO3419L_SOT23-3
4.7U_0603_6.3V6K
C?
40mil(1A)
23VSWLAN_GATE_R
100K_0402_5%
R?
3VSWLAN_GATE
1K_0402_5%
3
5
4
Q2010B
C2100
0.1U_0402_16V7K
<40> WLAN_ON
C2099
0.1U_0402_16V7K 3VSWLAN_R
R?
1K_0402_5%
1
2
R?
470_0603_5%
1
R?
+3VALW
3VSWLAN_GATE
Q2010A
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

E
37
of
60
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
38
of
60
Deafult use PCH side USB3.0 signal
Deafult use PCH side USB3.0 signal
<17> PCH_USB3_TX1_N
<17> PCH_USB3_TX1_P
1 @
2 0_0402_5%
C432
.1U_0402_16V7K
1
2
L3PUSB3@
2
U3TXDN1
U3TXDP1
U17
1
2
3
4
<44> SYSON#
1 @
GND
VIN
VIN
EN
AP2301MPG-13_MSOP8
OCE2012120YZF_0805
R10
+USB3_VCCA
EPAD
R9
PUSB3@
2
1PCH_USB3_TX1_N_C
CI18
0.1U_0402_16V4Z
PUSB3@
2
1PCH_USB3_TX1_P_C
CI19
0.1U_0402_16V4Z
+5VALW
VOUT
VOUT
VOUT
FLG
8
7
6
5
W=60mils
1
PUSB@
R314 2
0_0402_5%
USB_OC0# <17>
R05 modify
For USB2.0 ESD request
2 0_0402_5%
1
R11
1 @
2 0_0402_5%
2
L4PUSB3@
PCH_USB3_RX1_N
<17> PCH_USB3_RX1_N
C417
0.1U_0402_16V4Z
R02 modify
3
R12
1 @
U3RXDP1
OCE2012120YZF_0805
For ESD request
2 0_0402_5%
D35 @
U3TXDP1
10
U3TXDP1
U3TXDN1
U3TXDN1
U3RXDP1
U3RXDP1
U3RXDN1
1 @
<17> USB20_P0
R687
L52 PUSB@
2 2
3
U2DP0
U3RXDN1
U3TXDP1
U3TXDN1
U2DP0
U3TXDN1
U2DP0
USB3.0 Conn.
JUSB1
9
1
8
3
7
2
6
4
5
U2DN0
U3RXDP1
U3RXDN1
U3RXDN1
U3TXDP1
U2DN0
U3RXDP1
For USB2.0 ESD request
+USB3_VCCA
R03 modify
U2DP0
I/O4
I/O2
VDD
GND
I/O3
I/O1
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
GND
GND
GND
GND
10
11
12
13
ACON_TARA4-9K1311
CONN@
L05ESDL5V0NA-4
D24
WCM-2012-900T_0805
U2DN0
1 @
2
R686
0_0402_5%
<17> USB20_N0
0_0402_5%
2
C390
220U_6.3V_M
for ESD
C391
470P_0402_50V7K
PCH_USB3_RX1_P
<17> PCH_USB3_RX1_P
+USB3_VCCA
W=60mils
U3RXDN1
DC233007O00
U2DN0
AZC099-04S.R7G_SOT23-6
R04 modify
USB/B Conn.
C2070
0.1U_0402_16V4Z
(Port 0,2)
2
SYSON#
1
<17> USB20_N2
<17> USB20_P2
<17> USB20_N1
<17> USB20_P1
USB20_N1
USB20_P1
JUSB2
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
10
9
GND
GND
+BT_VCC
(Port 13)
13
14
JBT1
GND 8
7
6
5
4
3
2
GND 1
8
7
6
5
4
3
2
1
<18,37> BT_ON#
(WLAN_BT_DATA)
(WLAN_BT_CLK)
BT_ON#
USB20_P11 <17>
USB20_N11 <17>
1 BT@
2
R710
10K_0402_5%
C738
BT@
0.1U_0402_16V4Z
WL_EN# <18>
Q41
BT@
C731
BT@
1U_0603_10V6K
AP2301GN-HF_SOT23-3
W=40mils
+BT_VCC
1
ACES_87213-0800G
CONN@
BT Wire Cable Note:

Pin 3, Pin 4 NC
ACES_85201-1205N
CONN@
4.7U_0603_6.3V6K
C730
BT@
C729
BT@
R709
300_0603_5%
BT@
2
0.1U_0402_16V4Z
R05 modify
USB20_N2
USB20_P2
+3VS
+5VALW
BT Conn.
W=100mils
+5VALW
for ESD
R02 modify
Q42
2
G
SSM3K7002F_SC59-3 S
BT@
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

E
39
of
60
+3VS
C714
22P_0402_50V8J
2
1
R675
33_0402_5%
2
1
@
EC_MUTE#
R317
TP_CLK
R363
4.7K_0402_5%
TP_DATA
R364
4.7K_0402_5%
1 10K_0402_5%
CLK_PCI_LPC
KSO2
2 1K_0402_5%
EC_SMI#
2 2.2K_0402_5%
R2110
2 100K_0402_5%
EC_PME#
2 4.7K_0402_5%
WLAN_PME#
CLK_PCI_LPC
PLT_RST_BUF#
EC_RST#
EC_SCI#
WLAN_ON
<17> CLK_PCI_LPC
<17,35,37> PLT_RST_BUF#
<18> EC_SCI#
<37> WLAN_ON
2 2.2K_0402_5% EC_SMB_CK2
R361
2 2.2K_0402_5% EC_SMB_DA2
R685
2 10K_0402_5% EC_SCI#
R360
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
6
14
15
16
17
18
19
25
FAN_SPEED1
28
EC_PME#
29
E51TXD_P80DATA
30
E51RXD_P80CLK
31
R283 2 9012@ 10_0402_5% PCH_PWROK_901232
PWR_SUSP_LED#
34
WLAN_LED#
36
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
KSI[0..7]
<41> KSI[0..7]
KSO[0..17]
<41> KSO[0..17]
R02 modify
for ESD
C2074 1
2 0.1U_0402_16V4Z PLT_RST_BUF#
C2071 1
2 0.1U_0402_16V4Z PM_SLP_S3#
C2072 1
2 0.1U_0402_16V4Z PM_SLP_S4#
X1
32.768KHZ_12.5PF_CM31532768DZFT
EC_XCLK1 2
1EC_XCLK0
C723
@
3
15P_0402_50V8J
15P_0402_50V8J
Board ID
+3VALW
2
Analog Board ID definition,

Please see page 3.
R354
100K_0402_5%
AD_BID0
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
PCH_PWR_EN
MINI1_LED#
GPU_HOT#
<15> PM_SLP_S3#
<15> PM_SLP_S5#
<18> EC_SMI#
R03 modify
<44> PCH_PWR_EN
<37> MINI1_LED#
<53> GPU_HOT#
<43> FAN_SPEED1
<35,37> EC_PME#
<37> E51TXD_P80DATA
<37> E51RXD_P80CLK
<15> PCH_PWROK
<41> PWR_SUSP_LED#
<41> WLAN_LED#
<15> SUSCLK
Ra
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
R353
56K_0402_5%
Rb
ECAGND
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
68
70
71
72
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
83
84
85
86
87
88
EC_MUTE#
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00
97
98
99
109
VGATE
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
119
120
126
128
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
73
74
89
90
91
92
93
95
121
127
ENBKL
KB930_PECI
FSTCHG
BATT_BLUE_LED#
GPU_OVERT
PWR_LED
BATT_AMB_LED#
SYSON
VR_ON
PM_SLP_S4#
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
EC_LID_OUT#
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
110
112
114
115
116
117
118
V18R
124
BEEP#
ACOFF <45>
C452 2
BATT_TEMP
R697
EC_XCLK1
EC_XCLK0
0_0402_5%
122
123
C454
0.1U_0402_16V4Z
R769 2
1 100K_0402_5%
2
R04 modify
1
C834
XCLKI/GPIO5D
XCLKO/GPIO5E
D23
1 100P_0402_50V8J ECAGND
BATT_TEMP <46>
ADP_I
AD_BID0
EC_ACIN
2 10K_0402_5%
R02 Modify
9012@ 1
930@
R676
BEEP# <42>
ACOFF
EN_DFAN1
EN_DFAN1 <43>
1
RB751V-40_SOD323-2
C719
GPIO
Bus
GPIO
GPI
ACIN <15,44,47,48>
1 100P_0402_50V8J
R367
0_0402_5%
2
1
VR_HOT#
<52> VR_HOT#
EC_MUTE# <42>
WLAN_PME#
EAPD
TP_CLK
TP_DATA
H_PROCHOT# <5,46>
D
Q26
2N7002H_SOT23-3
2
G
R02 Modify
WLAN_PME# <37>
EAPD <42>
TP_CLK <41>
TP_DATA <41>
Latest design guide suggest change to

74LVC1G06.
+3VALW
VGATE <15,52>
ME_EN
2
R880
1
R2063
SPI Device Interface

SPI Flash ROM
+3VALW
200K_0402_5%
H_PROCHOT#_EC
PS2 Interface
+3VLP
200K_0402_5%
1
ADP_I <46,47>
ME_EN <13>
1
0_0402_5%
2
+3VLP
47K_0402_5%
R05 Modify
R02 Modify
VCIN0_PH <46>
LID_SW#
R696
1 100K_0402_5%
2
1
R691 100K_0402_5%
C721
<46,47>
<46,47>
<14,22>
<14,22>
63
64
65
66
75
76
DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
R735
R2085
R02 Modify
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
+3VS
2
12
13
37
20
38
BKOFF#
PWM Output
AGND/AGND
R807
EC_SMB_CK1
+3VS
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
69
2 2.2K_0402_5%
EC_SMB_DA1
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
C457
0.1U_0402_16V4Z
21
23
26
27
GND/GND
GND/GND
GND/GND
GND/GND
GND0
R358
<18> GATEA20
<18> EC_KBRST#
<13> SERIRQ
<13> LPC_FRAME#
<13> LPC_AD3
<13> LPC_AD2
<13> LPC_AD1
<13> LPC_AD0
1
2
3
4
5
7
8
10
11
24
35
94
113
R359
GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
+3VLP
2 47K_0402_5%
+5VS
+3VALW
1 930@
R682
1 930@ 2
R875
0_0402_5%
1 9012@ 2
R876
0_0402_5%
67
R339
U20
EC_VDD/AVCC
KSO1
+EC_VCC
+EC_VCC
9
22
33
96
111
125
2 47K_0402_5%
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
1 930@
C399
1000P_0402_50V7K
R336
C400
1000P_0402_50V7K
+3VALW
C720
0.1U_0402_16V4Z
C728
0.1U_0402_16V4Z
1
0_0805_5%
0.1U_0402_16V4Z
C456
0.1U_0402_16V4Z
C431 2
+3VALW_EC
2
C418
0.1U_0402_16V4Z
+3VALW
1
EC_RST#
1 47K_0402_5%
L21
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
R2038
+3VALW
R328 2
H_PROCHOT#_EC
GPXIOA07
BKOFF#
PBTN_OUT#
GPU_ACIN
SA_PGOOD
EC_ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
GPU_THERMAL_ALERT#
ENBKL <16> R355 2

930@ 1 43_0402_1%
FSTCHG <47>
BATT_BLUE_LED# <41>
R02
Modify
GPU_OVERT <22>
PWR_LED <41>
BATT_AMB_LED# <41>
SYSON <44,49>
VR_ON <52>
R2059
PM_SLP_S4# <15>
147K_0402_5%
2
H_PECI <5,18>
Modify R05
PCH_RSMRST# <15>
EC_LID_OUT# <18>
@ R891
2 0_0402_5%
1
BKOFF# <31>
PBTN_OUT# <15>
GPU_ACIN <22> R02
SA_PGOOD <51>
VCIN1_PROCHOT <46>
R894 2 930@
1 0_0402_5% PCH_PWROK
R893 2 @
1 0_0402_5% MAINPWON
Modify
EC_ON <41,48>
ON/OFF <41>
LID_SW# <41>
SUSP# <37,44,47,49,50>
GPU_THERMAL_ALERT# <22>R02
MAINPWON <46,48>
Modify R04
Modify
KB9012_PECI R898 2 9012@ 1 43_0402_1% H_PECI

+V18R
1
C398
KB9012QF-A2_LQFP128_14X14
4.7U_0603_6.3V6K
R03 Modify
R04 Modify
Co_lay NPCE885N Delete Co_lay NPCE885N
20mil
L23
ECAGND 2
1
FBMA-L11-160808-800LMT_0603
R02 Modify
20P_0402_50V8J
Follow KB930 checking List

+3VALW
R02 Modify
R2086 2
1 10K_0402_5%
R2087 2
1 10K_0402_5%
GPU_OVERT
GPU_THERMAL_ALERT#
Compal Secret Data
Issued Date
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

E
40
of
60
ON/OFF BTN
+3VALW
+3VLP
Test Only
Bottom Side
R144
100K_0402_5%
930@
R907
9012@
100K_0402_5%
@ SW1
SMT1-05-A_4P
1
3
+3VS
JKB1
PCH_SATALED# <13>
2
G
R104
930@
10K_0402_5%
Q7
SSM3K7002F_SC59-3
930@
CR_5IN1_LED# <35>
51ON# <45>
LED3
HT-191NB5_BLUE
+5VS
1
R380
2
680_0402_5%
27
28
PWR/B
MEDIA_LED#
JPWR1
LED7
HT-191NB5_BLUE
+3VS
KSO7
C252 1
100P_0402_50V8J
KSO14
C259 1
100P_0402_50V8J
KSO6
C251 1
100P_0402_50V8J
KSO13
C258 1
100P_0402_50V8J
KSO5
C250 1
100P_0402_50V8J
KSO12
C257 1
100P_0402_50V8J
KSO4
C249 1
100P_0402_50V8J
KSI0
C263 1
100P_0402_50V8J
KSO3
C248 1
100P_0402_50V8J
KSO11
C256 1
100P_0402_50V8J
KSI4
C267 1
100P_0402_50V8J
KSO10
C255 1
100P_0402_50V8J
KSO2
C247 1
100P_0402_50V8J
EMI request
WLAN_LED#
WLAN_LED# <40>
HT-191UD5_AMBER
100P_0402_50V8J
TP Conn.
R03 modify
LED6
+5VALW
@
1
R379
2
560_0402_5%
1
R2117
2
51_0402_5%
HT-191NB5_BLUE
BATT_GRN_LED#
+5VS
+3VS
BATT_BLUE_LED# <40>
JTP1
100P_0402_50V8J
KSO0
C245 1
100P_0402_50V8J
C254 1
100P_0402_50V8J
KSI5
C268 1
100P_0402_50V8J
KSI3
C266 1
100P_0402_50V8J
KSI6
C269 1
100P_0402_50V8J
KSO8
C253 1
100P_0402_50V8J
KSI7
C270 1
100P_0402_50V8J
1
2
3
4
5
6
7
8
GND
GND
LED2
@
1
R376
+3VALW
1
R2118
BATT_AMB_LED#
2
560_0402_5%
2
390_0402_5%
HT-191UD5_AMBER
BATT_AMB_LED# <40>
@
1
R374
2
560_0402_5%
D_CK_SDATA
@
D4
AZ5125-02S
+5VS
PWR_SUSP_LED#
2
C2162
100P_0402_50V8J 100P_0402_50V8J
1
PWR_SUSP_LED# <40>
TP_CLK
LEFT_BTN#
TP_DATA
RIGHT_BTN#
@
D3
AZ5125-02S
C2104
1
1
Q32
SW2
SMT1-05-A_4P
1
2
5
6
2
R512
100K_0402_5%
LEFT_BTN#
SSM3K7002F_SC59-3
RIGHT_BTN#
LEFT_BTN#
RIGHT_BTN#
R04 modify
SW3
SMT1-05-A_4P
1
C2106
C2107
56P_0402_50V8K56P_0402_50V8K
5
6
PWR_LED#
2
G
C2105
56P_0402_50V8K56P_0402_50V8K
HT-191UD5_AMBER
<40> PWR_LED
D_CK_SCLK
TP_VDD
C196
0.1U_0402_16V4Z
+3VALW
2
390_0402_5%
C217
2
51_0402_5%
LED1
1
R378
C2101
56P_0402_50V8K
1
R2119
HT-191NB5_BLUE
+3VALW
C2102
C2103
56P_0402_50V8K56P_0402_50V8K
1
D_CK_SDATA <11,12,14> 1
PWR_LED#
1 R2099
1 R2100
TP_CLK <40>
TP_DATA <40>
LEFT_BTN#
RIGHT_BTN#
ACES_85201-0805N
CONN@
LED5
+5VALW
D_CK_SCLK <11,12,14>
0_0402_5% 2
0_0402_5% 2
C265 1
KSO9
TP_VDD
TP_VDD
KSI2
D_CK_SCLK
TP_VDD
1
2
3
4
5
6
7
8
9
10
2
390_0402_5%
C246 1
1
R377
KSO1
ACES_85201-0805N
CONN@
LED4
+3VS
100P_0402_50V8J
100P_0402_50V8J
+3VS
PWR_LED#
ON/OFFBTN#
C260 1
+3VALW
LID_SW# <40>
LID_SW#
C262 1
KSO15
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
GND
GND
KSO17
100P_0402_50V8J
2
130_0402_5%
1
R2116
C261 1
100P_0402_50V8J
G1
G2
KSO16
EC_ON
<40,48> EC_ON
KB Conn.
C264 1
U8
MEDIA_LED#
5
KSO[0..17] <40>
D6
CHN202UPT_SC70-3
KSI[0..7] <40>
KSO[0..17]
51ON#
6
5
2
KSI[0..7]
ON/OFF <40>
R496
10K_0402_5%
ACES_85201-26051
CONN@
KSI1
2
ON/OFFBTN#
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
R04 modify
Delete SW5,SW6
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet
41
8
of
60
2
0_0805_5%
U40
0.1U_0402_16V4Z
SM010014520 3000ma 220ohm@100mhz DCR 0.04
1
D30
2
C771 1
<13> PCH_SPKR
C750
10U_0603_6.3V6M
2
B
560_0402_5%
1U_0402_6.3V6K
R724
2
1U_0402_6.3V6K
D
1
1U_0402_6.3V6K
MONO_IN
1
R729
Q44
2
2.4K_0402_1%
2SC2411K_SOT23-3
560_0402_5%
D29
+PVDD1_HDA
HD Audio Codec
20mil
0.1U_0402_16V4Z
1
1
C749
1U_0402_6.3V6K
C759 1
<40> BEEP#
R713
0_0603_5%
R723
C766
2
1
20mil
Place near Pin46
L50 2
1
FBMA-L11-201209-221LMA30T_0805
C739
R728
10K_0402_5%
10K_0402_5%
+PVDD_HDA
SM010014520 3000ma 220ohm@100mhz DCR 0.04

+VDDA
R725
+VDDA
1
2
SHDN
BYP
C741
G9191-475T1U_SOT23-5 0.01U_0402_16V7K
@
@
(output = 300 mA)
+PVDD_HDA
0.1U_0402_16V4Z
L46 2
1
FBMA-L11-201209-221LMA30T_0805
1
1
@
@
C748
C745
10U_0603_6.3V6M
2
2
R02 Modify
R712
10K_0402_5%
+3VS
4.75V
+VDDA
GND
OUT
C737
40mil
IN
60mil 1
1
1
R711
+5VS
+VDDA
R02 Modify
SM010030010 200ma 120ohm@100mhz DCR 0.2
Place near Pin39
C769 1
C765 1
C764 1
MIC1_L
<43> MIC1_L
MIC1_R
<43> MIC1_R
C762 1
1
Combo MIC
C755
2.2U_0402_6.3V6M
+MIC2_VREFO
LINE2_R
16
MIC2_L
17
23
24
LINE1_R
21
C760
46
MIC2_R
SPK_OUT_L-
41
SPKL-
LINE1_L
SPK_OUT_R+
45
SPKR+
SPK_OUT_R-
44
SPKR-
HPOUT_L
32
HP_LEFT
HP_LEFT <43>
HPOUT_R
33
HP_RIGHT
HP_RIGHT <43>
SDATA_IN
SDATA_OUT
MIC1_L
36
CBP
29
MIC2_VREFO
31
1
2
3
4
G1
G2
SYNC
10
RESET#
11
20mil
SPKL+
SPKL-
HDA_SDIN0_AUDIO 1 R721
2
33_0402_5%
HDA_SDOUT_AUDIO
HDA_SYNC_AUDIO
L2006 1
L2005 1
JSPK2
2 FBMA-L11-160808-800LMT_0603
2 FBMA-L11-160808-800LMT_0603
SPK_L+
SPK_L-
1
2
1
2
D1
AZ5125-02S
3
4
G1
G2
ACES_88266-02001
CONN@
HDA_SDIN0 <13>
<13>
<13>
MIC1_VREFO_R
BCLK
HDA_RST_AUDIO# <13>
HDA_BITCLK_AUDIO
MIC1_VREFO_L
19
<13>
@
2 C757
22P_0402_50V8J
@
1
2
1
R717 0_0402_5%
28
1
20K_0402_1%
SPKL+
CBN
10mil
2
10U_0603_6.3V6M
R02 Modify
2
R730
40
MIC1_R
1
2
ACES_88266-02001
CONN@
SPK_OUT_L+
35
10mil
+MIC1_VREFO
+INTMIC_VREFO
D2
AZ5125-02S
35mA
68mA 600mA
22
30
External MIC
DVDD
15
10mil
Internal MIC
B
LINE2_L
39
MIC1_C_L
2
4.7U_0603_6.3V6K
MIC1_C_R
2
4.7U_0603_6.3V6K
C763 1
14
38
U41
LINE2_C_L
4.7U_0603_6.3V6K
LINE2_C_R
2
4.7U_0603_6.3V6K
MIC2_C_L
2
4.7U_0603_6.3V6K
MIC2_C_R
2
4.7U_0603_6.3V6K
2
DVDD_IO
2
R719
1 COM_MIC_R
1K_0402_5%
C770 1
JSPK1
SPK_R+
SPK_R-
2 FBMA-L11-160808-800LMT_0603
2 FBMA-L11-160808-800LMT_0603
External MIC
INT_MIC
1
1K_0402_5%
2
1000P_0402_50V7K
SPKR+ L2003 1
SPKR- L2004 1
<43> COM_MIC
COM_MIC
2
R726
1
C2054
Int. Speaker Conn.

20mil
Place near Pin1, 9
Place near Pin25, 38

INT_MIC_R
+3VS
Combo MIC
C752
2
0.1U_0402_16V4Z
PVDD2
Internal MIC
L48 2
1
BLM18AG121SN1D_0603
1
C753
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
PVDD1
1
C761
C772
2
R02 Modify
<43> INT_MIC_R
25
C756
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C754
AVDD2
+VDDA
+AVDD_HDA
10mil
0.1U_0402_16V4Z
1
1
AVDD1
L51 2
1
BLM18AG121SN1D_0603
+3VS_DVDD
10mil
SM010030010 200ma 120ohm@100mhz DCR 0.2
LDD_CAP
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
PD#
JDREF
For EMI
EC_MUTE# <40>
C758
HP_PLUG#
2
1
R731
39.2K_0402_1%
MIC_PLUG#
2
1
R727
20K_0402_1% MIC2JD
<43> HP_PLUG#
<43> MIC_PLUG#
2 2.2U_0402_6.3V6M
34
10mil
SENSE_A
SENSE_B
EAPD_R
CPVEE
13
18
47
SENSE A
SENSE B
EAPD
48
SPDIFO
PCBEEP
12
MONO_OUT
AVSS2
20
37
VREF
27
MONO_IN
CODEC_VREF C767 1
C768 1
10mil
<40> EAPD
R718 1 271X@ 2 20K_0402_1%

R715 1 271X@ 2 0_0402_5%
+MIC2_VREFO
DVSS
GND
DGND
R2056 1 281X@ 2 0_0402_5%
AVSS1
PVSS2
PVSS1
ALC271X-VB6-CG_QFN48_6X6
C2073 1
MIC2JD
A
R03 modify
AGND
R722
2.2K_0402_5%
2
1
1
R720
22K_0402_5%
COM_MIC
R791
22K_0402_5%
Issued Date
R02 Modify
PJ23
@ JUMP_43X39
1 1
2 2
PJ24
@ JUMP_43X39
1 1
2 2
PJ25
@ JUMP_43X39
1 1
2 2
PJ26
@ JUMP_43X39
1 1
2 2
2011/06/02
GNDA
2012/06/02
Deciphered Date
GND
GNDA
Title
SCHEMATIC,MB A7912
Custom
Date:
PJ22
@ JUMP_43X39
1 1
2 2
Compal Secret Data
C746
10U_0603_6.3V6M
2
PJ21
@ JUMP_43X39
1 1
2 2
GND
2
G
3
271X@ Q43
BSS138_NL_SOT23-3
for ESD
2 0.1U_0402_16V4Z
Place next pin27
26
43
42
EAPD_R
7
49
R2057
0_0402_5%
@
R02 modify
2 0.1U_0402_16V4Z
2 10U_0603_6.3V6M
@
Rev
4019ID
Sheet

1
42
of
60
<42> HP_LEFT
HP_LEFT R716 1
2 47_0603_1%
<42> HP_RIGHT
HP_RIGHT R714 1
2 47_0603_1%
Singatron 2SJ2326
DC021007151
Headphone
Out
JHP1
C747
330P_0402_50V7K
330P_0402_50V7K
1
FBMA-L11-160808-800LMT_0603 1
L49
HPOUT_L_1
HPOUT_L_2
1
2
L47
HPOUT_R_1 1
HPOUT_R_2
2
FBMA-L11-160808-800LMT_0603
COM_MIC
<42> COM_MIC
3
6
+INTMIC_VREFO
1
2
4
HP_PLUG#
<42> HP_PLUG#
SM010004010 300ma 70ohm@100mhz DCR 0.3
C751
R02 Modify
5
2
15mil
CONN@
COM_MIC
2
220P_0402_50V7K
D16
AZ5125-02S
JMIC1
MIC1_L_R
MIC1_R_R
MIC JACK
1
2
<42> MIC_PLUG#
C733
MIC_PLUG# 5
220P_0402_50V7K
D25
AZ5125-02S
6
SINGA_2SJ-A960-C01
CONN@
220P_0402_50V7K
4
C732
FAN Stand-Off
FAN1 Conn
H8
H_3P0
H3
H_3P4
@
H9
H_3P0
JUSB3 Stand-Off
H10
H_3P0
H7
H_3P4
@
H2
H_3P4
H1
H_3P4
+5VS
INT_MIC_L
R708
4.7K_0402_5%
H11
H_3P0
H12
H_3P0
H13
H_3P0
H14
H_3P0
H15
H_3P0
H16
H_3P0
H17
H_3P5
H18
H_3P0
10U_0603_6.3V6M
2
C580
1
R02 Modify
@
<42> MIC1_R
G1
G2
D1001
AZ5125-02S
D27
1
<42> MIC1_L
MIC1_L
1
R707
MIC1_R 1
R706
R705
4.7K_0402_5%
FBMA-L11-160808-800LMT_0603
L45
2 MIC1_L_1
1
2
1K_0603_5%
L44
2 MIC1_R_1
1
2
1K_0603_5%
FBMA-L11-160808-800LMT_0603
3
4
ACES_88266-02001
CONN@
D26
1
2
C500
+MIC1_VREFO
D28
AZ5125-02S
JMIC2
1
2
HP_PLUG#
Int. MIC
15mil
L24
1
2 INT_MIC_L
FBMA-L11-160808-800LMT_0603
INT_MIC_R
<42> INT_MIC_R
SINGA_2SJ2326-001111
MIC_PLUG#
For EMI
R394
10K_0402_5%
U30
H19
H_4P0
H20
H_4P0
R02 Modify
@
APL5607KI-TRG_SO8
C585
10U_0603_6.3V6M
1
2
H25
H_7P0N
@
H27
H_3P5X3P0N
H28
H_3P5N
JFAN1
H26
H_3P0N
1
2
3
FD1
FD3
@
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FD4
@
FIDUCIAL_C40M80
2011/06/02
Deciphered Date
FIDUCIAL_C40M80
Compal Secret Data
Issued Date
FD2
ACES_85205-03001
CONN@
C579
1000P_0402_50V7K
R03 modify
H24
H_4P2
H23
H_4P2
40mil
+VCC_FAN1
<40> FAN_SPEED1
H22
H_4P2
H21
H_4P2
R489
10K_0402_5%
C587
1000P_0402_50V7K
1
2
+3VS
C598
0.1U_0402_16V4Z
8
7
6
5
GND
GND
GND
GND
2
R509
EN
VIN
VOUT
VSET
<40> EN_DFAN1
1
2
3
4
+VCC_FAN1
1
300_0402_5%
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet
43
of
60
C29
GM@
0.1U_0603_25V7K
1
6
@ R2107
2
10_0402_5%2
Q3A
DIS@
VGA_PWROK#
VGA_ON#
+5VALW
2
R02 Modify
R251
10K_0402_5%
R383
100K_0402_5%
<39> SYSON#
Q4
SSM3K7002F_SC59-3
@
2
G
SYSON
JUMP_43X118
R369
150_0603_5%
1
C821
1U_0402_6.3V6K
+5VALW
C822
.1U_0402_16V7K
R02 Modify
SUSP
2
4
2
+1.5V
3VS_ON
+5VALW
5VS_ON
+5VALW
1
2
VIN1
VIN1
ON1
VBIAS
ON2
6
7
2
Q34
2 SUSP
G
SSM3K7002F_SC59-3
1 1
14
13
CT1
12
GND
11
CT2
VIN2
VIN2
10
VOUT2
VOUT2
9
8
GPAD
15
@ R2075
100K_0402_5%
+3VS
C953
@1 330P_0402_50V7K
<20,35> PCH_PWR_EN#
2
1
@ 330P_0402_50V7K
C954
Q24
@
SYSON#
2
G
SSM3K7002F_SC59-3
Issued Date

2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Date:
Q2004 @
2N7002E_SOT23-3
Modify R02
Custom
A
@ R2076
100K_0402_5%
TPS22966DPUR_SON14_2X3~D
Compal Secret Data

2011/06/02
2
G
+5VS
Reserved
PCH_PWR_EN#
<40> PCH_PWR_EN
@ R365
470_0603_5%
1 1
Q5
SUSP
2
G
SSM3K7002F_SC59-3
R508
470_0603_5%
VOUT1
VOUT1
47K_0402_5%
2 R927
1
C951
@
1@
2
0.1U_0402_16V4Z
2 R926
1
@ 20K_0402_1%
C952
1@
2
0.1U_0402_16V4Z
+1.8VS
1 1
2
1
1
SUSP#
R29
470_0603_5%
Q23
SUSP
2
G
SSM3K7002F_SC59-3
+5VALW
U46
1
1 2
Modify R05
Modify R03
R366
22_0603_5%
Q2008
2N7002E_SOT23-3
C2059 @
0.1U_0603_25V7K
+3VALW
Q21
@
SSM3K7002F_SC59-3
+1.05VS_VTT
@Q2003A
@
Q2003A
Q2003B @
2
G
PCH_PWR_EN#
VGA_PWROK#
<51> VGA_PWROK#
<51,53> VGA_PWROK
1 200K_0402_5% 3V_GATE
PCH_PWR_EN#
@R2073
@
R2073
470_0603_5%
Q15B
R04 modify
C380
0.1U_0603_25V7K
10mil
R2074 2
+VSB
SUSP
2
G
3
R2103
100K_0402_5%
1
3
D
2
1
6
+0.75VS
<15,40,47,48> ACIN
ACIN
C2056
10U_0805_10V4Z
1
2
3
8
7
6
5
20mil
G
+3VALW
40mil
C2058
1U_0603_10V6K
Q15A
@
R245
470_0603_5%
1.5VS_GATE
1
Q8
SSM3K7002F_SC59-3
S DIS@
+3VALW_PCH
C2057
10U_0805_10V4Z
1
C338
1U_0402_6.3V6K
10mil
R268
510K_0402_5%
SUSP
2
1
R269
200K_0402_5%
+VSB
1
2
3
2
G
DIS@
R135
100K_0402_5%
Use 100k to make sure the

divided voltage is enough!!
+1.5VS
8
7
6
5
VGA_ON#
<51> VGA_ON#
3 1
J11
JUMP_43X79
U2006 @
SI4178DY-T1-GE3_SO8
C339
4.7U_0603_6.3V6K
20mil
C376
0.1U_0402_16V4Z
C377
0.1U_0402_16V4Z
C374
4.7U_0603_6.3V6K
C375
4.7U_0603_6.3V6K
+3VALW TO +3VALW(PCH AUX Power)
U12
AO4430L_SO8
R04 modify
+1.5V
DIS@
R134
100K_0402_5%
+1.5V to +1.5VS
<14,17,25,51,53> VGA_ON
C463
0.1U_0603_25V7K
+3VALW
Q25A
Q25B
3
G
SUSP
+3VALW
C2079
.1U_0402_16V7K
3VS_GATE
+5VS
+1.5VSDGPUH
+5VALW
PJ27
C2084
.1U_0402_16V7K
C2083
.1U_0402_16V7K
C2082
.1U_0402_16V7K
10mil
+1.5V
R373
100K_0402_5%
R02 modify for EMI
C2081
.1U_0402_16V7K
+VSB
PJ28
C2080
.1U_0402_16V7K
R368
47K_0402_5%
2
1
20mil
1
C458
1U_0402_6.3V6K
@
2
C461
4.7U_0603_6.3V6K
C459
4.7U_0603_6.3V6K
C460
4.7U_0603_6.3V6K
JUMP_43X118
@
2
+3VS
U21
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
Q27A
R04 modify
+3VALW TO +3VS
<40,49> SYSON
+3VALW
Q27B
R04 modify
1
2
4
1
R2106
10_0402_5%2
<37,40,47,49,50> SUSP#
ACIN
<15,40,47,48> ACIN
1
@
DIS@ Q3B
@R2105
@
R2105
1
2
0_0402_5%
VGA_ON#
10mil
1.5VSDGPU_GATE
2
1
R27
510K_0402_5%
GM@
2
1
6
R2104 GM@
VGA_PWROK# 10_0402_5%2
R04 modify
C470
0.1U_0603_25V7K
+VSB
GM@
R26
47_0603_5%
DIS@
20mil
DIS@
SUSP
<49> SUSP
DIS@
C826
330U_B2_2.5VM_R15M
Q19B
2 DIS@ 1 DIS@
C514
330U_2.5V_M_R15
SUSP
GM@
1
2
3
R246
100K_0402_5%
C157
1U_0402_6.3V6K
Q19A
+5VALW
+1.5VSDGPU
C156
4.7U_0603_6.3V6K
2 GM@
R28
510K_0402_5%
GM@
C7
4.7U_0603_6.3V6K
5VS_GATE
C819
4.7U_0603_6.3V6K
SUSP
R382
470_0603_5%
C818
4.7U_0603_6.3V6K
10mil
2
1
R372
20K_0402_1%
+VSB
C823
.1U_0402_16V7K
+1.5VSDGPUH
U2
AO4430L_SO8
8
7
6
5
2 GM@ 2 GM@
R02 Modify
C824
1U_0402_6.3V6K
+5VS
C469
1U_0402_6.3V6K
U22
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
C468
4.7U_0603_6.3V6K
20mil
C464
4.7U_0603_6.3V6K
C465
4.7U_0603_6.3V6K
1
1
+1.5VSDGPUH to +1.5VSDGPU for GPU
+5VALW TO +5VS
+5VALW
Rev
4019ID
Sheet

E
44
of
60
VIN
Pre_CHG
PQ1
TP0610K-T1-E3_SOT23-3
PD1
LL4148_LL34-2
2
1
PR4
1K_1206_5%
1
2
B+
PR3
1K_1206_5%
1
2
PR2
1K_1206_5%
1
2
VIN
PC4
1000P_0402_50V7K
PC3
100P_0402_50V8J
PR1
1K_1206_5%
1
2
PC2
100P_0402_50V8J
ACES_50305-00441-001
PC1
1000P_0402_50V7K
1
2
3
4
GND
GND
DC_IN_S2
DC_IN_S1
PJP1
PR5
100K_0402_5%
PL1
SMB3025500YA_2P
1
2
PR6
100K_0402_5%
PR7
100K_0402_5%
<40> ACOFF
2
1
+5VALWP
PQ3
PDTC115EU_SOT323
PQ2
PDTC115EU_SOT323
1 2
1
PD2
BAS40CW_SOT323-3
PJ1
+3VALWP
VIN
PJ2
2
+3VALW
+5VALWP
+5VALW
+1.5V
JUMP_43X118
JUMP_43X118
@ PD3
LL4148_LL34-2
1
@ PR8
@PR8
68_1206_5%
N1
VS
+1.8VSP
1
PJ4
2
+VSB
+1.5VP
JUMP_43X118
PJ5
1 1
2 2
@ PC6
@PC6
0.1U_0603_25V7K
PJ6
2
PJ7
2
+1.8VS +1.05VS_VCCPP
+1.05VS_VTT
JUMP_43X118
PJ8
1 1
2 2
JUMP_43X79
2
2
930@ PR11
22K_0402_1%
1
2
<41> 51ON#
930@ PC5
0.22U_0603_25V7K
JUMP_43X118
1
930@ PR10
100K_0402_1%
PJ3
@ PR9
@PR9
68_1206_5%
2
930@ PQ4
TP0610K-T1-E3_SOT23-3
BATT+
JUMP_43X39
+VSBP
930@ PD4
LL4148_LL34-2
2
1
JUMP_43X118
@
+0.75VSP
PJ9
2
+0.75VS
+VCCSA +1.05VS_DGPUP
JUMP_43X79
PJ11
+VCCSAP
+3VLP
+CHGRTC
PR12
0_0402_5%
1
PJ19
1
JUMP_43X118
+1.05VSDGPU
JUMP_43X118
PJ18
+1.5VSDGPUP
+1.5VSDGPU
JUMP_43X118
Issued Date
Compal Secret Data
2011/06/02
Deciphered Date
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID

D
Sheet
45
of
60
+3VLP
VMB
@ PR14
10K_0402_1%
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
EC_SMB_CK1 <40,47>
<40,48> MAINPWON
@ PR18
47K_0402_1%
@PH2
@
PH2
100K_0402_1%_NCP15WF104F03RC
2
G718TM1U_SOT23-8
VS
+3VALWP
TH
@ PU2B
LM393DR_SO8
7 O
8
P
1
1
@ PR24
1.5M_0402_5%
@ PC11
100P_0402_50V8J
@ PR25
100K_0402_1%
2
@ PD5
LL4148_LL34-2
@ PU2A
LM393DR_SO8
@ PR23
10K_0402_1%
@ PC10
0.022U_0402_16V7K
2
1
D
PQ5A
@ PR22
47K_0402_1%
H_PROCHOT#
VS
VL
MAINPWON
EC_SMB_DA1 <40,47>
@PU1
@
PU1
@ PR16
100K_0402_1%
BATT_TEMP <40>
@ PR13
10K_0402_1%
1
2
PR102
0_0402_5%
@ PC7
0.1U_0603_25V7K
1
2
PC9
0.01U_0402_25V7K
PR19
1K_0402_5%
1
1
2
PR21
1K_0402_1%
1
2
+3VALWP
PC8
1000P_0402_50V7K
1
PR17
100_0402_1%
PR15
100_0402_1%
PR20
6.49K_0402_1%
2
1
BATT+ <45,47>
PL2
SMB3025500YA_2P
1
2
CONN@ PJP2
SUYIN_200275GR008G13GZR
BATT_S1
1 1
2 2
PI
3 3
TH
4 4
EC_SMCA
5 5
EC_SMDA
6
6
7 7
8 8
GND 9
GND 10
+3VLP
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
3
65W@ PR33
3.92K_0402_1%
PR29
21K_0402_1%
PC14
0.1U_0603_25V7K
MAINPWON
D
PQ5B
PU3
VCC TMSNS1
GND RHYST1
~OT1 TMSNS2
~OT2 RHYST2
PR35
9.53K_0402_1%
1
1
9012@ PC17
2
1000P_0402_50V7K
For 65W adapter==>action 70W , Recovery 54W EC
pin
For 90W adapter==>action 97W , Recovery 75W
Issued Date
PH1
100K_0402_1%_NCP15WF104F03RC
2
1
Deciphered Date
1
2
9012@ PR57
9012@PR57
0_0402_5%
<40>
65W@ PR36
10.5K_0402_1%
2012/06/02
Title
SCHEMATIC,MB A7912
Date:
VCIN1_PROCHOT
PR38
10K_0402_1%
Custom
A
VCIN0_PH <40>
Compal Secret Data

2011/06/02
90W@ PR36
16.2K_0402_1%
G718TM1U_SOT23-8
90W@ PR33
8.87K_0402_1%
1
2
9012@PR37
9012@
PR37
0_0402_5%
2N7002KW_SOT323-3
S
@ PR32
100K_0402_1%
<5,40> H_PROCHOT#
PC15
1U_0402_6.3V6K
PR31
100K_0402_1%
PQ7
2
G
PR34
1K_0402_5%
1
2
1
<48> SPOK
PR28
100K_0402_1%
ADP_I <40,47>
1
PC13
0.1U_0603_25V7K
VL
+VSBP
PR27
22K_0402_1%
2
1
PR26
100K_0402_1%
B+
PC12
0.22U_0603_25V7K
PQ6
TP0610K-T1-E3_SOT23-3
Rev
4019ID

D
Sheet
46
of
60
for reverse input protection
PQ8
SI1304BDL-T1-E3_SC70-3
2
G
PR40
3M_0402_5%
PR43
0_0402_5%
PC27
0.01U_0402_50V7K
2
SRN
12
SRN 1
BATDRV
11
2 CSON1
PR55
6.8_0603_5%
BQ24725_BATDRV
PC36
0.01U_0402_50V7K
PC39
2200P_0402_50V7K
PC35
10U_0805_25V6K
2
1
1
2
1
2
PC34
10U_0805_25V6K
2
1
CSON1
PC38
0.1U_0402_25V6
1
2
PC37
0.1U_0402_25V6
CSOP1
PR53
4.7_1206_5%
2
1
PR54
10_0603_5%
2 CSOP1
SRP 1
ILIM
IOUT
SRP
13
14
3
2
1
GND
DL_CHG
2
1
PC41
0.1U_0603_25V7K
15
PC40
680P_0402_50V7K
17
18
16
LODRV
PL4
PR52
10UH_FDVE1040-H-100M=P3_6.5A_20% 0.01_1206_1%
BQ24725_LX
1
2 CHG
1
4
+3VALW
2
PR58
316K_0402_1%
PC42
0.01U_0402_25V7K
1
1
Vin Dectector
PR63
154K_0603_0.1%
L-->H
H-->L
1 2
PR62
2M_0402_1%
PR60
280K_0603_0.1%
1
2
PD9
RB751V-40_SOD323-2
VIN
PR59
2M_0402_1%
PR61
100K_0402_1%
ACDET
BATT+
10
Pre_CHG
<15,40,44,48> ACIN
SCL
ACOK
2
PR56
100K_0402_1%
SDA
ACDRV
ACDET
CMSRC
BQ24725_ACDRV
+3VLP
PQ12
SIS412DN-T1-GE3_POWERPAK8-5
PC33
1
2
BQ24725ARGRR_VQFN20_3P5X3P5
BQ24725_CMSRC
PC24
2200P_0402_50V7K
1
PR48
2.2_0603_5%
1
PR50
2.2_0402_5%
DH_CHG 1
2DH_CHG-1 4
REGN
ACP
PD7
RB751V-40_SOD323-2
BTST
HIDRV
ACN
19
VCC
PAD
PHASE
20
2
1
2
21
PR44
4.12K_0603_1%
1U_0603_25V6K
PU4
1
2
3
PC86
0.1U_0402_25V6
BQ24725_BATDRV 1
PQ13
@ PR51
3.3_1210_5%
BQ24725_BST 2
1U_0603_25V6K
DH_CHG
PC31
1
2
@ PC32
2.2U_0805_25V6K
PC87
0.1U_0402_25V6
PC29
0.047U_0402_25V7K
1
2
PR47
10_1206_1%
1
BQ24725_ACP
1
2
1 2
BQ24725_ACN
@ PR49
3.3_1210_5%
PC30
0.1U_0603_25V7K
PD6
BAS40CW_SOT323-3
BQ24725_LX
PR46
4.12K_0603_1%
PR45
4.12K_0603_1%
2
1
VIN
PC26
0.1U_0402_25V6
1
2
8
7
6
5
3
2
1
PC23
0.1U_0402_25V6
2
1
PQ11
AO4466L_SO8
PC22
10U_0805_25V6K
2
1
VIN
1
2
8
7
6
5
CHG_B+
PL3
1.2UH_PNS40201R2YAF_3A_30%
1
2
1
2
3
PC16
0.1U_0402_25V6
PR42
0_0402_5%
1
2
3
PC25
2200P_0402_50V7K
2
1
8
7
6
5
B+
PR41
0.02_2512_1%
PC21
10U_0805_25V6K
2
1
P2
PQ10
AO4466L_SO8
P1
PQ9
AO4466L_SO8
VIN
PR39
1M_0402_5%
PC28
0.1U_0402_25V6
1
1
ILIM and external DPM
EC_SMB_DA1 <40,46>
Min.
3.906A
Close EC
@ PC45
0.1U_0402_16V7K
Compal Secret Data
Issued Date
Typ
Max.
4.006A 4.108A
ADP_I <40,46>
PC44
100P_0402_50V8J
Max.
18.275V
17.898V
PR66
0_0402_5%
1
2
Typ
18.063V
17.687V
EC_SMB_CK1 <40,46>
PR65
66.5K_0603_0.1%
PC43
0.1U_0402_16V7K
PQ15
2N7002KW_SOT323-3
2
G
PQ14
PDTC115EUA_SC70-3
7,40,44,49,50> SUSP#
PR64
100K_0402_1%
1
2
<40> FSTCHG
ACDET
Min.
17.852V
17.476V
2011/06/02
Deciphered Date
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

D
47
of
60
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
PC46
1U_0603_10V6K
2VREF_8205
VS
VL
VS
2
G
LG_5V
5
3
2
1
PC65
4.7U_0805_10V6K
1
2
PR78
150K_0402_1%
2
1
RT8205_B+
Typ: 175mA
PR76
4.7_1206_5%
2
1
3
2
1
PQ19
SI7716ADN-T1-GE3_POWERPAK8-5
+5VALWP
1
PC62
330U_6.3V_M
PC63
680P_0402_50V7K
NC
5
4
18
VIN
GND
VREG5
17
13
RT8205LZQW(2) WQFN 24P PWM
VL
1
1
PC57
0.1U_0603_25V7K
2
1
19
PL7
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1
2
+
2
RT8205
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)
TPS51125A
TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
(2)SMPS2=305KHZ(+3VALWP)
3.3VALWP Delta I = 1.5836A (Freq=305KHz)
Iocp = 7.4965A ~ 10.349A
5VALWP Delta I = 2.6342A (Freq=245KHz)
Iocp = 7.4965A ~ 10.349A
+3.3VALWP Ipeak=7A ; Imax=4.9A

Delta I=1.5836A=>1/2Delta I=0.7918A (F=375K Hz)
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A
Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A
Iocp=Ilimit+1/2Delta I=7.4965A~10.349A
+5VALWP Ipeak=7A ; Imax=4.9A

Delta I=2.6342A=>1/2Delta I=1.3171A (F=300K Hz)
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A
Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A
Iocp=Ilimit+1/2Delta I=7.4965A ~ 10.349A
930@ PQ23B
5
G
930@ PQ22
S 930@ PQ23A
PDTC115EUA_SC70-3DMN66D0LDW-7_SOT363-6
4
PC67
1U_0603_10V6K
930@ PR84
1M_0402_1%
1
2
930@ PR83
316K_0402_1%
1
2
PC53
2200P_0402_50V7K
2
1
ENTRIP1
LGATE1
PQ20B
PQ21
PDTC115EUA_SC70-3
ACIN
VIN
930@ PR81
1M_0402_1%
1
2
3 2
1
930@ PR85
10K_0402_1%
2
1
930@ PR82
402K_0402_1%
930@ PD11
LL4148_LL34-2
2
1
LGATE2
SPOK <46>
PR79
100K_0402_1%
2
1
PR80
0_0402_5%
1
2
<40,46> MAINPWON
PQ17
<40,41> EC_ON
9012@ PR100
9012@PR100
2.2K_0402_5%
1
2
LX_5V
2VREF_8205
5
G
VL
FB1
UG_5V
20
2
1
PC66
0.1U_0603_25V7K
ENTRIP2
ENTRIP1
21
PHASE1
PR77
499K_0402_1%
1
2
GLZ5.1B_LL34-2
REF
UGATE1
PHASE2
VFB=2.0V
PQ20A
UGATE2
EN
1
B+
ENTRIP1
PR74
PC59
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2
PC64
1U_0603_10V6K
2
1
PD10
TONSEL
22
1
2
3
6
ENTRIP2
23
BOOT1
16
12
PGOOD
BOOT2
15
LG_3V
VREG3
SKIPSEL
PR75
4.7_1206_5%
2
1
PC54
4.7U_0805_10V6K
8
PR73
1 2
1 BST_3V 9
2.2_0603_5%
UG_3V 10
PC58
0.1U_0603_25V7K
LX_3V
11
2
24
PQ18
PC61
680P_0402_50V7K
2
1
PR72
174K_0402_1%
2
VO1
VO2
1
PC60
220U_6.3V_M
P PAD
RT8205_B+
4
7
PL6
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
2
1
+3VALWP
PU5
25
14
1
2
3
PR71
174K_0402_1%
2
1
PQ16
PC52
2200P_0402_50V7K
2
1
+3VLP
PC51
4.7U_0805_25V6-K
2
1
PC50
4.7U_0805_25V6-K
2
1
PC49
0.1U_0603_25V7K
2
1
PC48
560P_0402_50V7K
2
1
PC47
560P_0402_50V7K
2
1
B+
PR70
20K_0402_1%
1
2
FB2
Typ: 175mA
ENTRIP2
PR69
20K_0402_1%
2
1
RT8205_B+
PL5
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
1
2
PR68
30K_0402_1%
2
1
PC56
4.7U_0805_25V6-K
2
1
PR67
13.7K_0402_1%
1
2
PC55
4.7U_0805_25V6-K
2
1
Compal Secret Data
2011/06/02
Issued Date
Deciphered Date
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet
1
48
of
60
+VTT_REFP
VTTSNS
GND
VTTREF
RT8207MZQW_WQFN20_3X3
PGND
14
CS
13
VDDP
12
VDD
11
LG_1.5V
PR88
9.1K_0402_1%
2
1
1
2
PL9
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
1
+1.5VP
DCR: 0.82m5%
@ PR87
@PR87
4.7_1206_5%
2
1
+
PC74
330U_6.3V_M
LX_1.5V
UG_1.5V
16
17
PHASE
BOOT
UGATE
19
18
LGATE
15
B+
PC70
560P_0402_50V7K
Rds=2.7m(Typ)
3.3m(Max)
@ PC75
@PC75
680P_0402_50V7K
VTTGND
PR86
PC71
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.5V-1
1
2
3
2
1
PAD
VLDOIN
20
PU6
21
VTT
Output Cap PAD
PC73
10U_0805_25V6K
+0.75VSP
PC72
10U_0805_25V6K
BST_1.5V
3
2
1
PJ13
JUMP_43X79
PQ24
MDU1516URH_POWERDFN56-8-5
PL8
2
1
PQ25
MDU1511RH_POWERDFN56-8-5
+1.5VP
1.5V_B+
PC69
4.7U_0805_25V6-K
PC68
4.7U_0805_25V6-K
+5VALW
1
2
2
1
PR90
10K_0402_5%
PC77
1U_0603_10V6K
2
1
PGOOD
10
1
PR89
5.1_0603_5%
PC78
1U_0603_10V6K
PGOOD_1.5V
@ PR94
5.9K_0402_1%
2
1
PQ27
2N7002KW_SOT323-3
@ PC79
0.1U_0402_16V7K
PC325
0.1U_0402_16V7K
+3VALW
PR93
887K_0402_1%
2
1 1.5V_B+
2
G
<44> SUSP
<40,44> SYSON
TON
S5
8
PR92
0_0402_5%
1
2
S5_1.5V
<37,40,44,47,50> SUSP#
S3_1.5V
PR91
267K_0402_1%
1
2
S3
VDDQ
FB
PC76
0.033U_0402_16V7K
+1.5VP
FB=0.75V
To GND = 1.5V
To VDD = 1.8V
PR95
5.76K_0402_1%
STATE
S3
S5
1.5VP
VTT_REFP
FB=0.6V
0.75VSP
Note:Iload(max)=3.5A
1
2
PC83
22U_0805_6.3VAM
1
2
PC82
22U_0805_6.3VAM
FB_1.8V
PC81
68P_0402_50V8J
2
1
1
PR97
20K_0402_1%
2
1
2
PR96
4.7_1206_5%
+1.8VSP
PR99
10K_0402_1%
2
2
2
FB
1
PR98
1M_0402_5%
EN
PG
PR257
100K_0402_1%
+1.8VSP_ON
1
2
Note: S3 - sleep ; S5 - power off
SVIN
SUSP#
LX
PL10
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
PC85
680P_0402_50V7K
Off
Off
Off
(Discharge) (Discharge) (Discharge)
LX
LX_1.8V
NC
Lo
PVIN
Lo
PC90
47P_0402_50V8J
S4/S5
PC80
22U_0805_6.3VAM
NC
On
TP
On
Hi
11
Lo
+3VALW
S3
On
Off
(Hi-Z)
On
PC84
0.1U_0402_16V7K
On
Hi
Hi
PU7
SY8033BDBC_DFN10_3X3
10 PVIN
S0
@ PJ14
@PJ14
JUMP_43X79
1 1
2 2
Notice: Internal resistance about 500K on 2nd EN pin
Issued Date
Compal Secret Data
2011/06/02
Deciphered Date
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID

D
Sheet
49
of
60
SW_+1.05VS_VTTP
VFB
V5IN
+1.05VS_VTTP_5V
TST
DRVL
LG_+1.05VS_VTTP
FB_+1.05VS_VTTP 4
+5VALW
3
2
1
PQ30
PC98
4.7U_0805_25V6-K
2
1
2
1
Rds=2.7m(Typ)
3.3m(Max)
@ PR115
4.7_1206_5%
TPS51212DSCR_SON10_3X3
PC101
1U_0603_10V6K
@ PC104
680P_0402_50V7K
2
PC103
0.1U_0402_16V7K
PC102
330U_6.3V_M
PR276
0_0402_5%
1
2
VSSIO_SENSE <8>
PR114
470K_0402_1%
11
3
2
1
TP
+1.05VS_VCCPP
1
PL14
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1
2
UG_+1.05VS_VTTP
EN
PC99
0.1U_0603_25V7K
1
2
SW
TRIP
EN_+1.05VS_VTTP 3
PR111
2.2_0603_5%
1
2
DRVH
TRIP_+1.05VS_VTTP2
RF_+1.05VS_VTTP
PC100
0.1U_0402_16V7K
BST_+1.05VS_VTTP
VBST
PR113
330K_0402_1%
1
2
1
<37,40,44,47,49> SUSP#
10
PGOOD
B+
PU9
1
PC97
4.7U_0805_25V6-K
2
1
PC96
2200P_0402_50V7K
2
1
2
1
@ PR274
0_0402_5%
PR112
38.3K_0402_1%
2
1
PL13
FBMA-L11-322513-151LMA50T_1210
2
1
+1.05VS_VTTP_B+
PC95
0.1U_0402_25V6
2
1
<51> VCCPPWRGOOD
Cesr= 15m ohm

Ipeak= 15.37A Imax= 10.759A
Delta I= 3.4368A ==>1/2 Delta I= 1.7184A
Vtrip=Rtrip*10uA= 0.255V
Iocp= 19.108A~29.416A
PQ29
MDV1525URH_PDFN33-8-5
1
PR261
10K_0402_1%
VFB= 0.704V
Vo=VFB*(1+PR116/PR119)= 1.05V
Freq= 266~314KHz , 290KHz(typ)
+3VS
PR101
0_0402_5%
2
1
PR116
4.99K_0402_1%
2
1
VFB=0.7V
PC105
1000P_0402_50V7K
2
1
PR117
1.2K_0402_1%
2
1
PR118
100_0402_1%
1
2
VCCIO_SENSE
<8>
PR119
10K_0402_1%
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
50
of
60
GPU@ PC328
1U_0402_6.3V6K
+3VS
PR120
100K_0402_5%
1
13
SW
11
SW
10
SW
SW
SW
TP
25
PR125
PC108
0_0603_5%
0.22U_0603_16V7K
2+VCCSA_BT_1 1
2
PL15
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
+VCCSA_PHASE
23
VIN
24
VIN
MODE
VOUT
COMP
3
VREF
2
GND
PAD-OPEN 43X118
@ PC109
680P_0402_50V7K
GNDA_VCCSA
@ PR127
33K_0402_5%
+VCCSA_PWR_SRC
@PR126
@PR126
4.7_1206_5%
2
TPS51461RGER_QFN24_4X4
+VCCSAP
PC121
10U_0805_25V6K
1
2
+VCCSA_PWR_SRC
VIN
SLEW
PGND
22
21
+3VALW
PC120
10U_0805_25V6K
1
2
PJ15
PC119
0.1U_0603_25V7K
1
2
PC118
2200P_0402_50V7K
12
PC117
22U_0805_6.3V6M
1
2
EN
BST
PC116
22U_0805_6.3V6M
1
2
PGND
<50>
PC115
2200P_0402_50V7K
2
1
20
VCCPPWRGOOD
PC114
22U_0805_6.3V6M
1
2
PGND
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A
PC113
22U_0805_6.3V6M
1
2
19
PR124
0_0402_5%
1
2
+VCCSA_EN
VID0
V5DRV
PU10
PGOOD
Ien=10uA, Vth=0.3V, notice

the res. and pull high
voltage from HW
V5FILT
PC107
2.2U_0603_10V7K
1
2
+VCCSA_VID0
+VCCSA_VID1
17
15
18
2
PR123
10_0402_1%
2
1
PC106
1U_0603_10V6K
+5VALW
16
2
G
GPU@ PQ50
2N7002KW_SOT323-3
+VCCSA_PWRGD
<44> VGA_ON#
<40> SA_PGOOD
D
GPU@ PR264
0_0402_1%
1
2
@
PR266
0_0402_1%
1
2
<44> VGA_PWROK#
H_VCCSA_VID0 <9>
PR122
1K_0402_5%
2
1
PC112
.1U_0402_16V7K
2
1
2
1
1
@ PR270
22K_0402_5%
H_VCCSA_VID1 <9>
PC111
22U_0805_6.3V6M
1
2
GPU@ PR260
6.04K_0402_1%
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
output voltage adjustable network
PC110
22U_0805_6.3V6M
1
2
GPU@ PC330
22U_0805_6.3V6M
14
GPU@ PR277
47_0603_5%
PR121
1K_0402_5%
2
1
VID[1]
0
1
0
1
FB=0.8V
GPU@ PC327
1U_0402_6.3V6K
GPU@ PC326
0.022U_0402_25V7K
@ PR258
18K_0402_1%
1
2
<14,17,25,44,53> VGA_ON
+1.05VS_DGPUP
GPU@ PR259
1.91K_0402_1%
FB
3
4
+VCCSA_PWRGD
GPU@ PR263
18K_0402_1%
1
2
<44,53> VGA_PWROK
VOUT
VOUT
EN
POK
8
7
GPU@ PC329
4.7U_0603_6.3V6K
VCNTL
VIN
VIN
GND
GPU@ PU16
APL5930KAI-TRG_SO8
6
5
9
VID1
+1.5VSDGPU
VID [0]
0
0
1
1
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
+3VALW
PR128
100_0402_5%
2
1
PC122
1
0.22U_0402_10V6K
1
PC123
3300P_0402_50V7K
1.5VSDGPU_EN
1
GPU@ PC324
0.1U_0402_16V7K
GPU@ PC316
10U_0805_25V6K
2
1
VBST
10
BST_1.5VSDGPU
TRIP
DRVH
DH_1.5VSDGPU
EN
SW
LX_1.5VSDGPU
GPU@ PR251
2.2_0603_5%
1
2
GPU@ PC317
0.1U_0603_25V7K
1
2
3
2
1
PGOOD
GPU@ PL27
1.2UH_1164AY-1R2N=P3_9.8A_30%
1
2
+5VALW
VFB
V5IN
TST
DRVL
DL_1.5VSDGPU
GPU@ PQ45
4
@ PC319
680P_0402_50V7K
GPU@ PC320
330U_6.3V_M
Cesr= 15m ohm

Ipeak= 10.40A Imax= 7.28A
Delta I= 4.002A ==>1/2 Delta I= 2.001A
Vtrip=Rtrip*10uA= 1.13V
Iocp= 12.464A~14.167A
3
2
1
Rds=13.5m(Typ)
16.5m(Max)
GPU@ PR248
2K_0402_1%
2
1
VFB=0.7V
VFB= 0.704V
Vo=VFB*(1+PR248/PR255)= 1.5V
Freq= 266~314KHz , 290KHz(typ)
GPU@ PC323
4.7U_0805_10V6K
+1.5VSDGPUP
@ PR247
4.7_1206_5%
1 2
11
TPS51212DSCR_SON10_3X3
GPU@ PR250
470K_0402_1%
TP
@ PR256
10K_0402_5%
GNDA_VCCSA
@
PR246
47K_0402_1%
1
2
+VCCSA_SENSE <9>
PAD-OPEN1x1m
VGA_ON
<14,17,25,44,53>
GPU@ PU15
GPU@ PR253
137K_0402_1%
2
1
GPU@ PQ46
GPU@ PR265
0_0402_5%
1
2
<44,53> VGA_PWROK
1.5VSDGPU_B+
GPU@ PC318
10U_0805_25V6K
2
1
GPU@ PC322
560P_0402_50V7K
2
1
B+
GPU@ PC321
560P_0402_50V7K
2
1
GPU@ PL26
1
2
PR130
0_0402_5%
2
1
PJ16
PR129
10K_0402_5%
PC124
0.01U_0402_25V7K
1
2
2011/06/02
Deciphered Date
2012/06/02
Title
Issued Date
Compal Secret Data
GPU@ PR255
1.74K_0402_1%
Size
C
Date:
SCHEMATIC,MB A7912
Document Number
Rev
4019ID
Sheet

1
51
of
60
PHASE3
GND
TP
LGATE3
BOOT1
PR156
4.7_1206_5%
1
QC@ PR157
10K_0603_1%
ISEN3 1
2
1 2
+5VS
1
PR162
1_0603_5%
VSUM-
PQ35
PC186
0.01UF_0402_25V7K
2
1
PR204
1_0402_5%
ISEN2G 2
1
@PR205
@
PR205
10K_0402_1%
PC172
680P_0402_50V7K
2
1 2
3
2
1
+VGFX_CORE
DCR: 0.82m5%
ISEN21
2
PR181
10K_0603_1%
VSUM+
1
1
PR188
1_0402_5%
2011/06/02
PC179
10U_0805_25V6K
2
1
PC177
10U_0805_25V6K
2
1
PC178
10U_0805_25V6K
2
1
+CPU_CORE
DCR: 0.82m5%
ISEN11
2
PR196
10K_0603_1%
2
1
@ PR197
10K_0402_1%
ISEN2
VSUM+
1
2
1
@ PR262
10K_0402_1%
ISEN3
2
PR198
3.65K_0603_1%
VSUM2
1
PR201
1_0402_5%

2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
3
2
1 ISEN3
@PR254
@
PR254
10K_0402_1%
Date:
2
1ISEN1
@PR182
@
PR182
10K_0402_1%
PL21
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
Compal Secret Data
Issued Date
PQ37
PC176
10U_0805_25V6K
2
1
PC175
2
1
5
2
PC187
0.22U_0603_16V7K
VSUMG-
1
PR179
4.7_1206_5%
PQ36
3
2
1
1
PR180
12
2.61K_0402_1%
1
11K_0402_1%
PC166
0.22U_0603_16V7K
2
PR184
QC@ PC168
0.22U_0603_16V7K
2
1
1
2
PH6
10KB_0402_5%_ERTJ0ER103J
PR194
2.2_0603_5%
BOOT1 2
1 1
DCR: 0.82m5%
1
2
QC@ PR202
10K_0603_1%
VSUMG+ 1
2
PR203
3.65K_0603_1%
1
@ PR200
4.7_1206_5%
PC190
680P_0402_50V7K
2
1 2
3
2
1
PQ40
5
BOOT1G
LGATE1G
PR206
2.2_0603_5%
UGATE1-1 4
LGATE1
3
2
1
2
1 1
PR192
0_0402_5%
1
2
PHASE1
For DC 35W 2+1

CPU_CORE LL= -1.9m, OCP ~70A
GFX_CORE LL= -3.9m, OCP ~40A
CPU_B+
For 45W 3+2

CPU_CORE LL= -1.9m, OCP ~116A
GFX_CORE LL= -3.9m, OCP ~55A
+CPU_CORE
PR185
3.65K_0603_1%
VSUM2
PC188
680P_0402_50V7K
2
1 2
1
PR195
4.7_1206_5%
PL22
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
PC189
0.22U_0603_16V7K
VSUM-
PQ39
<8> VSSSENSE
PHASE1G
DC@ PC168
0.1U_0603_25V7K
PC157
3
2
1
<8> VCCSENSE
2
1
@ PR193
10_0402_1%
PQ38
LGATE2
@ PC180
330P_0402_50V7K
2
1
PC164
0.22U_0603_16V7K
4
UGATE1
2
1
@ PR191
10_0402_1%
ISEN1G
CPU_B+
5
UGATE1G
DC@ PC170
33P_0402_50V8J
PC185
330P_0402_50V7K
2
1
+CPU_CORE
PR178
2.2_0603_5%
BOOT2 2
1 1
PL20
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
Close Phase 1 choke
DC@ PR187
390_0402_1%
PC184
10U_0805_25V6K
2
1
PC183
10U_0805_25V6K
2
1
PC182
10U_0805_25V6K
2
1
PC181
10U_0805_25V6K
2
1
DC@ PR189
2.15K_0402_1%
PC174
150P_0402_50V8J
2
1
2
1
PR190
267K_0402_1%
2
1ISEN2
@PR163
@
PR163
10K_0402_1%
220U_25V_M
UGATE2-1 4
PC161
10U_0805_25V6K
2
1
UGATE2
PR175
0_0402_5%
1
2
.1U_0402_16V7K
QC@ PR189
3.65K_0402_1%
2
1
1
2
PC165
0.22U_0402_6.3V6K
1
2
PC171
0.22U_0402_6.3V6K
1
2
QC@ PC173
0.22U_0402_6.3V6K
DC@ PR177
20.5K_0402_1%
DCR: 0.82m5%
2
1ISEN1
@PR154
@
PR154
10K_0402_1%
QC@ PR167
1_0402_5%
2
1
PC160
10U_0805_25V6K
2
1
+3VS
@ PC169
0.068U_0402_16V7K
2
1
QC@ PC170
47P_0402_50V8J
2
1
QC@ PR187
475_0402_1%
PC167
470P_0402_50V7K
2
1
2
1
PR183
499_0402_1%
DC@ PC163
10P_0402_50V8J
2
1
QC@ PR166
3.65K_0603_1%
VSUM+ 1
2
PC159
10U_0805_25V6K
2
1
5
VGATE <15,40>
ISEN3
ISEN2
ISEN1
QC@ PR177
5.76K_0402_1%
2
1
CPU_B+
VSUM+
PR176
2K_0402_1%
2
1
QC@ PL19
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
PHASE2
PC162
560P_0402_50V7K
2
1
PC131
10U_0805_25V6K
2
1
@
+CPU_CORE
ISL95836HRTZ-T_TQFN40_5X5~D
1.91K_0402_1%
1
PC153
680P_0402_50V7K
UGATE1
5
DC@ PR159
0_0603_5%
2
1
PC154
1U_0603_10V6K
2
1
LGATE1
LGATE
3
2
1
BOOT3
PWM PHASE
3
2
1
ISL6208BCRZ-T_QFN8_2X2
LGATE2
PHASE1
UGATE
FCCM BOOT
VCC
CPU_B+
QC@ PR146
1_0402_5%
2
1 VSUMG-
PR148
VSUMG+
10K_0402_1%
1
2 ISEN1G
ISEN2G
PL18
2
1
B+
QC@ PQ34
PHASE2
QC@ PU12
30
29
28
27
26
25
24
23
22
21
QC@ PR150
2.2_0603_5%
2
1
LGATE
PC150
680P_0402_50V7K
2
1
GND
TP
DCR: 0.82m5%
PC149
680P_0402_50V7K
2
1
QC@ PC147
PC142
PR140
10U_0805_25V6K
680P_0402_50V7K 4.7_1206_5%
2
1
2
1 2
1
PC148
10U_0805_25V6K
2
1
QC@
PR144
2
1
10K_0603_1%
2
1
QC@ PR145
3.65K_0603_1%
PWM PHASE
+VGFX_CORE
QC@ PC146
10U_0805_25V6K
2
1
BOOT2G
2
1
2
QC@ PR138
2.2_0603_5%
QC@ PC136
0.22U_0603_16V7K
LGATE2G
4
QC@ PQ33
QC@ PQ32
MDV1525URH_PDFN33-8-5 MDU1511RH_POWERDFN56-8-5
PC145
10U_0805_25V6K
2
1
3
2
1
UGATE2
QC@ PC130
10U_0805_25V6K
2
1
PC129
10U_0805_25V6K
2
1
QC@ PL17
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
FCCM BOOT
QC@ PR151
0_0402_5%
UGATE31
2UGATE3-1
4
9
3
2
1
QC@ PC132
1U_0603_10V6K
2
1
QC@ PR133
0_0603_5%
QC@ PC144
0.22U_0603_16V7K
40
39
38
37
36
35
34
33
32
31
BOOT2
PR174
2
PHASE2G
PC155
1U_0603_10V6K
PWMG2 PR147
ISL6208BCRZ-T_QFN8_2X2
BOOT1G
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
UGATE
4
9
UGATE1G
ISEN3/FB2
ISEN2
ISEN1
ISUMP
ISUMN
RTN
FB
COMP
PGOOD
BOOT1
VCC
PC158
10U_0805_25V6K
2
1
@ PC126
0.1U_0402_16V7K
TP
+5VS
PHASE1G
BOOT2
UGATE2
PHASE2
LGATE2
VCCP
VDD
PWM3
LGATE1
PHASE1
UGATE1
QC@ PQ31
3
2
1
+1.05VS_VTT
41
ISUMPG
ISEN1G
ISEN2G
NTCG
SCLK
ALERT#
SDA
VR_HOT#
VR_ON
NTC
UGATE2G
DC@ PR137
2.55K_0402_1%
LGATE1G
11
12
13
14
15
16
17
18
19
20
PH5
470K_0402_5%_ TSM0B474J4702RE
2
1
2
1
2
PR168
0_0402_5%
1
2
PR169
130_0402_1%
1
2
PR170
75_0402_5%
1
2
PR171
54.9_0402_1%
1
470K_0402_5%_
TSM0B474J4702RE
1
2
1
2 PR160 0_0402_5%
PR161 0_0402_5%
1
2
PR164 0_0402_5%
1
2
PR165 0_0402_5%
@ PC156
47P_0402_50V8J
1
2
3
4
5
6
7
8
9
10
ISEN1G
ISEN2G
NTCG
SCLK
ALERT#
SDA
PR172
27.4K_0402_1%
+5VS
PH4
QC@ PC152
0.22U_0603_10V7K
2
1
DC@ PR155
0_0402_5%
1
2
PU13
PR173
3.83K_0402_1%
PR158
3.83K_0402_1%
1
2
<8> VR_SVID_CLK
<8> VR_SVID_ALRT#
<8> VR_SVID_DAT
<40> VR_HOT#
<40> VR_ON
QC@ PC151
0.22U_0603_10V7K
2
1
DC@ PC140
0.1U_0603_25V7K
PR152
27.4K_0402_1%
2
1
PC138
330P_0402_50V7K
QC@ PC143
1U_0603_10V6K
DC@ PR143
154K_0402_1%
VSUMG+
PWMG2
2
1
1.91K_0402_1%
+3VS
CPU_B+
QC@ PU11
2
1
QC@ PR137
3.65K_0402_1%
1 2
PC141
0.1U_0603_25V7K
1
2
QC@ PC140
0.22U_0603_16V7K
1
2
2
1
@ PC139
0.022U_0402_16V7K
1
2
2
1
QC@ PR143
169K_0402_1%
2
2 1
PR142
11K_0402_1%
PR141
2.61K_0402_1%
.1U_0402_16V7K
PC137
PH3
10KB_0402_5%_ERTJ0ER103J
PC135
150P_0402_50V8J
1
2
1
PR136
267K_0402_1%
PR139
2K_0402_1%
2
1
QC@ PR135
316_0402_1%
2
1
QC@ PR149
0_0603_5%
DC@ PR135
357_0402_1%
VSUMG-
PC134
470P_0402_50V7K
2
1
2
1
PR134
499_0402_1%
QC@ PC133
47P_0402_50V8J
2
1
PC127
0.01UF_0402_25V7K
1
@ PR132
10_0402_1%
2
QC@ PR153
0_0603_5%
10_0402_1%
+5VS
DC@ PC133
33P_0402_50V8J
@ PC125
1000P_0402_50V7K
2 2
@ PR131
<9> VCC_AXG_SENSE
<9> VSS_AXG_SENSE
QC@ PC128
10U_0805_25V6K
2
1
+VGFX_CORE
Rev
4019ID
Sheet
1
52
of
60
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
BOOT2_VGA
2S@ PC195
0.22U_0603_10V7K
BOOT2_2_VGA 1
2
UGATE2_VGA
2S@
F
+3VS
3
2
1
GPU_VID6
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
@ PD12
RB751V-40TE17_SOD323-2
2
1
PR219
100K_0402_5%
2
2S@ PR211
10K_0402_5%
2S@ PR214
3.65K_0402_1%
2
1
@ PR213
2.2_1206_5%
B+
2S@
PL24
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
+VGA_CORE
V2N_VGA
DCR: 0.82m5%
2S@ PR215
1_0402_5%
2S@ PR217
10K_0402_5%
1
2V1N_VGA
VSUM+_VGA
LGATE2_VGA
GPU@ PR216
1.91K_0402_1%
51> VGA_PWROK
VSUM-_VGA
ISEN2_VGA
@ PC198
680P_0402_50V7K
CLK_ENABLE#_VGA
2S@ PQ42
5
@
PR212
1.91K_0402_1%
1
2
GPU@ PR218
0_0402_5%
1
2
GPU@ PL23
FBMA-L11-322513-151LMA50T_1210
2
1
PHASE2_VGA
+3VS
+VGA_B+
3
2
1
GPU@ PC331
0.1U_0402_16V7K
2S@ PR208
2.2_0603_5%
2
1
VID0
0.9V
VID1
2S@ PC194
10U_0805_25V6K
2
1
N13P GV
VID2
GPU@ PR210
10K_0402_1%
1
2
0.9V
VID3
GPU@ PR209
68K_0402_1%
1
2
VGA_ON
N13P GL
VID4
GPU@ PR207
0_0402_5%
<14,17,25,44,51>
<22>
<22>
<22>
<22>
<22>
<22>
@
PR278
0_0402_5%
1
2
+3VSDGPU
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
N12P GV4 0.9V
VID5
2S@ PC193
10U_0805_25V6K
N12P GS4 0.975V

H
VID6
Default
Voltage
2S@ PC192
2200P_0402_50V7K
2
1
VGA Chipset
PC191
0.1U_0603_25V7K
2
1
2S@ PQ41
GPU@ PR220
47K_0402_1%
2
1
+3VS
GPU@ PR222
1
0_0402_5%
2
+5VS
E
GPU@ PR221
0_0402_5%
GPU@ PC201
1U_0603_10V6K
+VGA_B+
3
2
1
Layout Note:
Place near Phase1 Choke
GPU@ PC213
10U_0805_25V6K
2
1
GPU@ PC212
10U_0805_25V6K
VSUM+_VGA
@ PC223
680P_0402_50V7K
+VGA_CORE
GPU@ PC91
56P_0402_50V8
2
1
GPU@ PC89
56P_0402_50V8
2
1
GPU@ PC88
56P_0402_50V8
2
1
2S@ PR242
10K_0402_5%
1
2V2N_VGA
1
2
GPU@ PR238
3.65K_0402_1%
2
1
@ PR237
2.2_1206_5%
5
4
3 V1N_VGA
DCR: 0.82m5%
GPU@ PR240
1_0402_5%
GPU@ PR234
2.61K_0402_1%
2
1
LGATE1_VGA
2S@ PR245
953_0402_1%
1
2
GPU@ PL25
0.36UH_PDME104T-R36MS0R825_37A_20%
1
4
PHASE1_VGA
GPU@ PR241
11K_0402_1%
2
1
GPU@ PC218
0.1U_0603_25V7K
2
1
2
1
2
VSUM-_VGA
ISEN1_VGA
VSUM-_VGA
GPU@ PC224
0.1U_0402_16V7K
GPU@ PR244
10_0402_5%
1
2
GPU@ PC214
0.22U_0603_10V7K
1
2
GPU@ PH7
10K_0402_1%_TSM0A103F34D1RZ
2
2S@ PC217
0.22U_0603_16V7K
2
1
1
1
2
GPU@ PC221
1000P_0402_50V7K
PC216
0.01U_0402_25V7K
<24> VSSSENSE_VGA
GPU@ PR243
0_0402_5%
1
@
2
GPU@ PC215
330P_0402_50V7K
PR233
82.5_0402_5%
GPU@ PR236
0_0402_5%
PC222
330P_0402_50V7K
2
1
<24> VCCSENSE_VGA
GPU@ PR235
2.2_0603_5%
2
1 BOOT1_1_VGA
LL Disable
1 phase OCP ~33A
2 phase OCP ~57A
2S@ PR239
10K_0402_5%
VSUM+_VGA
GPU@ PR232
10_0402_5%
+VGA_CORE
C
PC210
0.1U_0603_25V7K
2
1
UGATE1_VGA
VSUM-_VGA
2
GPU@ PC211
2200P_0402_50V7K
2
1
+5VS
GPU@ PC209
0.22U_0603_25V7K
1
2
GPU@ PC208
1U_0603_10V6K
2
1
+VGA_B+
GPU@ PR230
1_0402_5%
1
2
+5VS
+5VS
BOOT1_VGA
GPU@ PR231
255K_0402_1%
ISEN1_VGA
1
GPU@ PR229
324K_0402_1%
1S@ PR249
0_0402_5%
1
2
ISEN2_VGA
1
2
GPU@ PR226
0_0402_5%
GPU@ PQ43
GPU@ PR228
0_0402_5%
1
2
GPU@ PQ44
GPU@ PC203
470P_0402_50V7K
1S@
PR252
0_0402_5%
2
1
ISL62883CHRTZ-T_TQFN40_5X5
3
2
1
11
12
13
14
15
16
17
18
19
20
GPU@ PR225
499_0402_1%
2 1
GPU@ PC205
150P_0402_50V8J
AGND
1
2
GPU@ PR227
3.57K_0402_1%
41
30
29
28
27
26
25
24
23
22
21
GPU@ PC204
47P_0402_50V8J
1
2
1
2
GPU@ PC202
1000P_0402_50V7K
GPU@ PR224
8.06K_0402_1%
1
2
1S@ PR223
120K_0402_1%
1
2
@ PC200
33P_0402_50V8J
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
@ PR199
3.83K_0402_1%
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
1
2
3
4
5
6
7
8
9
10
2S@ PC207
0.22U_0402_10V4Z
@ PR186
27.4K_0402_1%
2S@ PC206
0.22U_0402_10V4Z
40
39
38
37
36
35
34
33
32
31
@ PR275
10K_0402_5%
@ PH8
470K_0402_5%_ TSM0B474J4702RE
2
1
2S@ PC199
1U_0603_10V6K
1
2
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
GPU@ PU14
1
<40> GPU_HOT#
1S@ PR245
590_0402_1%
1S@ PC217
0.1U_0603_25V7K
2011/06/02
Issued Date
Deciphered Date
2012/06/02
Title
Size
C
Date:
Compal Secret Data
SCHEMATIC,MB A7912
Document Number
Rev
4019ID
Sheet
53
1
of
60
PWR Rule
CPU 330uF/9m *5,22uF *16,10uF*10
GFX 470uF/4.5m*1,330uF/9m*1,22uF*12
PC246
22U_0805_6.3V6M
PC245
22U_0805_6.3V6M
PC244
22U_0805_6.3V6M
PC243
22U_0805_6.3V6M
PC242
22U_0805_6.3V6M
PC262
22U_0805_6.3V6M
PC261
22U_0805_6.3V6M
PC260
22U_0805_6.3V6M
PC259
22U_0805_6.3V6M
PC258
330U_D2_2V_Y
PC257
330U_D2_2V_Y
PC241
22U_0805_6.3V6M
PC256
470U_D2_2VM_R4.5M
PC255
330U_D2_2V_Y
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
PC254
22U_0805_6.3V6M
2 @
PC253
22U_0805_6.3V6M
2 @
PC252
22U_0805_6.3V6M
PC240
10U_0805_25V6K
PC251
22U_0805_6.3V6M
+CPU_CORE
PC239
10U_0805_25V6K
PC250
22U_0805_6.3V6M
PC249
22U_0805_6.3V6M
PC248
22U_0805_6.3V6M
PC247
22U_0805_6.3V6M
PC238
10U_0805_25V6K
PC237
10U_0805_25V6K
PC236
10U_0805_25V6K
PC235
22U_0805_6.3V6M
PC234
22U_0805_6.3V6M
PC233
22U_0805_6.3V6M
PC232
22U_0805_6.3V6M
PC231
22U_0805_6.3V6M
PC230
22U_0805_6.3V6M
PC229
10U_0805_25V6K
PC228
10U_0805_25V6K
PC227
10U_0805_25V6K
PC226
10U_0805_25V6K
1
D
PC225
10U_0805_25V6K
+VGFX_CORE
+CPU_CORE
PC270
22U_0805_6.3V6M
PC269
22U_0805_6.3V6M
PC268
22U_0805_6.3V6M
PC267
22U_0805_6.3V6M
PC266
22U_0805_6.3V6M
PC265
22U_0805_6.3V6M
Can connect to GND if motherboard only

supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
PC264
22U_0805_6.3V6M
Vaxg
PC263
22U_0805_6.3V6M
+CPU_CORE
1
+
1
PC271
330U_D2_2V_Y
1
+
PC272
330U_D2_2V_Y
1
+
PC273
330U_D2_2V_Y
1
PC274
330U_D2_2V_Y
+ PC275
470U_D2_2VM_R4.5M
2
1
+
2 @
PC285
22U_0805_6.3V6M
PC284
22U_0805_6.3V6M
PC283
22U_0805_6.3V6M
PC282
22U_0805_6.3V6M
PC280
22U_0805_6.3V6M
PC281
PC291
22U_0805_6.3V6M
330U_D2_2.5VY_R15M
PC279
22U_0805_6.3V6M
PC290
330U_D2_2.5VY_R15M
PC289
22U_0805_6.3V6M
PC278
22U_0805_6.3V6M
PC288
22U_0805_6.3V6M
PC277
22U_0805_6.3V6M
PC286
22U_0805_6.3V6M
PC276
22U_0805_6.3V6M
+1.05VS_VTT
1
1
PC287
22U_0805_6.3V6M
+1.05VS_VTT
INTEL Recommend
3*330uF(1 in other page),12*22uF, 5 no stuff
from PDDG 1.0
2011/06/02
Issued Date
Compal Secret Data
Deciphered Date
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet
54
of
SCHEMATIC,MB A7912
60
2
1
2
1
2
GPU@ PC220
470U_V_2.5VM
1
2
1
@ PC315
22U_0805_6.3V6M
GPU@ PC299
0.1U_0402_16V7K
GPU@ PC307
4.7U_0603_6.3V6K
@ PC314
22U_0805_6.3V6M
GPU@ PC298
0.1U_0402_16V7K
2
1
GPU@ PC306
4.7U_0603_6.3V6K
@ PC313
22U_0805_6.3V6M
GPU@ PC297
0.1U_0402_16V7K
2
1
GPU@ PC305
4.7U_0603_6.3V6K
GPU@ PC312
22U_0805_6.3V6M
GPU@ PC296
0.1U_0402_16V7K
2
1
GPU@ PC304
4.7U_0603_6.3V6K
1
GPU@ PC311
47U_0805_4V6
GPU@ PC295
0.1U_0402_16V7K
2
1
GPU@ PC303
4.7U_0603_6.3V6K
2
GPU@ PC310
470U_V_2.5VM
2
1
GPU@ PC294
0.1U_0402_16V7K
2
1
GPU@ PC302
4.7U_0603_6.3V6K
GPU@ PC293
0.1U_0402_16V7K
2
1
GPU@ PC301
4.7U_0603_6.3V6K
GPU@ PC339
4.7U_0603_6.3V6K
2
1
GPU@ PC338
4.7U_0603_6.3V6K
2
1
+
2
GPU@ PC219
390U_2.5V_M
+VGA_CORE
1
GPU@ PC337
4.7U_0603_6.3V6K
2
1
1
GPU@ PC309
4.7U_0603_6.3V6K
2
2
@ PC197
330U_D2_2V_Y
2
1
1
GPU@ PC336
4.7U_0603_6.3V6K
2
1
GPU@ PC292
0.1U_0402_16V7K
2
1
2
GPU@ PC300
4.7U_0603_6.3V6K
GPU@ PC196
390U_2.5V_M
GPU@ PC308
4.7U_0603_6.3V6K
GPU@ PC335
4.7U_0603_6.3V6K
2
1
5
4
3
Issued Date
2011/06/02
Deciphered Date
2012/06/02
+VGA_CORE
Under GPU
D
Near GPU
B
B
A
A
Compal Secret Data

Title
Size
B
Date:
Document Number
SCHEMATIC,MB A7912
4019ID
Rev
Sheet
1
55
of
60
Version change list (P.I.R. List)

Item
Fixed Issue
Reason for change
S3 sequence @ DC
Meet Intel sequence SPEC
1.5VSDGPU lose
Improve FB pin anit-noise
Cut-in SMT memo
Rev.
PG#
Modify List
Page 1 of 2
for PWR
Change RP91 to 267K
2011
1208
DVT
51
Change RP248 to 2K, PR255 to 1.74K, PR253 to 137K
2011
1208
DVT
52
Add PC182, PC184
2011
1208
DVT
2011
1212
2011
1217
DVT
2011
1221
DVT
Standard design
Change PR138, PR150, PR178, PR194, RP205 , PR235 to 2.2
Vth has risk

Enable select
Phase
49
Date
Cut-in EMI solution
51
Change PU16 from G971 to APL5930
51
Add PR266
53
Add PC88, PC89, PC91
DVT
8
9
10
11
B
12
13
14
15
16
17
A
18
19
2011/06/02
Issued Date
Compal Secret Data
Deciphered Date
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet
1
56
of
60
Version change list (P.I.R. List)

Item
Fixed Issue
Reason for change
Rev.
PG#
Modify List
Page 2 of 2
for PWR
Date
Phase
2
3
4
5
6
C
7
8
9
10
11
B
12
13
14
15
16
A
17
2011/06/02
Issued Date
Compal Secret Data
Deciphered Date
2012/06/02
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet
1
57
of
60
Version Change List ( P. I. R. List )

Item Page#
D
Date
Request
Owner
Page 1
Issue Description
Solution Description
Rev.
P.40.13
9/7
EC
Change th HDA_SDO to ME_EN
P.40
9/7
HW
Add R2085 ,change the EC_ACIN pull high to +3VLP
0.2
P.37
9/7
HW
Add fl1009 USB3.0 TX coupling capacitor (c2060,c2061)
0.2
P.38.39.40
9/7
HW
Add USB chargaer schematic(C2060.C2061.R2077~R2084,R2065~R2072)
0.2
P.22.40
9/7
HW
Follow ABO request,add ADPS function(Q2005),R2086.R2087)
0.2
P.20
9/7
HW
Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2088)
0.2
P.44
9/7
HW
Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004)
0.2
P.43
9/7
HW
For FSOV spec,Chang R714,R716 from 75ohm to 47ohm.
0.2
P.13
9/7
HW
For WIN8,Change R681.R651.R684.R652 to 33ohm
0.2
10
P.44
9/7
HW
Delete C817,Change C826 from D2 size to B2 size
0.2
11
P.17.37
9/7
HW
Follow chief river common design, please chang Mini-Card 2(port 11) to port 9
0.2
12
P.38
9/7
HW
Delete +1.5V to +1.05V_V128 Transfer(U2002.R2002.R2003.R2005.C2002.C2003.C2005.R2008)

0.2
13
P.38
9/7
HW
Delete USB3.0 EEPROM(U2004.R2035.R2034.C2039)
0.2
14
P.37
9/7
HW
Reserve Mini-Card 2
0.2
15
P.19
9/7
HW
16
P.22.40
9/8
HW
17
P41
9/14
HW
18
19
Title
P27.30
P06.11.17.35.
P39.40.42
9/14
HW
9/14
HW
20
P16
9/16
HW
21
P31
9/16
HW
0.2
Add SW5.SW6 for EG project.
0.2
Swap MDC37 and MDC38

Swap MDA13 and MDA14
For ESD request
Add C2065~C2075
For HDMI PCH_DPB_HPD noise
Add C2076
For LVDS power sequence
Change R5 from 300 to 200 ohm
Change R2 from 1k to 10k ohm
change C2 from 0.047uF to 1uF
0.2
0.2
0.2
9/16
HW
Delete PCH test ponit(T31~T46,T49~T61,T63~T65)
0.2
23
P21,40
9/19
HW
Change Q22,Q26 from SB000008J10 to SB000009080
0.2
P14,22,35,38
9/19
HW
For Crystal
Change Y2 ,Y4 from SJ10000DJ00 to SJ10000E800
Change Y1000 from SJ10000DK00 to SJ100009700
Change C630,C631,C2019,C2028,C1008,C1009 to 10pF
Change C681,C679 to 15pF
Issued Date
0.2
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Compal Secret Data
0.2
P18
F2 flick issue on projector P5202 D-sub

0.2
Add C2063.C2064
Change VGA GPIO12 of dGPU connection to EC controlled for the power limited usage
0.2
Add EC pin 107-->GPU_ACIN
22
24
Rev
4019ID
Sheet

1
58
of
60

Item Page#
D
Title
Date
Request
Owner
Page 2
Issue Description
Rev.
25
P.44
9/20
EMI
For EMI request (Add C2079~C2084)
26
P.36
9/20
HW
For SD3.0 issue (Add R2088.R2089)
0.2
27
P.20
10/17
HW
Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2090)
0.3
28
P.44
10/17
HW
Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004)
0.3
29
P.40
10/17
HW
30
P.40
10/17
HW
31
P.17,39
10/17
HW
32
P.18
10/18
HW
Board ID error.
Add R353.
Board ID 0.3.
Change R353 to 18K
Follow Intels suggestion;
Change USB3.0 from port 2 to port 1
Change USB2.0 from port 0,1 to port 2,9
Support eDP
GPIO71-->0 (eDP)
GPIO71-->1 (LVDS)
Co_lay NPCE885N
Delete U38,C722,R690,R695,C727
Add C2085,R2091~R2096
33
P.13.40
10/25
0.2
HW
0.3
0.3
0.3
0.3
C
0.3
Issued Date
Compal Secret Data
2011/06/02
2012/06/02
Deciphered Date
Title
SCHEMATIC,MB A7912
Custom
Date:
Rev
4019ID
Sheet

1
59
of
60

Item Page#
D
Title
Date
Request
Owner
Page 3
Issue Description
Rev.
Delete SW5,SW6,
Pop SW2,SW3
43
P.41
11/16
ME
44
P.05
11/16
HW
BUF_CPU_RST# noise
Add C2090
45
P.35
11/17
HW
LAN SPROM on Chip
De-pop U31,R537
Pop R538
46
P.36
11/17
EMI
47
P.13
11/17
HW
48
P.31,32,41
11/17
ESD
De-pop D3,D4,D17,D18,D15
Pop D24,D36
0.4
49
P.40
11/17
HW
De-pop R891,R893
0.4
50
P.24
11/21
HW
N13P_GS
Change strap2 to PD 15k
Change strap4 to PD 10k
0.4
51
P.13
11/21
HW
Chip Select
Change R651,R2049 to 0ohm
0.4
52
P.13,40
11/21
HW
Delete NPCE885N
(R2091.R2092.R2094.R2095.R2096,R698,
R699,R692,C2085)
0.4
53
P.45
11/22
HW
Change +1.05VSDGPU JUMP size

PJ19 change to 43x118
0.4
55
P.35,36
11/23
HW
0.4
56
P.13
11/23
HW
Card Reader
Change R216 to 22 ohm
Change R2088 to 47ohm
Change R2089 to 22 ohm
Add C2091~C2093
Change R525,R536,R537,R538 to 1k
Delete R2093,R2049,R651(0ohm)
57
P.13
11/23
HW
Change N13P-GS to SA000051880

Change U33 to SA00005AG00
0.4
58
P.35, P36
11/23
HW
0.4
59
P.36
11/24
HW
Del C2093, R222, R2089,

net(CR_CLK_XD_RY_BY#_23)
Add R2101, C2094
ADD R2102, C2096 for EMI ISSUE
0.4
0.4
0.4
Change C478 to 10P_50V
0.4
Change C682,C686 to 15P
RTC issue
Issued Date
0.4
2011/06/02
2012/06/02
Deciphered Date
0.4
Title
SCHEMATIC,MB A7912
Date:
0.4
Custom
5
Compal Secret Data
Rev
4019ID
Sheet

1
60
of
60
www.s-manuals.com

Compal La-7912p r0.2 Schematics

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Compal La-7912p r0.2 Schematics

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A

Model Name :Q5WV1/Q5WS1

Q5WV1 M/B Schematics Document

PCB 0N4 LA-7912P REV0 M/B

Compal Electronics, Inc.

Compal Secret Data

Friday, January 06, 2012

PCI-E 2.0x16 5GT/s PER LANE

USB 2.0 conn x2

USB port 0,1 on

USB 3.0 conn x1

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

USB port 8 page 34

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

Power On/Off CKT.

DC/DC Interface CKT.

Compal Electronics, Inc.

Compal Secret Data

Friday, January 06, 2012

Adapter power supply (19V)

Battery power supply (12.6V)

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for GPU

Core voltage for UMA graphic

+0.75VP to +0.75VS switched power rail for DDR terminator

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

+1.05VS_VCCP to +1.05VS_PCH power for PCH

+1.5VP to +1.5V power rail for DDRIII

+1.5V to +1.5VS switched power rail

+1.5VS to +1.5VSDGPU switched power rail for GPU

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON

+1.8VS to +1.8VSDGPU switched power rail for GPU

+3VALW always on power rail

+3VALW always to KBC

+3VALW to +3V_LAN power rail for LAN

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

+5VALW to +5VS switched power rail

+VSBP to +VSB always on power rail for sequence control

Clock Generator (9LVS3199AKLFT,

PCH SM Bus address

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

USB Port Table

Compal Electronics, Inc.

Mini Card 1(WLAN)

Compal Secret Data

BTO Option Table

BT & USB30 & USB20 Config

Board ID / SKU ID Table for AD channel

Friday, January 06, 2012

PCI EXPRESS* - GRAPHICS

Add eDP circuit

PEG_ICOMPI and PEG_RCOMPO signals should be

eDP_COMPIO and ICOMPO signals should

Typ- suggest 220nF. The change in AC capacitor

Compal Electronics, Inc.

Compal Secret Data

Friday, January 06, 2012

If use External Graphic or

DDR3 Compensation Signals