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A B C D E Compal Confidential Model Name :Q5WV1/Q5WS1 Compal Project Name : 1
A
B
C
D
E
Compal Confidential
Model Name :Q5WV1/Q5WS1
Compal Project Name :
1
1
File Name : LA-7912P
Compal Confidential
2
2
Q5WV1 M/B Schematics Document
Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH
Nvidia N13P GS/GL
2011-12-24
3
3
REV:0.2
ZZZ2
ZZZ2
1G@
1G@
ZZZ3
ZZZ3
2G@
2G@
MB PCB
MB PCB
4
4
Part Number
Part Number
Description
Description
DA60000SV00
DA60000SV00
PCB 0N4 LA-7912P REV0 M/B
PCB 0N4 LA-7912P REV0 M/B
X76344BOL01
X76344BOL01
X76344BOL02
X76344BOL02
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
1 1 1
of
of
of
60
A
B
C
D
E
A B C D E Fan Control page 42 1 1 PEG(DIS) 100MHz PCI-E 2.0x16
A
B
C
D
E
Fan Control
page 42
1
1
PEG(DIS)
100MHz
PCI-E 2.0x16
5GT/s PER LANE
Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Nvidia
133MHz
Intel
Sandy/Ivy Bridge
Dual Channel
BANK 0, 1, 2, 3
page 11,12
N13P GS/GL
Processor
1.5V DDRIII 1066/1333
page22~30
eDP
rPGA989
page31
page 4~10
USB 2.0 conn x2
Bluetooth
CMOS Camera
FDI x8
DMI x4
Conn
HDMI Conn.
CRT Conn.
LVDS Conn.
USB port 13
USB port 10
100MHz
100MHz
USB port 0,1 on
USB/B
page 38
page 38
page 31
page 33
page 32
page 31
2.7GT/s
1GB/s x4
USBx14
3.3V 48MHz
2
2
LVDS(UMA/OPTIMUS)
CRT(UMA/OPTIMUS)
Intel
Panther Point-M
HD Audio
3.3V 24MHz
TMDS(UMA/OPTIMUS)
PCH
HDA Codec
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
100MHz
989pin BGA
ALC271X/281X
port 5
port 3
port 1
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
100MHz
page 41
SPI
page 13~21
USB 3.0 conn x1
Fresco FL1009
with USB3.0 Conn.
LAN(GbE) &
port 1
port 0
MINI Card x1
port 2
SATA HDD
Card Reader
WLAN
BCM57785
Conn.
USB port 11
SPI ROM x1
Int. Speaker
Phone Jack x 2
page 37
page 35,36
port 2
page 34
page 45
page 13
page 41
page 41
MSATA(WWAN)
SATA CDROM
Card Reader
RJ45
USB port 8
page 34
Conn.
LPC BUS
3
page 34
3
page 36
Conn. page 35,36
33MHz
ENE KB930/KB9012
page 39
RTC CKT.
page 13
Touch Pad
Int.KBD
page 40
page 40
Power On/Off CKT.
Sub-board
page 40
LS-7911P
USB 2.0/B 2Port
USB Port0,1
BIOS ROM
page 39
page 40
DC/DC Interface CKT.
page 43,44
4
4
LS-7912P
Power Circuit DC/DC
PWR/B
page 41
page 46~59
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
2
2
2
of
of
of
60
A
B
C
D
E
A B C D E Voltage Rails SIGNAL STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V
A
B
C
D
E
Voltage Rails
SIGNAL
STATE
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
Full ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
1 +CPU_CORE
Core voltage for CPU
ON
OFF
OFF
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
1
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.05VSDGPU
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.05VS_VTT
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
OFF
Board ID / SKU ID Table for AD channel
+1.05VS_PCH
+1.05VS_VCCP to +1.05VS_PCH power for PCH
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
Vcc
3.3V +/- 5%
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
Ra/Rc/Re
100K +/- 5%
+1.5VSDGPU
+1.5VS to +1.5VSDGPU switched power rail for GPU
ON
OFF
OFF
Board ID
Rb / Rd / Rf
V
min
AD_BID
V AD_BID typ
V AD_BID max
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
ON
OFF
OFF
0
0
0 V
0 V
0 V
+1.8VSDGPU
+1.8VS to +1.8VSDGPU switched power rail for GPU
ON
OFF
OFF
1
8.2K +/- 5%
0.216
V
0.250
V
0.289
V
+3VALW
+3VALW always on power rail
ON
ON
ON*
2
18K +/- 5%
0.436
V
0.503
V
0.538
V
+3VALW_EC
+3VALW always to KBC
ON
ON
ON*
3
33K +/- 5%
0.712
V
0.819
V
0.875
V
+3V_LAN
+3VALW to +3V_LAN power rail for LAN
ON
ON
ON*
4
56K +/- 5%
1.036
V
1.185
V
1.264
V
+3VALW_PCH
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
ON
ON
ON*
5
100K +/- 5%
1.453
V
1.650
V
1.759
V
2
2 +3VS
+3VALW to +3VS power rail
ON
OFF
OFF
6
200K +/- 5%
1.935
V
2.200
V
2.341
V
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
7
NC
2.500
V
3.300
V
3.300
V
+5VALW_PCH
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
BOARD ID Table
BTO Option Table
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
BTO Item
BOM Structure
+RTCVCC
RTC power
ON
ON
ON
Board ID
PCB Revision
UMA Only
UMAO@
0
Dis with OPTIMUS
DIS@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
1
Blue Tooth
BT@
EC SM Bus1 address
EC SM Bus2 address
2
Internal USB 3.0
PUSB@
3
0.1
eDP
eDP@
Device
Address
Device
Address
4
0.2
VRAM
X76@
Smart Battery
0001 011X b
5
0.3
Connector
CONN@
6
0.4
Unpop
@
PCH SM Bus address
7
N13P-GS
GS@
N13P-GL
GL@
Device
Address
Win8
Win8@
3
3
Clock Generator (9LVS3199AKLFT,
1101 0010b
USB Port Table
Audio ALC271X
271X@
RTM890N-631-VB-GRT)
Audio ALC281X
281X@
DDR DIMM0
1001 000Xb
3 External
USB 2.0
USB 1.1
Port
PCH HM65
HM65@
DDR DIMM2
1001 010Xb
USB Port
PCH HM76
HM76@
0
USB3.0 colay USB2.0 Conn
UHCI0
BT & USB30 & USB20 Config
1
USB/B (Right Side)
OPTMIUS SKU:DIS@
N13P-GL:GL@ N13P-GS:GS@
N13P-GF108_ES4:GF108@
2
USB/B (Right Side)
UHCI1
BT SKU:BT@
internal USB SKU: PUSB@
3
EHCI1
DIS USB30 SKU:DUSB@
4
UHCI2
eDP SKU: EDP@
LVDS SKU: LVDS@
EC 930 SKU: 930@ EC 9012 SKU: 9012@
PCH HM65: HM65@ PCH HM76: HM76@
5
6
UHCI3
7
8
Mini Card 1(WLAN)
UHCI4
Win8: WIN8@
9
10
Camera
EHCI2
UHCI5
11
BlueTooth
4
4
12
UHCI6
13
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
3
3
3
of
of
of
60
A
B
C
D
E
5 4 3 2 1 D +1.05VS_VTT D R517 R517 24.9_0402_1% 24.9_0402_1% PEG_ICOMPI and PEG_RCOMPO
5
4
3
2
1
D
+1.05VS_VTT
D
R517
R517
24.9_0402_1%
24.9_0402_1%
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,
max length = 500 mils,trace width=4mils
PEG_ICOMPO signals should be routed with - max
length = 500 mils,trace width=12mils
JCPU1A
JCPU1A
PEG_COMP
spacing =15mils
J22
PEG_ICOMPI
J21
PEG_ICOMPO
B27
H22
<15> DMI_CRX_PTX_N0
DMI_RX#[0]
PEG_RCOMPO
B25
<15> DMI_CRX_PTX_N1
DMI_RX#[1]
A25
<15> DMI_CRX_PTX_N2
DMI_RX#[2]
PEG_GTX_C_HRX_N15
C46
C46
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N15
B24
K33
2
<15> DMI_CRX_PTX_N3
DMI_RX#[3]
PEG_RX#[0]
PEG_GTX_C_HRX_N14
C49
C49
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N14
M35
2
PEG_RX#[1]
PEG_GTX_C_HRX_N13
B28
L34
C51
C51
1 GSGL@ 0.22U_0402_10V6K
2
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N13
<15> DMI_CRX_PTX_P0
DMI_RX[0]
PEG_RX#[2]
PEG_GTX_C_HRX_N12
C53
C53
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N12
B26
J35
2
<15> DMI_CRX_PTX_P1
DMI_RX[1]
PEG_RX#[3]
PEG_GTX_C_HRX_N11
A24
J32
C60
C60
1 GSGL@ 0.22U_0402_10V6K
2
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N11
<15> DMI_CRX_PTX_P2
DMI_RX[2]
PEG_RX#[4]
PEG_GTX_HRX_N[0
15]
<22>
PEG_GTX_C_HRX_N10
C71
C71
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N10
B23
H34
2
<15> DMI_CRX_PTX_P3
DMI_RX[3]
PEG_RX#[5]
PEG_GTX_HRX_P[0
15]
<22>
PEG_GTX_C_HRX_N9
C75
C75
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N9
H31
2
PEG_RX#[6]
PEG_GTX_C_HRX_N8
G21
G33
C82
C82
1 GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_N8
2
GSGL@ 0.22U_0402_10V6K
<15> DMI_CTX_PRX_N0
DMI_TX#[0]
PEG_RX#[7]
PEG_HTX_C_GRX_N[0
15]
<22>
PEG_GTX_C_HRX_N7
C92
C92
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N7
E22
G30
2
<15> DMI_CTX_PRX_N1
DMI_TX#[1]
PEG_RX#[8]
PEG_HTX_C_GRX_P[0
15]
<22>
PEG_GTX_C_HRX_N6
PEG_GTX_HRX_N6
F21
F35
C93
C93
1 DIS@
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
<15> DMI_CTX_PRX_N2
DMI_TX#[2]
PEG_RX#[9]
PEG_GTX_C_HRX_N5
C102
C102
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N5
D21
E34
2
<15> DMI_CTX_PRX_N3
DMI_TX#[3]
PEG_RX#[10]
PEG_GTX_C_HRX_N4
C111
C111
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N4
E32
2
PEG_RX#[11]
PEG_GTX_C_HRX_N3
PEG_GTX_HRX_N3
G22
D33
C113
C113
1 DIS@
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
<15> DMI_CTX_PRX_P0
DMI_TX[0]
PEG_RX#[12]
PEG_GTX_C_HRX_N2
C125
C125
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N2
D22
D31
2
<15> DMI_CTX_PRX_P1
DMI_TX[1]
PEG_RX#[13]
PEG_GTX_C_HRX_N1
PEG_GTX_HRX_N1
F20
B33
C129
C129
1 DIS@
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
<15> DMI_CTX_PRX_P2
DMI_TX[2]
PEG_RX#[14]
PEG_GTX_C_HRX_N0
C144
C144
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N0
C21
C32
2
<15> DMI_CTX_PRX_P3
DMI_TX[3]
PEG_RX#[15]
PEG_GTX_C_HRX_P15
J33
C47
C47
1 GSGL@ 0.22U_0402_10V6K
2
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_P15
PEG_RX[0]
PEG_GTX_C_HRX_P14
C50
C50
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_P14
L35
2
PEG_RX[1]
C
PEG_GTX_C_HRX_P13
C52
C52
1 GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_P13
C
K34
2
GSGL@ 0.22U_0402_10V6K
PEG_RX[2]
PEG_GTX_C_HRX_P12
C56
C56
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_P12
A21
H35
2
<15> FDI_CTX_PRX_N0
FDI0_TX#[0]
PEG_RX[3]
PEG_GTX_C_HRX_P11
C66
C66
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_P11
H19
H32
2
<15> FDI_CTX_PRX_N1
FDI0_TX#[1]
PEG_RX[4]
PEG_GTX_C_HRX_P10
E19
G34
C68
C68
1 GSGL@ 0.22U_0402_10V6K
2
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_P10
<15> FDI_CTX_PRX_N2
FDI0_TX#[2]
PEG_RX[5]
PEG_GTX_C_HRX_P9
C81
C81
1 GSGL@ 0.22U_0402_10V6K
GSGL@ 0.22U_0402_10V6K
PEG_GTX_HRX_P9
F18
G31
2
<15> FDI_CTX_PRX_N3
FDI0_TX#[3]
PEG_RX[6]
PEG_GTX_C_HRX_P8
PEG_GTX_HRX_P8
B21
F33
C86
C86
1 GSGL@ 0.22U_0402_10V6K
2
GSGL@ 0.22U_0402_10V6K
<15> FDI_CTX_PRX_N4
FDI1_TX#[0]
PEG_RX[7]
PEG_GTX_C_HRX_P7
C89
C89
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P7
C20
F30
2
<15> FDI_CTX_PRX_N5
FDI1_TX#[1]
PEG_RX[8]
PEG_GTX_C_HRX_P6
C100
C100
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P6
D18
E35
2
<15> FDI_CTX_PRX_N6
FDI1_TX#[2]
PEG_RX[9]
PEG_GTX_C_HRX_P5
E17
E33
C105
C105
1 DIS@
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P5
<15> FDI_CTX_PRX_N7
FDI1_TX#[3]
PEG_RX[10]
PEG_GTX_C_HRX_P4
C106
C106
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P4
F32
2
PEG_RX[11]
PEG_GTX_C_HRX_P3
D34
C117
C117
1 DIS@
PEG_GTX_HRX_P3
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_RX[12]
PEG_GTX_C_HRX_P2
C119
C119
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P2
A22
E31
2
<15> FDI_CTX_PRX_P0
FDI0_TX[0]
PEG_RX[13]
PEG_GTX_C_HRX_P1
C135
C135
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P1
G19
C33
2
<15> FDI_CTX_PRX_P1
FDI0_TX[1]
PEG_RX[14]
PEG_GTX_C_HRX_P0
E20
B32
C138
C138
1 DIS@
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P0
2
0.22U_0402_10V6K
<15> FDI_CTX_PRX_P2
FDI0_TX[2]
PEG_RX[15]
G18
<15> FDI_CTX_PRX_P3
FDI0_TX[3]
PEG_HTX_GRX_N15
B20
C516
1 GSGL@ 0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_N15
M29
C516
2
GSGL@
<15> FDI_CTX_PRX_P4
FDI1_TX[0]
PEG_TX#[0]
PEG_HTX_GRX_N14
C520
C520
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_N14
C19
M32
2
<15> FDI_CTX_PRX_P5
FDI1_TX[1]
PEG_TX#[1]
PEG_HTX_GRX_N13
C529
C529
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_N13
D19
M31
2
<15> FDI_CTX_PRX_P6
FDI1_TX[2]
PEG_TX#[2]
PEG_HTX_GRX_N12
F17
L32
C534
C534
1 GSGL@ 0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_N12
2
GSGL@
<15> FDI_CTX_PRX_P7
FDI1_TX[3]
PEG_TX#[3]
PEG_HTX_GRX_N11
C538
C538
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_N11
L29
2
PEG_TX#[4]
+1.05VS_VTT
eDP_COMPIO and ICOMPO signals should
be shorted near balls,
Trace Width for EDP_COMPIO=4mils,
PEG_HTX_GRX_N10
J18
K31
C540
C540
1 GSGL@ 0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_N10
2
GSGL@
<15> FDI_FSYNC0
FDI0_FSYNC
PEG_TX#[5]
PEG_HTX_GRX_N9
C542
C542
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_N9
J17
K28
2
<15> FDI_FSYNC1
FDI1_FSYNC
PEG_TX#[6]
PEG_HTX_GRX_N8
C544
C544
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_N8
J30
2
PEG_TX#[7]
PEG_HTX_GRX_N7
H20
J28
C546
C546
1 DIS@
2
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_N7
0.22U_0402_10V6K
<15> FDI_INT
FDI_INT
PEG_TX#[8]
PEG_HTX_GRX_N6
C548
C548
1 DIS@
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_N6
0.22U_0402_10V6K
H29
2
EDP_ICOMPO=12mils,
PEG_TX#[9]
PEG_HTX_GRX_N5
J19
G27
C550
C550
1 DIS@
2
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_N5
0.22U_0402_10V6K
<15> FDI_LSYNC0
FDI0_LSYNC
PEG_TX#[10]
and both length less than 500 mils
should not be left floating
,even if disable eDP function
R145
R145
PEG_HTX_GRX_N4
C552
C552
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_N4
H17
E29
2
<15> FDI_LSYNC1
FDI1_LSYNC
PEG_TX#[11]
PEG_HTX_GRX_N3
C554
C554
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_N3
24.9_0402_1%
24.9_0402_1%
F27
2
PEG_TX#[12]
PEG_HTX_GRX_N2
D28
C556
C556
1 DIS@
2
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_N2
0.22U_0402_10V6K
PEG_TX#[13]
PEG_HTX_GRX_N1
C558
C558
1 DIS@
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_N1
0.22U_0402_10V6K
F26
2
PEG_TX#[14]
PEG_HTX_GRX_N0
E25
C560
C560
1 DIS@
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_N0
PEG_TX#[15]
EDP_COMP
A18
eDP_COMPIO
B
PEG_HTX_GRX_P15
C515
C515
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_P15
B
A17
M28
2
eDP_ICOMPO
PEG_TX[0]
EDP_HPD#
PEG_HTX_GRX_P14
B16
C528
1 GSGL@ 0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_P14
M33
C528
2
GSGL@
eDP_HPD#
PEG_TX[1]
PEG_HTX_GRX_P13
C533
C533
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_P13
M30
2
PEG_TX[2]
PEG_HTX_GRX_P12
L31
C536
C536
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_P12
2
PEG_TX[3]
PEG_HTX_GRX_P11
C539
C539
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_P11
C15
L28
2
<31> EDP_AUXP
eDP_AUX
PEG_TX[4]
Add eDP circuit
PEG_HTX_GRX_P10
C541
C541
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_P10
D15
K30
2
<31> EDP_AUXN
eDP_AUX#
PEG_TX[5]
PEG_HTX_GRX_P9
K27
C543
C543
1 GSGL@ 0.22U_0402_10V6K
2
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_P9
PEG_TX[6]
PEG_HTX_GRX_P8
C545
C545
1 GSGL@ 0.22U_0402_10V6K
GSGL@
0.22U_0402_10V6K PEG_HTX_C_GRX_P8
J29
2
PEG_TX[7]
PEG_HTX_GRX_P7
C17
J27
C547
C547
1 DIS@
2
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_P7
0.22U_0402_10V6K
<31> EDP_TXP0
eDP_TX[0]
PEG_TX[8]
PEG_HTX_GRX_P6
C549
C549
1 DIS@
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_P6
0.22U_0402_10V6K
F16
H28
2
<31> EDP_TXP1
eDP_TX[1]
PEG_TX[9]
PEG_HTX_GRX_P5
C551
C551
1 DIS@
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_P5
0.22U_0402_10V6K
C16
G28
2
eDP_TX[2]
PEG_TX[10]
PEG_HTX_GRX_P4
G15
E28
C553
C553
1 DIS@
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_P4
eDP_TX[3]
PEG_TX[11]
+1.05VS_VTT
PEG_HTX_GRX_P3
C555
C555
1 DIS@
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_P3
0.22U_0402_10V6K
F28
2
PEG_TX[12]
PEG_HTX_GRX_P2
C18
D27
C557
C557
1 DIS@
2
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_P2
0.22U_0402_10V6K
<31> EDP_TXN0
eDP_TX#[0]
PEG_TX[13]
PEG_HTX_GRX_P1
C559
C559
1 DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K PEG_HTX_C_GRX_P1
E16
E26
2
<31> EDP_TXN1
eDP_TX#[1]
PEG_TX[14]
PEG_HTX_GRX_P0
C561
C561
1 DIS@
DIS@
0.22U_0402_10V6K PEG_HTX_C_GRX_P0
0.22U_0402_10V6K
D16
D25
2
eDP_TX#[2]
PEG_TX[15]
R809
R809
F15
eDP_TX#[3]
EDP@
EDP@
1K_0402_5%
1K_0402_5%
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
<31> EDP_HPD#
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
4
4
4
of
of
of
60
5
4
3
2
1
12
12
Intel(R) FDIeDP
Intel(R) FDIeDP
DMI
DMI
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
12
5 4 3 2 1 D D SNB_IVB# had changed the name to PROC_SELCT#,function for
5
4
3
2
1
D
D
SNB_IVB# had changed the name to
PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
JCPU1B
JCPU1B
CLK_CPU_DMI
A28
BCLK
CLK_CPU_DMI
<14>
CLK_CPU_DMI#
C26
A27
<17> H_SNB_IVB#
PROC_SELECT#
BCLK#
CLK_CPU_DMI#
<14>
AN34
For LVDS
SKTOCC#
CLK_CPU_DPLL
A16
DPLL_REF_CLK
CLK_CPU_DPLL
<14>
CLK_CPU_DPLL#
CLK_CPU_DPLL
A15
For eDP
R516
R516
2
LVDS@
LVDS@
1 1K_0402_5%
1K_0402_5%
DPLL_REF_CLK#
CLK_CPU_DPLL#
<14>
CLK_CPU_DPLL#
R518
R518
LVDS@
LVDS@
1 1K_0402_5%
1K_0402_5%
2
+1.05VS_VTT
T6
T6
PAD
PAD
H_CATERR#
AL33
CATERR#
@
@
Processor Pullups
H_PECI
SM_DRAMRST#
AN33
R8
If use External Graphic or
use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
<18,40> H_PECI
PECI
SM_DRAMRST#
SM_DRAMRST# <6>
R91R91
62_0402_5%62_0402_5%
R92
R92
2
1
+1.05VS_VTT
56_0402_5%
56_0402_5%
H_PROCHOT#
H_PROCHOT#_R
SM_RCOMP0
R231
R231
1 140_0402_1%
140_0402_1%
1
2
AL32
AK1
2
<40,46> H_PROCHOT#
PROCHOT#
SM_RCOMP[0]
C
SM_RCOMP1
R566
R566
1 25.5_0402_1%
25.5_0402_1%
C
A5
2
SM_RCOMP[1]
SM_RCOMP2
R571
R571
1 200_0402_1%
200_0402_1%
A4
2
SM_RCOMP[2]
H_THRMTRIP#
AN32
DDR3 Compensation Signals
<18> H_THRMTRIP#
THERMTRIP#
AP29
PRDY#
AP27
PREQ#
+3VS
TCK
@
@
AR26
PAD
PAD
TCK
T66
T66
TMS
@
@
AR27
PAD
PAD
TMS
T67
T67
H_PM_SYNC
TRST#
AM34
AP30
@
@
<15> H_PM_SYNC
PAD
PAD
PM_SYNC
TRST#
T68
T68
R84R84
10K_0402_5%10K_0402_5%
TDI
2
1
AR28
@
@
PAD
PAD
TDI
T69
T69
TDO
@
@
R40
R40
AP26
PAD
PAD
TDO
T70
T70
H_CPUPWRGD
AP33
1K_0402_5%
1K_0402_5%
<18> H_CPUPWRGD
UNCOREPWRGOOD
UNCOREPWRGOOD:非CORE外的電OK
XDP_DBRESET#
AL35
XDP_DBRESET# <15>
DBR#
PM_DRAM_PWRGD_R
V8
SM_DRAMPWROK
AT28
BPM#[0]
SM_DRAMPWROK:DRAM power ok
AR29
BPM#[1]
AR30
BPM#[2]
BUF_CPU_RST#
AR33
AT30
RESET#
BPM#[3]
AP32
BPM#[4]
AR31
BPM#[5]
AT31
BPM#[6]
AR32
BPM#[7]
B
B
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
Buffered reset to CPU
+3VALW
+3VS
+1.5VS
1
C307
C307
+1.05VS_VTT
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C162
C162
R205
R205
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
U11
U11
200_0402_1%
200_0402_1%
2
R90
R90
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
75_0402_1%
75_0402_1%
1
<15> SYS_PWROK
B
U7
U7
R87
R87
PM_SYS_PWRGD_BUF
PM_DRAM_PWRGD_R
4
1
2
O
1
43_0402_1%
43_0402_1%
2
R204
R204
130_0402_5%
130_0402_5%
<15> PM_DRAM_PWRGD
NC
A
BUFO_CPU_RST#
BUF_CPU_RST#BUF_CPU_RST#
4
1
2
Y
PLT_RST#
R203
R203
2
<17>
PLT_RST#
A
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
2
39_0402_1%
39_0402_1%
@
@
R88
R88
C?
C?
@
@
0_0402_5%
0_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
RESET#:都ok後請CPU做reset
A
A
R04 modify
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
5
5
5
of
of
of
60
5
4
3
2
1
3
5
G
P
12
12
MISCTHERMALPWR
MISCTHERMALPWR
MANAGEMENT
MANAGEMENT
JTAG & BPM
JTAG & BPM
DDR3
DDR3
CLOCKS
CLOCKS
MISC
MISC
3
5
G
P
12
12
12
5 4 3 2 1 JCPU1C JCPU1C JCPU1D JCPU1D AB6 AE2 <11> DDR_A_D[0 63] SA_CLK[0]
5
4
3
2
1
JCPU1C
JCPU1C
JCPU1D
JCPU1D
AB6
AE2
<11> DDR_A_D[0 63]
SA_CLK[0]
SA_CLK_DDR0
<11>
<12> DDR_B_D[0 63]
SB_CLK[0]
SB_CLK_DDR0
<12>
AA6
AD2
SA_CLK#[0]
SA_CLK_DDR#0
<11>
SB_CLK#[0]
SB_CLK_DDR#0
<12>
DDR_A_D0
DDR_B_D0
C5
V9
C9
R9
SA_DQ[0]
SA_CKE[0]
DDRA_CKE0_DIMMA
<11>
SB_DQ[0]
SB_CKE[0]
DDRB_CKE0_DIMMB
<12>
DDR_A_D1
DDR_B_D1
D5
A7
SA_DQ[1]
SB_DQ[1]
DDR_A_D2
DDR_B_D2
D3
D10
SA_DQ[2]
SB_DQ[2]
DDR_A_D3
DDR_B_D3
D2
C8
SA_DQ[3]
SB_DQ[3]
DDR_A_D4
DDR_B_D4
D6
AA5
A9
AE1
SA_DQ[4]
SA_CLK[1]
SA_CLK_DDR1
<11>
SB_DQ[4]
SB_CLK[1]
SB_CLK_DDR1
<12>
D
DDR_A_D5
DDR_B_D5
D
C6
AB5
A8
AD1
SA_DQ[5]
SA_CLK#[1]
SA_CLK_DDR#1
<11>
SB_DQ[5]
SB_CLK#[1]
SB_CLK_DDR#1
<12>
DDR_A_D6
DDR_B_D6
C2
V10
D9
R10
SA_DQ[6]
SA_CKE[1]
DDRA_CKE1_DIMMA
<11>
SB_DQ[6]
SB_CKE[1]
DDRB_CKE1_DIMMB
<12>
DDR_A_D7
DDR_B_D7
C3
D8
SA_DQ[7]
SB_DQ[7]
DDR_A_D8
DDR_B_D8
F10
G4
SA_DQ[8]
SB_DQ[8]
DDR_A_D9
DDR_B_D9
F8
F4
SA_DQ[9]
SB_DQ[9]
DDR_A_D10
DDR_B_D10
G10
AB4
F1
AB2
SA_DQ[10]
RSVD_TP[1]
SB_DQ[10]
RSVD_TP[11]
DDR_A_D11
DDR_B_D11
G9
AA4
G1
AA2
SA_DQ[11]
RSVD_TP[2]
SB_DQ[11]
RSVD_TP[12]
DDR_A_D12
DDR_B_D12
F9
W9
G5
T9
SA_DQ[12]
RSVD_TP[3]
SB_DQ[12]
RSVD_TP[13]
DDR_A_D13
DDR_B_D13
F7
F5
SA_DQ[13]
SB_DQ[13]
DDR_A_D14
DDR_B_D14
G8
F2
SA_DQ[14]
SB_DQ[14]
DDR_A_D15
DDR_B_D15
G7
G2
SA_DQ[15]
SB_DQ[15]
DDR_A_D16
DDR_B_D16
K4
AB3
J7
AA1
SA_DQ[16]
RSVD_TP[4]
SB_DQ[16]
RSVD_TP[14]
DDR_A_D17
DDR_B_D17
K5
AA3
J8
AB1
SA_DQ[17]
RSVD_TP[5]
SB_DQ[17]
RSVD_TP[15]
DDR_A_D18
DDR_B_D18
K1
W10
K10
T10
SA_DQ[18]
RSVD_TP[6]
SB_DQ[18]
RSVD_TP[16]
DDR_A_D19
DDR_B_D19
J1
K9
SA_DQ[19]
SB_DQ[19]
DDR_A_D20
DDR_B_D20
J5
J9
SA_DQ[20]
SB_DQ[20]
DDR_A_D21
DDR_B_D21
J4
J10
SA_DQ[21]
SB_DQ[21]
DDR_A_D22
DDR_B_D22
J2
AK3
K8
AD3
SA_DQ[22]
SA_CS#[0]
DDRA_CS0_DIMMA#
<11>
SB_DQ[22]
SB_CS#[0]
DDRB_CS0_DIMMB#
<12>
DDR_A_D23
DDR_B_D23
K2
AL3
K7
AE3
SA_DQ[23]
SA_CS#[1]
DDRA_CS1_DIMMA#
<11>
SB_DQ[23]
SB_CS#[1]
DDRB_CS1_DIMMB#
<12>
DDR_A_D24
DDR_B_D24
M8
AG1
M5
AD6
SA_DQ[24]
RSVD_TP[7]
SB_DQ[24]
RSVD_TP[17]
DDR_A_D25
DDR_B_D25
N10
AH1
N4
AE6
SA_DQ[25]
RSVD_TP[8]
SB_DQ[25]
RSVD_TP[18]
DDR_A_D26
DDR_B_D26
N8
N2
SA_DQ[26]
SB_DQ[26]
DDR_A_D27
DDR_B_D27
N7
N1
SA_DQ[27]
SB_DQ[27]
DDR_A_D28
DDR_B_D28
M10
M4
SA_DQ[28]
SB_DQ[28]
DDR_A_D29
DDR_B_D29
M9
AH3
N5
AE4
SA_DQ[29]
SA_ODT[0]
SA_ODT0 <11>
SB_DQ[29]
SB_ODT[0]
SB_ODT0 <12>
DDR_A_D30
DDR_B_D30
N9
AG3
M2
AD4
SA_DQ[30]
SA_ODT[1]
SA_ODT1 <11>
SB_DQ[30]
SB_ODT[1]
SB_ODT1 <12>
DDR_A_D31
DDR_B_D31
M7
AG2
M1
AD5
SA_DQ[31]
RSVD_TP[9]
SB_DQ[31]
RSVD_TP[19]
DDR_A_D32
DDR_B_D32
AG6
AH2
AM5
AE5
SA_DQ[32]
RSVD_TP[10]
SB_DQ[32]
RSVD_TP[20]
DDR_A_D33
DDR_B_D33
AG5
AM6
SA_DQ[33]
SB_DQ[33]
DDR_A_D34
DDR_B_D34
AK6
AR3
SA_DQ[34]
SB_DQ[34]
DDR_A_D35
DDR_B_D35
AK5
AP3
SA_DQ[35]
SB_DQ[35]
DDR_A_D36
DDR_B_D36
AH5
AN3
SA_DQ[36]
DDR_A_DQS#[0
7]
<11>
SB_DQ[36]
DDR_B_DQS#[0
7]
<12>
C
DDR_A_D37
DDR_A_DQS#0
DDR_B_D37
DDR_B_DQS#0
C
AH6
C4
AN2
D7
SA_DQ[37]
SA_DQS#[0]
SB_DQ[37]
SB_DQS#[0]
DDR_A_D38
DDR_A_DQS#1
DDR_B_D38
DDR_B_DQS#1
AJ5
G6
AN1
F3
SA_DQ[38]
SA_DQS#[1]
SB_DQ[38]
SB_DQS#[1]
DDR_A_D39
DDR_A_DQS#2
DDR_B_D39
DDR_B_DQS#2
AJ6
J3
AP2
K6
SA_DQ[39]
SA_DQS#[2]
SB_DQ[39]
SB_DQS#[2]
DDR_A_D40
DDR_A_DQS#3
DDR_B_D40
DDR_B_DQS#3
AJ8
M6
AP5
N3
SA_DQ[40]
SA_DQS#[3]
SB_DQ[40]
SB_DQS#[3]
DDR_A_D41
DDR_A_DQS#4
DDR_B_D41
DDR_B_DQS#4
AK8
AL6
AN9
AN5
SA_DQ[41]
SA_DQS#[4]
SB_DQ[41]
SB_DQS#[4]
DDR_A_D42
DDR_A_DQS#5
DDR_B_D42
DDR_B_DQS#5
AJ9
AM8
AT5
AP9
SA_DQ[42]
SA_DQS#[5]
SB_DQ[42]
SB_DQS#[5]
DDR_A_D43
DDR_A_DQS#6
DDR_B_D43
DDR_B_DQS#6
AK9
AR12
AT6
AK12
SA_DQ[43]
SA_DQS#[6]
SB_DQ[43]
SB_DQS#[6]
DDR_A_D44
DDR_A_DQS#7
DDR_B_D44
DDR_B_DQS#7
AH8
AM15
AP6
AP15
SA_DQ[44]
SA_DQS#[7]
SB_DQ[44]
SB_DQS#[7]
DDR_A_D45
DDR_B_D45
AH9
AN8
SA_DQ[45]
SB_DQ[45]
DDR_A_D46
DDR_B_D46
AL9
AR6
SA_DQ[46]
SB_DQ[46]
DDR_A_D47
DDR_B_D47
AL8
AR5
SA_DQ[47]
SB_DQ[47]
DDR_A_D48
DDR_B_D48
AP11
AR9
SA_DQ[48]
DDR_A_DQS[0
7]
<11>
SB_DQ[48]
DDR_B_DQS[0
7]
<12>
DDR_A_D49
DDR_A_DQS0
DDR_B_D49
DDR_B_DQS0
AN11
D4
AJ11
C7
SA_DQ[49]
SA_DQS[0]
SB_DQ[49]
SB_DQS[0]
DDR_A_D50
DDR_A_DQS1
DDR_B_D50
DDR_B_DQS1
AL12
F6
AT8
G3
SA_DQ[50]
SA_DQS[1]
SB_DQ[50]
SB_DQS[1]
DDR_A_D51
DDR_A_DQS2
DDR_B_D51
DDR_B_DQS2
AM12
K3
AT9
J6
SA_DQ[51]
SA_DQS[2]
SB_DQ[51]
SB_DQS[2]
DDR_A_D52
DDR_A_DQS3
DDR_B_D52
DDR_B_DQS3
AM11
N6
AH11
M3
SA_DQ[52]
SA_DQS[3]
SB_DQ[52]
SB_DQS[3]
DDR_A_D53
DDR_A_DQS4
DDR_B_D53
DDR_B_DQS4
AL11
AL5
AR8
AN6
SA_DQ[53]
SA_DQS[4]
SB_DQ[53]
SB_DQS[4]
DDR_A_D54
DDR_A_DQS5
DDR_B_D54
DDR_B_DQS5
AP12
AM9
AJ12
AP8
SA_DQ[54]
SA_DQS[5]
SB_DQ[54]
SB_DQS[5]
DDR_A_D55
DDR_A_DQS6
DDR_B_D55
DDR_B_DQS6
AN12
AR11
AH12
AK11
SA_DQ[55]
SA_DQS[6]
SB_DQ[55]
SB_DQS[6]
DDR_A_D56
DDR_A_DQS7
DDR_B_D56
DDR_B_DQS7
AJ14
AM14
AT11
AP14
SA_DQ[56]
SA_DQS[7]
SB_DQ[56]
SB_DQS[7]
DDR_A_D57
DDR_B_D57
AH14
AN14
SA_DQ[57]
SB_DQ[57]
DDR_A_D58
DDR_B_D58
AL15
AR14
SA_DQ[58]
SB_DQ[58]
DDR_A_D59
DDR_B_D59
AK15
AT14
SA_DQ[59]
SB_DQ[59]
DDR_A_D60
DDR_B_D60
AL14
AT12
SA_DQ[60]
DDR_A_MA[0
15]
<11>
SB_DQ[60]
DDR_B_MA[0
15]
<12>
DDR_A_D61
DDR_A_MA0
DDR_B_D61
DDR_B_MA0
AK14
AD10
AN15
AA8
SA_DQ[61]
SA_MA[0]
SB_DQ[61]
SB_MA[0]
DDR_A_D62
DDR_A_MA1
DDR_B_D62
DDR_B_MA1
AJ15
W1
AR15
T7
SA_DQ[62]
SA_MA[1]
SB_DQ[62]
SB_MA[1]
DDR_A_D63
DDR_A_MA2
DDR_B_D63
DDR_B_MA2
AH15
W2
AT15
R7
SA_DQ[63]
SA_MA[2]
SB_DQ[63]
SB_MA[2]
DDR_A_MA3
DDR_B_MA3
W7
T6
SA_MA[3]
SB_MA[3]
DDR_A_MA4
DDR_B_MA4
V3
T2
SA_MA[4]
SB_MA[4]
DDR_A_MA5
DDR_B_MA5
V2
T4
SA_MA[5]
SB_MA[5]
DDR_A_MA6
DDR_B_MA6
W3
T3
SA_MA[6]
SB_MA[6]
DDR_A_MA7
DDR_B_MA7
AE10
W6
AA9
R2
<11> DDR_A_BS0
SA_BS[0]
SA_MA[7]
<12> DDR_B_BS0
SB_BS[0]
SB_MA[7]
B
DDR_A_MA8
DDR_B_MA8
B
AF10
V1
AA7
T5
<11> DDR_A_BS1
SA_BS[1]
SA_MA[8]
<12> DDR_B_BS1
SB_BS[1]
SB_MA[8]
DDR_A_MA9
DDR_B_MA9
V6
W5
R6
R3
<11> DDR_A_BS2
SA_BS[2]
SA_MA[9]
<12> DDR_B_BS2
SB_BS[2]
SB_MA[9]
DDR_A_MA10
DDR_B_MA10
AD8
AB7
SA_MA[10]
SB_MA[10]
DDR_A_MA11
DDR_B_MA11
V4
R1
SA_MA[11]
SB_MA[11]
DDR_A_MA12
DDR_B_MA12
W4
T1
SA_MA[12]
SB_MA[12]
DDR_A_MA13
DDR_B_MA13
AE8
AF8
AA10
AB10
<11> DDR_A_CAS#
SA_CAS#
SA_MA[13]
<12> DDR_B_CAS#
SB_CAS#
SB_MA[13]
DDR_A_MA14
DDR_B_MA14
AD9
V5
AB8
R5
<11> DDR_A_RAS#
SA_RAS#
SA_MA[14]
<12> DDR_B_RAS#
SB_RAS#
SB_MA[14]
DDR_A_MA15
DDR_B_MA15
AF9
V7
AB9
R4
<11> DDR_A_WE#
SA_WE#
SA_MA[15]
<12> DDR_B_WE#
SB_WE#
SB_MA[15]
D
D
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
CONN@
CONN@
G G
S
S
Follow CRB1.0
+1.5V
@R184
@ R184
0_0402_5%
0_0402_5%
R217
R217
CPU通知 DIMM做 reset
1K_0402_5%
1K_0402_5%
1
2
R155
R155
1K_0402_5%
1K_0402_5%
SM_DRAMRST#
DIMM_DRAMRST#_R
3
1
1
2
<5> SM_DRAMRST#
DIMM_DRAMRST#
<11,12>
Q12
Q12
2
R02 modify for ESD
S
S
TR SSM3K7002F 1N SC59-3
TR SSM3K7002F 1N SC59-3
C2065
C2065
R186
R186
S0
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.99K_0402_1%
4.99K_0402_1%
RST_GATE hgih ,MOS ON
1
A
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
A
S3
<11,12,14>
RST_GATE
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
1 S4,5
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
C293
C293
RST_GATE Low ,MOS OFF
0.047U_0402_16V7K
0.047U_0402_16V7K
2 SM_DRAMRST# lo,DIMM_DRAMRST# low
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Dimm reset
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
6
6
6
of
of
of
60
5
4
3
2
1
1
2
2
12
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B

5

4

3

2

1

D

C

5 4 3 2 1 D C D B A CFG Straps for Processor CFG2 Sandy

D

5 4 3 2 1 D C D B A CFG Straps for Processor CFG2 Sandy

B

A

CFG Straps for Processor

CFG2 Sandy Ivy R112 R112 AH26 1K_0402_5% 1K_0402_5% GND VSS_DIE_SENSE JCPU1E JCPU1E PEG Static Lane
CFG2
Sandy
Ivy
R112
R112
AH26
1K_0402_5%
1K_0402_5%
GND
VSS_DIE_SENSE
JCPU1E
JCPU1E
PEG Static Lane Reversal - CFG2 is for the 16x
AH27 change to VCC_DIE_SENSE
AH27
CFG2
@@
PADPAD
T7T7
VCC_DIE_SENSE
1: Normal Operation; Lane # definition matches
socket pin map definition
T8
T8
PAD
PAD
CFG0
AK28
AH26
@@
PADPAD
T74T74
CFG[0]
VSS_DIE_SENSE
@
@
AK29
CFG[1]
CFG2
AL26
0:Lane Reversed
CFG[2]
*
AL27
CFG[3]
CFG4
AK26
L7
CFG[4]
RSVD28
CFG5
CFG4
AL29
AG7
CFG[5]
RSVD29
CFG6
AL30
AE7
CFG[6]
RSVD30
CFG7
AM31
AK2
EDP@
EDP@
CFG[7]
RSVD31
AM32
CFG[8]
AM30
W8
R109
R109
CFG[9]
RSVD32
1K_0402_5%
1K_0402_5%
AM28
CFG[10]
AM26
CFG[11]
AN28
AT26
CFG[12]
RSVD33
AN31
AM33
CFG[13]
RSVD34
AN26
AJ27
CFG[14]
RSVD35
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
R811
R811
Display Port Presence Strap
@
@
49.9_0402_1%
49.9_0402_1%
T8
RSVD37
J16
1
RSVD38
VAXG_VAL_SENSE
*
AJ31
H16
CFG4
VAXG_VAL_SENSE
RSVD39
: Disabled; No Physical Display Port
attached to Embedded Display Port
VSSAXG_VAL_SENSE
AH31
G16
VSSAXG_VAL_SENSE
RSVD40
VCC_VAL_SENSE
AJ33
VCC_VAL_SENSE
VSS_VAL_SENSE
AH33
: Enabled; An external Display Port device is
connected to the Embedded Display Port
0
VSS_VAL_SENSE
AJ26
AR35
RSVD5
RSVD_NCTF1
R813
R813
AT34
RSVD_NCTF2
@
@
AT33
RSVD_NCTF3
49.9_0402_1%
49.9_0402_1%
CFG6
AP35
RSVD_NCTF4
AR34
RSVD_NCTF5
CFG5
GM@
GM@
F25
RSVD8
R107
R107
R108
R108
F24
RSVD9
F23
1K_0402_5%
1K_0402_5%
@
@
1K_0402_5%
1K_0402_5%
RSVD10
D24
B34
RSVD11
RSVD_NCTF6
G25
A33
RSVD12
RSVD_NCTF7
G24
A34
RSVD13
RSVD_NCTF8
E23
B35
RSVD14
RSVD_NCTF9
D23
C35
RSVD15
RSVD_NCTF10
C30
RSVD16
A31
RSVD17
B30
PCIE Port Bifurcation Straps
RSVD18
B29
RSVD19
D30
AJ32
RSVD20
RSVD51
B31
AK32
11: (Default) x16 - Device 1 functions 1 and 2 disabled
RSVD21
RSVD52
*
A30
RSVD22
C29
CFG[6:5]
RSVD23
AN35
BCLK_ITP
J20
AM35
RSVD24
BCLK_ITP#
B18
RSVD25
RSVD54 and RSVD55 had changed to
BCLK_ITP and BCLK_ITP#
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
J15
AT2
RSVD27
RSVD_NCTF11
AT1
RSVD_NCTF12
AR1
RSVD_NCTF13
CFG7
B1
KEY
R102
R102
@
@
1K_0402_5%
1K_0402_5%
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
1
2
1
2
1
2
1
2
CFG
CFG
RESERVED
RESERVED
12
12
12
12
12

+CPU_CORE +VGFX_CORE

R810

R810

R812

R812

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

Security Classification

Security Classification

Security Classification

Compal Secret Data

Compal Secret Data

Compal Secret Data

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

C

@ @

49.9_0402_1%

49.9_0402_1%

@ @

49.9_0402_1%

49.9_0402_1%

B

A

5

Issued Date

Issued Date

Issued Date

2011/06/02

2011/06/02

2011/06/02

Deciphered Date

Deciphered Date

Deciphered Date

2012/06/02

2012/06/02

2012/06/02

Title

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC,MB A7912

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size

Size

Size

Document Number

Document Number

Document Number

Custom

Custom

Custom

4019ID

Rev

Rev

Rev

B

4

3

2

1

Date:

Date:

Date:

Friday, January 06, 2012

Friday, January 06, 2012

Friday, January 06, 2012

Sheet

Sheet

Sheet

7

7 7

of

of

of

60

5 4 3 2 1 POWER POWER SV type CPU JCPU1F JCPU1F +CPU_CORE QC 53A
5
4
3
2
1
POWER
POWER
SV type CPU
JCPU1F
JCPU1F
+CPU_CORE
QC
53A
DC
53A
+1.05VS_VTT
8.5A
AG35
VCC1
AG34
AH13
VCC2
VCCIO1
AG33
AH10
VCC3
VCCIO2
AG32
AG10
VCC4
VCCIO3
AG31
AC10
VCC5
VCCIO4
D
D
AG30
Y10
VCC6
VCCIO5
AG29
U10
VCC7
VCCIO6
AG28
P10
VCC8
VCCIO7
AG27
L10
VCC9
VCCIO8
AG26
J14
VCC10
VCCIO9
AF35
J13
VCC11
VCCIO10
AF34
J12
VCC12
VCCIO11
AF33
J11
VCC13
VCCIO12
AF32
H14
VCC14
VCCIO13
AF31
H12
VCC15
VCCIO14
AF30
H11
VCC16
VCCIO15
AF29
G14
VCC17
VCCIO16
AF28
G13
VCC18
VCCIO17
AF27
G12
VCC19
VCCIO18
AF26
F14
VCC20
VCCIO19
AD35
F13
VCC21
VCCIO20
AD34
F12
VCC22
VCCIO21
AD33
F11
VCC23
VCCIO22
AD32
E14
VCC24
VCCIO23
AD31
E12
VCC25
VCCIO24
AD30
VCC26
AD29
E11
VCC27
VCCIO25
AD28
D14
VCC28
VCCIO26
AD27
D13
VCC29
VCCIO27
AD26
D12
VCC30
VCCIO28
AC35
D11
VCC31
VCCIO29
AC34
C14
VCC32
VCCIO30
AC33
C13
VCC33
VCCIO31
AC32
C12
VCC34
VCCIO32
AC31
C11
VCC35
VCCIO33
AC30
B14
VCC36
VCCIO34
AC29
B12
VCC37
VCCIO35
C
C
AC28
A14
VCC38
VCCIO36
AC27
A13
VCC39
VCCIO37
AC26
A12
VCC40
VCCIO38
AA35
A11
VCC41
VCCIO39
AA34
VCC42
AA33
J23
VCC43
VCCIO40
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
+1.05VS_VTT
AA27
VCC49
+1.05VS_VTT
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
R450
R450
R447
R447
VCC56
130_0402_1%
130_0402_1%
Y29
75_0402_5%
75_0402_5%
VCC57
Y28
VCC58
Y27
VCC59
R448
R448
Y26
VCC60
V35
43_0402_1%
43_0402_1%
VCC61
H_CPU_SVIDALRT#
V34
AJ29
1 2
VCC62
VIDALERT#
VR_SVID_ALRT#
<52>
H_CPU_SVIDCLK
V33
AJ30
R446
R446
1 0_0402_5%
2
0_0402_5%
VCC63
VIDSCLK
VR_SVID_CLK
<52>
H_CPU_SVIDDAT
R449
R449
1 0_0402_5%
0_0402_5%
V32
AJ28
2
VCC64
VIDSOUT
VR_SVID_DAT
<52>
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
B
B
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
Place the PU
resistors close to CPU
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
+CPU_CORE
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R445
R445
R32
VCC84
R31
100_0402_1%
100_0402_1%
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
VCCSENSE_R
R444
R444
1 0_0402_5%
0_0402_5%
R27
AJ35
2
VCC89
VCC_SENSE
VCCSENSE
<52>
VSSSENSE_R
R443
R443
1 0_0402_5%
0_0402_5%
R26
AJ34
2
VCC90
VSS_SENSE
VSSSENSE
<52>
P35
VCC91
P34
1
2
+1.05VS_VTT
VCC92
P33
R910
R910
10_0402_5%
10_0402_5%
VCC93
R442
R442
P32
B10
VCC94
VCCIO_SENSE
VCCIO_SENSE
<50>
VSSIO_SENSE
P31
A10
100_0402_1%
100_0402_1%
VCC95
VSS_SENSE_VCCIO
VSSIO_SENSE
<50>
P30
VSSIO_SENSE
VCC96
P29
VCC97
change to
P28
VCC98
VSS_SENSE_VCCIO
R163
R163
P27
VCC99
10_0402_5%
10_0402_5%
P26
VCC100
A
Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.
A
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
8
8
8
of
of
of
60
5
4
3
2
1
CORE SUPPLY
CORE SUPPLY
SENSE LINES
SENSE LINES
SVID
SVID
PEG AND DDR
PEG AND DDR
12
12
12
12
12
5 4 3 2 1 C355 C355 330U_D2_2V_Y 330U_D2_2V_Y C361 C361 10U_0603_6.3V6M 10U_0603_6.3V6M C829 C829
5
4
3
2
1
C355
C355
330U_D2_2V_Y
330U_D2_2V_Y
C361
C361
10U_0603_6.3V6M
10U_0603_6.3V6M
C829
C829
10U_0603_6.3V6M
10U_0603_6.3V6M
C365
C365
10U_0603_6.3V6M
10U_0603_6.3V6M
+VGFX_CORE
C828
C828
10U_0603_6.3V6M
10U_0603_6.3V6M
C341
C341
10U_0603_6.3V6M
10U_0603_6.3V6M
D
D
C213
C213
POWER
POWER
R903
R903
10U_0603_6.3V6M
10U_0603_6.3V6M
QC
46A
+VGFX_CORE
C362
C362
JCPU1G
JCPU1G
10_0402_5%
10_0402_5%
10U_0603_6.3V6M
10U_0603_6.3V6M
DC
33A
C219
C219
10U_0603_6.3V6M
10U_0603_6.3V6M
AT24
AK35
VAXG1
VAXG_SENSE
VCC_AXG_SENSE
<52>
C364
C364
AT23
AK34
VAXG2
VSSAXG_SENSE
VSS_AXG_SENSE <52>
+1.5VS
10U_0603_6.3V6M
10U_0603_6.3V6M
AT21
VAXG3
C605
C605
AT20
VAXG4
10U_0603_6.3V6M
10U_0603_6.3V6M
AT18
R904
R904
VAXG5
C363
C363
AT17
VAXG6
10U_0603_6.3V6M
10U_0603_6.3V6M
AR24
10_0402_5%
10_0402_5%
R582
R582
VAXG7
C214
C214
1K_0402_1%
1K_0402_1%
AR23
VAXG8
10U_0603_6.3V6M
10U_0603_6.3V6M
AR21
VAXG9
+V_SM_VREF should
have 20 mil trace width
AR20
VAXG10
+V_SM_VREF
AR18
AL1
VAXG11
SM_VREF
AR17
VAXG12
AP24
1
VAXG13
C688
C688
R575
R575
AP23
VAXG14
AP21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1K_0402_1%
1K_0402_1%
VAXG15
SA_DIMM_VREFDQ
AP20
B4
VAXG16
SA_DIMM_VREFDQ
SA_DIMM_VREFDQ
<11>
2
SB_DIMM_VREFDQ
AP18
D1
VAXG17
SB_DIMM_VREFDQ
SB_DIMM_VREFDQ
<12>
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
INTEL Recommend
AN18
VAXG23
+1.5VS
AN17
5A
VAXG24
1*330uF,6*10uF
AM24
AF7
VAXG25
VDDQ1
AM23
AF4
VAXG26
VDDQ2
C
from CR PDDG 0.8
C
AM21
AF1
VAXG27
VDDQ3
AM20
AC7
1 1
1
1
1
1
1
VAXG28
VDDQ4
AM18
AC4
VAXG29
VDDQ5
+ +
AM17
AC1
VAXG30
VDDQ6
AL24
Y7
VAXG31
VDDQ7
2 2
2
2
2
2
AL23
Y4
VAXG32
VDDQ8
2
AL21
Y1
VAXG33
VDDQ9
AL20
U7
VAXG34
VDDQ10
AL18
U4
VAXG35
VDDQ11
AL17
U1
VAXG36
VDDQ12
AK24
P7
VAXG37
VDDQ13
AK23
P4
VAXG38
VDDQ14
AK21
P1
VAXG39
VDDQ15
AK20
VAXG40
AK18
VAXG41
INTEL Recommend
AK17
VAXG42
AJ24
VAXG43
1*330uF,3*10uF
AJ23
VAXG44
AJ21
VAXG45
+VCCSA
AJ20
6A
from CR PDDG 0.8
VAXG46
AJ18
VAXG47
+VCCSA
R137
R137
@
@
0_0402_5%
0_0402_5%
+VCCSA_SENSE
AJ17
M27
1
2
VAXG48
VCCSA1
AH24
M26
VAXG49
VCCSA2
AH23
L26
1
VAXG50
VCCSA3
AH21
J26
1
1 1
1 1
1
VAXG51
VCCSA4
+
AH20
J25
+ C221
C221
VCCSA
VAXG52
VCCSA5
@
@
AH18
J24
VAXG53
VCCSA6
330U_D2_2V_Y
330U_D2_2V_Y
VID0
VID1
Vout
Sandy
Ivy
AH17
H26
VAXG54
VCCSA7
2
2 2
2 2
2
2
C653
C653
H25
VCCSA8
1U_0402_6.3V6K
1U_0402_6.3V6K
0
0
0.9V
V
V
INTEL Recommend
0
1
0.8V
V
V
C654
C654
B
1U_0402_6.3V6K
1U_0402_6.3V6K
1*330uF,1*10uF and 2*1uF(0402)
from CR PDDG 0.8
B
1
0
0.725V
X
V
1.2A
H23
VCCSA_SENSE
+VCCSA_SENSE
<51>
+1.8VS
1
1
0.675V
X
V
+VCCPLL
1
2
B6
VCCPLL1
C655
C655
R528
R528
0_0805_5%
0_0805_5%
H_VCCSA_VID0
1
A6
C22
VCCPLL2
VCCSA_VID[0]
H_VCCSA_VID0
<51>
10U_0603_6.3V6M
10U_0603_6.3V6M
H_VCCSA_VID1
1 1
1
1
1
A2
C24
VCCPLL3
VCCSA_VID[1]
H_VCCSA_VID1
<51>
+ +
@
@
C830
C830
2
2 2
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
VCCIO_SEL
A19
R138
R138
VCCIO_SEL
0_0402_5%
0_0402_5%
@
@
C831
C831
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
10U_0603_6.3V6M
10U_0603_6.3V6M
CONN@
CONN@
+3VALW
C664
C664
330U_D2_2V_Y
330U_D2_2V_Y
VCCIO_SEL For 2012 CPU support
R909
R909
10K_0402_5%
10K_0402_5%
1/NC : (Default) +1.05VS_VTT
A19
*
0: +1.0VS_VTT
VCCIO_SEL
RSVD26 had changed the name to VCCIO_SEL
Need PH +3VALW 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select
R913
R913
@
@
A
A
10K_0402_5%
10K_0402_5%
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2011/06/02
2011/06/02
2011/06/02
2012/06/02
2012/06/02
2012/06/02
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
SCHEMATIC,MB A7912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019ID
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Sheet
Sheet
Sheet
9 9 9
of
of
of
60
5
4
3
2
1
1.8V RAIL
1.8V RAIL
GRAPHICS
GRAPHICS
SENSE
SENSE
VREFMISC
VREFMISC
SA RAIL
SA RAIL
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
LINES
LINES
12
12
12
12
12
12
12

5

4

3

2

1

JCPU1H JCPU1H JCPU1I JCPU1I AT35 AJ22 VSS1 VSS81 AT32 AJ19 VSS2 VSS82 AT29 AJ16 T35
JCPU1H
JCPU1H
JCPU1I
JCPU1I
AT35
AJ22
VSS1
VSS81
AT32
AJ19
VSS2
VSS82
AT29
AJ16
T35
F22
VSS3
VSS83
VSS161
VSS234
AT27
AJ13
T34
F19
VSS4
VSS84
VSS162
VSS235
AT25
AJ10
T33
E30
VSS5
VSS85
VSS163
VSS236
AT22
AJ7
T32
E27
VSS6
VSS86
VSS164
VSS237
AT19
AJ4
T31
E24
VSS7
VSS87
VSS165
VSS238
AT16
AJ3
T30
E21
VSS8
VSS88
VSS166
VSS239
AT13
AJ2
T29
E18
VSS9
VSS89
VSS167
VSS240
AT10
AJ1
T28
E15
VSS10
VSS90
VSS168
VSS241
AT7
AH35
T27
E13
VSS11
VSS91
VSS169
VSS242
AT4
AH34
T26
E10
VSS12
VSS92
VSS170
VSS243
AT3
AH32
P9
E9
VSS13
VSS93
VSS171
VSS244
AR25
AH30
P8
E8
VSS14
VSS94
VSS172
VSS245
AR22
AH29
P6
E7
VSS15
VSS95
VSS173
VSS246
AR19
AH28
P5
E6
VSS16
VSS96
VSS174
VSS247
AR16
AH25
P3
E5
VSS17
VSS98
VSS175
VSS248
AR13
AH22
P2
E4
VSS18
VSS99
VSS176
VSS249
AR10
AH19
N35
E3
VSS19
VSS100
VSS177
VSS250
AR7
AH16
N34
E2
VSS20
VSS101
VSS178
VSS251
AR4
AH7
N33
E1
VSS21
VSS102
VSS179
VSS252
AR2
AH4
N32
D35
VSS22
VSS103
VSS180
VSS253
AP34
AG9
N31
D32
VSS23
VSS104
VSS181
VSS254
AP31
AG8
N30
D29
VSS24
VSS105
VSS182
VSS255
AP28
AG4
N29
D26
VSS25
VSS106
VSS183
VSS256
AP25
AF6
N28
D20
VSS26
VSS107
VSS184
VSS257
AP22
AF5
N27
D17
VSS27
VSS108
VSS185
VSS258
AP19
AF3
N26
C34
VSS28
VSS109
VSS186
VSS259
AP16
AF2
M34
C31
VSS29
VSS110
VSS187
VSS260
AP13
AE35
L33
C28
VSS30
VSS111
VSS188
VSS261
AP10
AE34
L30
C27
VSS31
VSS112
VSS189
VSS262
AP7
AE33
L27
C25
VSS32
VSS113
VSS190
VSS263
AP4
AE32
L9
C23
VSS33
VSS114
VSS191
VSS264
AP1
AE31
L8
C10
VSS34
VSS115
VSS192
VSS265
AN30
AE30
L6
C1
VSS35
VSS116
VSS193
VSS266
AN27
AE29
L5
B22
VSS36
VSS117
VSS194
VSS267
AN25
VSS
L4
VSS37
VSS
AE28
VSS
B19
VSS118
VSS195
VSS
VSS268
AN22
AE27
L3
B17
VSS38
VSS119
VSS196
VSS269
AN19
AE26
L2
B15
VSS39
VSS120
VSS197
VSS270
AN16
AE9
L1
B13
VSS40
VSS121
VSS198
VSS271
AN13
AD7
K35
B11
VSS41
VSS122
VSS199
VSS272
AN10
AC9
K32
B9
VSS42
VSS123
VSS200
VSS273
AN7
AC8
K29
B8
VSS43
VSS124
VSS201
VSS274
AN4
AC6
K26
B7
VSS44
VSS125
VSS202
VSS275
AM29
AC5
J34
B5
VSS45
VSS126
VSS203
VSS276
AM25
AC3
J31
B3
VSS46
VSS127
VSS204
VSS277
AM22
AC2
H33
B2
VSS47
VSS128
VSS205
VSS278
AM19
AB35
H30
A35
VSS48
VSS129
VSS206
VSS279
AM16
AB34
H27
A32
VSS49
VSS130
VSS207
VSS280
AM13
AB33
H24
A29
VSS50
VSS131
VSS208
VSS281
AM10
AB32
H21
A26
VSS51
VSS132
VSS209
VSS282
AM7
AB31
H18
A23
VSS52
VSS133
VSS210
VSS283
AM4
AB30
H15
A20
VSS53
VSS134
VSS211
VSS284
AM3
AB29
H13
A3
VSS54
VSS135
VSS212
VSS285
AM2
AB28
H10
VSS55
VSS136
VSS213
AM1
AB27
H9
VSS56
VSS137
VSS214
AL34
AB26
H8
VSS57
VSS138
VSS215
AL31
Y9
H7
VSS58
VSS139
VSS216
AL28
Y8
H6
VSS59
VSS140
VSS217
AL25
Y6
H5
VSS60
VSS141
VSS218
AL22
Y5
H4
VSS61
VSS142
VSS219
AL19
Y3
H3
VSS62
VSS143
VSS220
AL16
Y2
H2
VSS63
VSS144
VSS221
AL13
W35
H1
VSS64
VSS145
VSS222
AL10
W34
G35
VSS65
VSS146
VSS223
AL7
W33
G32
VSS66
VSS147
VSS224
AL4
W32
G29
VSS67
VSS148
VSS225
AL2
W31
G26
VSS68
VSS149
VSS226
AK33
W30
G23
VSS69
VSS150
VSS227
AK30
W29
G20
VSS70
VSS151
VSS228
AK27
W28
G17
VSS71
VSS152
VSS229
AK25
W27
G11
VSS72
VSS153
VSS230
AK22
W26
F34
VSS73
VSS154
VSS231
AK19
U9
F31
VSS74
VSS155
VSS232
AK16
U8
F29
VSS75
VSS156
VSS233
AK13
U6
VSS76
VSS157
AK10
U5
VSS77
VSS158
AK7
U3
VSS78
VSS159
AK4
U2
VSS79
VSS160
AJ25
VSS80
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
CONN@
CONN@

D

D

C

C

BRIDGE CONN@ CONN@ CONN@ CONN@ D D C C B A 5 B A Security Classification
BRIDGE CONN@ CONN@ CONN@ CONN@ D D C C B A 5 B A Security Classification

B

A

5

B

A

Security Classification

Security Classification

Security Classification

Compal Secret Data

Compal Secret Data

Compal Secret Data

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Issued Date

Issued Date

Issued Date

2011/06/02

2011/06/02

2011/06/02

Deciphered Date

Deciphered Date

Deciphered Date

2012/06/02

2012/06/02

2012/06/02

Title

Title

Title

SCHEMATIC,MB A7912

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Size

Size

Size

Custom

Custom

Custom

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Document Number

Document Number

Document Number

4019ID

Rev

Rev

Rev

B

Date:

Date:

Date:

Friday, January 06, 2012

Friday, January 06, 2012

Friday, January 06, 2012

Sheet

Sheet

Sheet

10 10

10

of

of

of

60

4

3

2

1

C409 C409 C388 C388 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C414 C414 C407 C407
C409
C409
C388
C388
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C414
C414
C407
C407
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D2_2V_Y
330U_D2_2V_Y
C410
C410
C394
C394
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C415
C415
C383
C383
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C385
C385
C395
C395
1U_0402_6.3V6K
1U_0402_6.3V6K
C378
C378
C412
C412
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C371
C371
C384
C384
C413
C413
C393
C393
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
5
4
3
2
1
+1.5V
R320
R320
DDR_A_DQS#[0
7]
<6>
1K_0402_5%
1K_0402_5%
+1.5V
+1.5V
M3 support
@
@
R133
R133
DDR_A_DQS[0
7]
<6>
0_0402_5%
0_0402_5%
JDIMM1
JDIMM1
+V_DDR_REFA
1
2
1
2
<9> SA_DIMM_VREFDQ
VREF_DQ
VSS1
DDR_A_D[0
63]
<6>
DDR_A_D4
3
4
VSS2
DQ4
DDR_A_D0
DDR_A_D5
5
6
DQ0
DQ5
DDR_A_MA[0
15]
<6>
DDR_A_D1
7
8
DQ1
VSS3
1
R319
R319
DDR_A_DQS#0
3
1
1 9
10
VSS4
DQS#0
C373
C373
Q46
Q46
1K_0402_5%
1K_0402_5%
DDR_A0_DM0
DDR_A_DQS0
11
12
DM0
DQS0
0.1U_0402_16V4Z
0.1U_0402_16V4Z
S
S
TR SSM3K7002F 1N SC59-3
TR SSM3K7002F 1N SC59-3
@
@
13
14
VSS5
VSS6
D
DDR_A_D2
2
DDR_A_D6
D
15
16
2
DQ2
DQ6
DDR_A_D3
DDR_A_D7
17
18
<6,12,14>
RST_GATE
DQ3
DQ7
C2066
C2066
19
20
Layout Note:
VSS7
VSS8
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C372
C372
DDR_A_D8
DDR_A_D12
21
22
DQ8
DQ12
Place near JDIMM1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
DDR_A_D9
DDR_A_D13
23
24
DQ9
DQ13
+1.5V
25
26
VSS9
VSS10
DDR_A_DQS#1
DDR_A0_DM1
27
28
DQS#1
DM1
DDR_A_DQS1
DDR3_DRAMRST#
29
30
DIMM_DRAMRST#
<6,12>
DQS1
RESET#
All VREF traces should
have 10 mil trace width
31
32
VSS11
VSS12
DDR_A_D10
DDR_A_D14
33
34
DQ10
DQ14
DDR_A_D11
DDR_A_D15
35
36
1
1 1
1
1
DQ11
DQ15
37
38
VSS13
VSS14
DDR_A_D16
DDR_A_D20
39
40
DQ16
DQ20
DDR_A_D17
DDR_A_D21
41
42
DQ17
DQ21
2
2 2
2
2
43
44
VSS15
VSS16
DDR_A_DQS#2
DDR_A0_DM2
45
46
DQS#2
DM2
DDR_A_DQS2
47
48
DQS2
VSS17
DDR_A_D22
49
50
VSS18
DQ22
DDR_A_D18
DDR_A_D23
R02 modify for ESD
51
52
DQ18
DQ23
DDR_A_D19
53
54
DQ19
VSS19
DDR_A_D28
55
56
VSS20
DQ28
DDR_A_D24
DDR_A_D29
57
58
DQ24
DQ29
DDR_A_D25
59
60
DQ25
VSS21
+1.5V
DDR_A_DQS#3
61
62
VSS22
DQS#3
DDR_A0_DM3
DDR_A_DQS3
63
64
DM3
DQS3
65
66
VSS23
VSS24
DDR_A_D26
DDR_A_D30
67
68
DQ26
DQ30
DDR_A_D27
DDR_A_D31
69
70
DQ27
DQ31
71
72
1
1
1
1
VSS25
VSS26
2
2 2
2
C
DDRA_CKE0_DIMMA
DDRA_CKE1_DIMMA
C
73
74
<6> DDRA_CKE0_DIMMA
DDRA_CKE1_DIMMA
<6>
CKE0
CKE1
75
76
VDD1
VDD2
DDR_A_MA15
77
78
NC1
A15
DDR_A_BS2
DDR_A_MA14
79
80
<6> DDR_A_BS2
BA2
A14
81
82
VDD3
VDD4
DDR_A_MA12
DDR_A_MA11
83
84
A12/BC#
A11
DDR_A_MA9
DDR_A_MA7
85
86
A9
A7
87
88
VDD5
VDD6
+1.5V
DDR_A_MA8
DDR_A_MA6
89
90
A8
A6
R301
R301
DDR_A_MA5
DDR_A_MA4
91
92
A5
A4
10K_0402_5%
10K_0402_5%
93
94
CHG C407 to oscon
VDD7
VDD8
DDR_A_MA3
DDR_A_MA2
95
96
A3
A2
DDR_A_MA1
DDR_A_MA0
97
98
1
A1
A0
R302
R302
99
100
@
@
1
1 1
VDD9
VDD10
10K_0402_5%
10K_0402_5%
+ +
SA_CLK_DDR0
SA_CLK_DDR1
101
102
<6> SA_CLK_DDR0
SA_CLK_DDR1
<6>
CK0
CK1
SA_CLK_DDR#0
SA_CLK_DDR#1
103
104
<6> SA_CLK_DDR#0
SA_CLK_DDR#1
<6>
CK0#
CK1#
+1.5V
@
@
105
106
VDD11
VDD12
2
2
2
2
DDR_A_MA10
DDR_A_BS1
107
108
DDR_A_BS1
<6>
A10/AP
BA1
C411
C411
C416
C416
DDR_A_BS0
DDR_A_RAS#
109
110
<6> DDR_A_BS0
DDR_A_RAS#
<6>
BA0
RAS#
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
111
112
VDD13
VDD14
DDR_A_WE#
DDRA_CS0_DIMMA#
113
114
<6> DDR_A_WE#
DDRA_CS0_DIMMA#
<6>
WE#
S0#
DDR_A_CAS#
SA_ODT0
R267
R267
115
116
<6> DDR_A_CAS#
SA_ODT0 <6>
CAS#
ODT0
C408
C408
1K_0402_5%
1K_0402_5%
117
118
VDD15
VDD16
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C404
C404
DDR_A_MA13
SA_ODT1
119
120
SA_ODT1 <6>
A13
ODT1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRA_CS1_DIMMA#
121
122
<6> DDRA_CS1_DIMMA#
S1#
NC2
123
124
VDD17
VDD18
+VREF_CA
125
126
NCTEST
VREF_CA
127
128
VSS27
VSS28
DDR_A_D32
DDR_A_D36
129
130
DQ32
DQ36
DDR_A_D33
DDR_A_D37
+0.75VS
131
132
DQ33
DQ37
133
134
R266
R266
1
1
VSS29
VSS30
DDR_A_DQS#4
DDR_A0_DM4
1K_0402_5%
1K_0402_5%
135
136
DQS#4
DM4
B
DDR_A_DQS4
B
137
138
DQS4
VSS31
DDR_A_D38
139
140
VSS32
DQ38
2
2
DDR_A_D34
DDR_A_D39
141
142
1 1
1 1
DQ34
DQ39