A

Compal confidential

Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_GM/PM+ICH7-M core logic

2005-12-15
REV:1.0

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom LA-2841
Date:

Rev
1.0

Thursday, December 15, 2005

Sheet
E

of

60

Compal confidential
File Name : LA-2841
ZZZ

Mobile Yonah
uFCBGA-479/uFCPGA-478 CPU

Thermal Sensor
ADM1032

PCB

VRAM
128/256MB

page 4
page 4, 5, 6

page 22,23,24,25

Fan Control

H_A#(3..31)

page 4

Nvidia
NV71/72M

Clock Generator
ICS 954306

FSB

H_D#(0..63)

533/667MHz

page 15

PCI-E x 16

Intel Calistoga GMCH

page 18,19,20,21,26

DDR2 -400/533/667

PCBGA 1466
LVDS Panel
Interface
page

DDR2-SO-DIMM X2
BANK 0, 1, 2, 3

page 13,14

Dual Channel

page 7, 8, 9, 10,11,12

16

Mini-PCIE Card

CRT & TV OUT

page 17

New Card
Connector
x2
page 34

PCIE x3
USB2.0

Intel ICH7-M

LAN I/F

page 37

DMI

AC-LINK

mBGA-652

PCI BUS

3.3V 33 MHz

page 27, 28, 29, 30

USB conn X3
page 41

10/100 LAN

CardBus Controller
TI PCI7412

page 35

BT Conn

LPC BUS

page 32

page 41

Audio CKT
AMOM page

RTC CKT.
RJ45 CONN

page 29

page 35

Slot 0

13 94

page 33

page 32

Card reader

ENE KB910/L

page 32

page 40

SATA HDD
Connector x2

SPR CONN.

Int.KBD

*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DC JACK
*TVOUT CONN
*USB CONN x1
*CIR x1

page 42

page 42

Power On/Off CKT.

BIOS

page 42

39

38

page 31

Touch Pad

AMP & Audio Jack

page 44

MO DEM
AMOM page

PATA CDROM
Connector
page 45

page 31

DC/DC Interface CKT.

page 47

page 46

Power Circuit DC/DC

Compal Secret Data

Security Classification
2005/03/10

Issued Date

page 48~56

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Block Diagram

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

E

of

60

Voltage Rails
+5VS
+3VS

power
plane

+2.5VS
+1.8VS

+B
LDO3

+5VALW

+1.8V

LDO5

+3VALW

+5V

+1.5VS
+1.2VS
+VGA_CORE
+0.9VS

State

+CPU_CORE
+VCCP

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

O MEANS ON
X MEANS OFF

PCI Devices
EXTERNAL

IDSEL#

CARD BUS & 1394

AD22

REQ/GNT#
2

PIRQ
C,D,E,G

Load BOM check item

1.U31 GM/PM/GML part number
2.U6 ICH7 part number
3.VRAM part number and Page26 RAM_CFG[0:3]/PCI_DEVID[0:3] modify check
4.For NV73 R510/R75/R533/R168 change to 499ohm
5.U33 NV7x part number

Compal Secret Data

Security Classification
2005/03/10

Issued Date

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Notes List

Size Document Number

Custom LA-2841
Date:

Thursday, December 15, 2005

Rev
1.0
Sheet

of

60

+VCCP
This shall place near CPU
R6
56_0402_5%
1
2

ITP_TDI
H_D#[0..63] <7>

JP16A

L2
V4

ADSTB0#
ADSTB1#

CLK_CPU_BCLK A22
CLK_CPU_BCLK# A21

<15> CLK_CPU_BCLK
<15> CLK_CPU_BCLK#

<7>
<7>
<7>
<7>
<7>
<7>
R17
<7>
56_0402_5%
<7>
1
2
<7>
<7>

+VCCP

<7>

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRD Y#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_RESET#

H_RS#[0..2]

<7>

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

<29> ITP_DBRESET#
<7>
H_DBSY#
<28> H_DPSLP#
<28,53> H_DPRSTP#
<7>
H_DPWR#
<53> H_PROCHOT#
+VCCP

1 R18
2
75_0402_5%
<28> H_PWRGOOD
<7> H_CPUSLP#

R456 1
R455 1

2 @ 1K_0402_5%
51_0402_5%
2

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

F3
F4
G3
G2

RS0#
RS1#
RS2#
TRDY#

AD4
AD3
AD1
AC4

BPM0#
BPM1#
BPM2#
BPM3#

HOST CLK

CONTROL

ITP_DBRESET# C20
H_DBSY#
E1
H_DPSLP#
B5
H_DPRSTP#
E5
H_DPWR#
D24
ITP_BPM#4
AC2
ITP_BPM#5
AC1
H_PROCHOT# D21

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

H_PW RGOOD D6
H_CPUSLP#
D7
ITP_TCK
AC5
ITP_TDI
AA6
ITP_TDO
AB3
TEST1
C26
TEST2
D25
ITP_TMS
AB5
ITP_TRST#
AB6

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

H_THERMDA
A24
H_THERMDC
A25
H_THERMTRIP# C7

<7,28> H_THERMTRIP#

BCLK0
BCLK1

H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil

R181 1

R3

56_0402_5%

ITP_TDO

R2

56_0402_5%

ITP_BPM#5

R1

56_0402_5%

ITP_TRST#

R4

56_0402_5%

ITP_TCK

R5

56_0402_5%

2 @ 200_0402_5%

PAD T27

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

PAD
PAD
PAD
PAD
PAD

T5
T4
T3
T1
T2

Thermal Sensor ADM1032AR

+3VS

C598
0.1U_0402_16V4Z

1
U30

C592
2

VDD

SCLK

EC_SMC_2

H_THERMDA

D+

SDATA

EC_SMD_2

H_THERMDC

D-

ALERT#

THERM#

GND

2200P_0402_50V7K

THERM#

+3VS

ADM1032AR_SOP8

10K_0402_5%

Address:100_1100

MISC

J26
M26
V23
AC20

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

H23
M24
W24
AD23
G22
N25
Y25
AE24

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

FAN control

+5VS

C765 1

2 10U_1206_16V4Z

U40
1
2
3
4

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

<7>
<7>
<7>
<7>

<44>

EN_FAN1

VEN
VIN
VO
VSET

8
7
6
5

GND
GND
GND
GND

G993P1UF_SOP8
B

H_DSTBN#[0..3] <7>

+5VS

H_DSTBP#[0..3] <7>

+3VS

R551
10K_0402_5%

1SS355_SOD323
D28
FAN1
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

A6
A5
C4
B3
C6
B4

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

STPCLK#
SMI#

D5
A3

H_STPCLK#
H_SMI#

LEGACY CPU

THERMAL
THERMDA DIODE
THERMDC
THERMTRIP#

H_A20M# <28>
H_FERR# <28>
H_IGNNE# <28>
H_INIT# <28>
H_INTR
<28>
H_NMI
<28>

1
D22
BAS16_SOT23

H_STPCLK# <28>
H_SMI#
<28>

FOX_PZ47903-2741-42_YONAH

<44> FAN_SPEED1

JP30
1
2
3
ACES_85205-0300

C762
1000P_0402_50V7K

+VCCP

EC_SMC_2
EC_SMD_2

<44> EC_SMC_2
<44> EC_SMD_2

FAN1
DINV0#
DINV1#
DINV2#
DINV3#

R458

H_ADSTB#0
H_ADSTB#1

ITP_DBRESET#

ITP_TMS

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

C763 10U_0805_10V4Z

K3
H2
K2
J3
L5

DATA GROUP

ADDR GROUP

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

C761
1000P_0402_50V7K

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

YONAH

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

<7> H_ADSTB#0
<7> H_ADSTB#1

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

<7> H_REQ#[0..4]

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_A#[3..31]

<7>

+VCCP
R437
H_DPSLP# 1

@ 56_0402_5%

@ 56_0402_5%
R436
H_DPRSTP# 1
2

2 2

R457

1 OCP#
Q35
@ MMBT3904_SOT23
5

OCP#

Compal Secret Data

Security Classification
2005/03/10

Issued Date

@ 56_0402_5%

H_PROCHOT# 3

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<29>

Title

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

of

60

+VCCP

2
1

R442
100_0402_1%
2

R441
100_0402_1%
1
2

VCCSENSE

+1.5VS

C586
0.01U_0402_16V7K

R454
1K_0402_1%

VSSSENSE

R451
2K_0402_1%

Close to CPU pin AD26

within 500mils.

C587
10U_0805_10V4Z

+CPU_CORE

JP16B
AF7
AE7

VCCSENSE
VSSSENSE

B26

VCCA

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

H_PSI#

AE6

PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD6
AF5
AE5
AF4
AE3
AF2
AE2

VID0
VID1
VID2
VID3
VID4
VID5
VID6

Close to CPU pin

within 500mils.

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

166

H_PSI#

<53>
<53>
<53>
<53>
<53>
<53>
<53>

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD26

V_CPU_GTLREF
<15> CPU_BSEL0
<15> CPU_BSEL1
<15> CPU_BSEL2

R438
54.9_0402_1%
2
1

R439
27.4_0402_1%
2
1

R452
54.9_0402_1%
2
1

GTLREF

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

B22
B23
C21

BSEL0
BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

R26
U26
U1
V1

COMP0
COMP1
COMP2
COMP3

+CPU_CORE

R453
27.4_0402_1%
2
1

JP16C
D

VCCSENSE
VSSSENSE

+VCCP

<53>

+CPU_CORE

Length match within 25 mils

The trace width 18 mils space
<53> VCCSENSE
7 mils
<53> VSSSENSE

V_CPU_GTLREF

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7

FOX_PZ47903-2741-42_YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUND

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FOX_PZ47903-2741-42_YONAH

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

of

60

+CPU_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

1
C13
10U_0805_6.3V6M

1
C14
10U_0805_6.3V6M

1
C28
10U_0805_6.3V6M

1
C23
10U_0805_6.3V6M

1
C34
10U_0805_6.3V6M

1
C18
10U_0805_6.3V6M

1
C19
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

+CPU_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

1
C33
10U_0805_6.3V6M

1
C39
10U_0805_6.3V6M

1
C42
10U_0805_6.3V6M

1
C35
10U_0805_6.3V6M

1
C38
10U_0805_6.3V6M

1
C41
10U_0805_6.3V6M

1
C2
10U_0805_6.3V6M

C48
10U_0805_6.3V6M

+CPU_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

1
C40
10U_0805_6.3V6M

1
C32
10U_0805_6.3V6M

1
C27
10U_0805_6.3V6M

1
C22
10U_0805_6.3V6M

1
C16
10U_0805_6.3V6M

1
C11
10U_0805_6.3V6M

1
C36
10U_0805_6.3V6M

C31
10U_0805_6.3V6M

+CPU_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

1
C26
10U_0805_6.3V6M

1
C21
10U_0805_6.3V6M

1
C15
10U_0805_6.3V6M

1
C10
10U_0805_6.3V6M

1
C1
10U_0805_6.3V6M

1
C6
10U_0805_6.3V6M

1
C24
10U_0805_6.3V6M

C12
10U_0805_6.3V6M

Mid Frequence Decoupling

1
+
2

1
+
2

1
+
2

1
+
2

@ C578
820U_E9_2_5V_M_R7

C585
@330U_V_2.5VK_R9

C584
330U_V_2.5VK_R9

C576
330U_V_2.5VK_R9

@ C583
820U_E9_2_5V_M_R7

@ C8
330U_V_2.5VK_R9

C47
330U_V_2.5VK_R9

South Side Secondary

C37
330U_V_2.5VK_R9

+CPU_CORE

ESR <= 1.5m ohm

Capacitor > 1980uF

1
+

North Side Secondary

2
B

+VCCP

1
C591
220U_D2_4VM

+
2

1
C43
0.1U_0402_16V4Z

1
C44
0.1U_0402_16V4Z

1
C45
0.1U_0402_16V4Z

1
C3
0.1U_0402_16V4Z

1
C4
0.1U_0402_16V4Z

C5
0.1U_0402_16V4Z

Place these inside

socket cavity on L8
(North side
Secondary)

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

CPU Bypass capacitors

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

of

60

R462
54.9_0402_1%
2
1

R464
24.9_0402_1%
2
1

R466
24.9_0402_1%
2
1

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

<29>
<29>
<29>
<29>

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

<29>
<29>
<29>
<29>

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

<29>
<29>
<29>
<29>

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

HADSTB#0
HADSTB#1

B9
C13

H_ADSTB#0
H_ADSTB#1

HCLKN
HCLKP

AG1
AG2

CLK_MCH_BCLK#
CLK_MCH_BCLK

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

J7
W8
U3
AB10

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRD Y#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

HRS0#
HRS1#
HRS2#

B4
E6
D6

H_RS#0
H_RS#1
H_RS#2

<13>
<13>
<14>
<14>
H_ADSTB#0 <4>
H_ADSTB#1 <4>

H_DSTBP#[0..3] <4>

<13>
<13>
<14>
<14>

+1.8V

R41

<4>
<4>
<4>
<4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT#
<4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
T17
T11

R40
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

<13>
<13>
<14>
<14>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

1
1

PAD
PAD

M_ODT0
M_ODT1
M_ODT2
M_ODT3
2 80.6_0402_1%
2
80.6_0402_1%

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AE35
AF39
AG35
AH39

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AC35
AE39
AF35
AG39

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AE37
AF41
AG37
AH41

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AC37
AE41
AF37
AG41

DMITXP0
DMITXP1
DMITXP2
DMITXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

AY35
AR1
AW7
AW40

SM_CK0
SM_CK1
SM_CK2
SM_CK3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

AW35
AT1
AY7
AY40

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

AU20
AT20
BA29
AY29

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

DDR_CS0_DIMMA# AW13
DDR_CS1_DIMMA# AW12
DDR_CS2_DIMMB# AY21
DDR_CS3_DIMMB# AW21

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

AL20
AF10

SM_OCDCOMP0
SM_OCDCOMP1

BA13
BA12
AY20
AU21

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

AV9
AT9
AK1
AK41

PM_BMBUSY#
G28
<29> PM_BMBUSY#
PM_EXTTS#0
F25
<13,14> PM_EXTTS#0
DPRSLPVR
H26
<29,53> DPRSLPVR
H_THERMTRIP#
G6
<4,28> H_THERMTRIP#
ICH_POK
AH33
<29,44> ICH_POK
PLTRST_R#
AH34
2
1
R98
100_0402_1%
K28
<27> MCH_ICH_SYNC#

D_REF_CLKN
D_REF_CLKP
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#

M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN

M_OCDOCMP0
M_OCDOCMP1

V_DDR_MCH_REF

<27,31,32,34,37> PLT_RST#

CFG

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

<13>
<13>
<14>
<14>

H_REQ#[0..4] <4>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HDINV#0
HDINV#1
HDINV#2
HDINV#3

<29>
<29>
<29>
<29>

<13>
<13>
<14>
<14>

D8
G8
B8
F8
A8

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

Description at page15.

U31B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

CLK

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

SM_RCOMPN
SM_RCOMPP

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
ICH_SYNC#

CALISTOGA_FCBGA1466~D

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5
CFG6
PAD
CFG7
CFG8
PAD
CFG9
CFG10
PAD
CFG11
CFG12
CFG13
CFG14
PAD
CFG15
PAD
CFG16
CFG17
PAD
CFG18
CFG19
CFG20

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>
MCH_CLKSEL2 <15>
T6
T9
CFG5
<11>
T7
CFG7
<11>
T12
CFG9
<11>
T10
CFG11
<11>
CFG12
<11>
CFG13
<11>
T8
T16
CFG16
<11>
T14
CFG18
<11>
CFG19
<11>
CFG20
<11>

AG33 CLK_MCH_3GPLL
AF33 CLK_MCH_3GPLL#
A27
A26

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK

CLK_MCH_DREFCLK# <15>
CLK_MCH_DREFCLK <15>

C40 MCH_SSCDREFCLK#
D41 MCH_SSCDREFCLK

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

SM_VREF0
SM_VREF1

PM

J13
H_VREF
K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
H_SWNG0
E4
H_SWNG1 W1

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

DDR MUXING

+VCCP

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DMI

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

H_A#[3..31] <4>

U31A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

R461
54.9_0402_1%
2
1

NC

H_D#[0..63]

HOST

<4>

RESERVED

MCH_SSCDREFCLK# <15>
MCH_SSCDREFCLK <15>

CLKREQB#

CLKREQB# <15>

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

H_RS#[0..2] <4>
+1.8V
1

CALISTOGA_FCBGA1466~D

R483

1
R463

221_0603_1%

1
R38
2

221_0603_1%

100_0402_1%

2
1

PM_EXTTS#0

R71
10K_0402_5%
2
1

DPRSLPVR

R79
@ 10K_0402_5%
1
2
A

H_SWNG1

0.1U_0402_16V4Z
C601

1
R465
2

100_0402_1%

0.1U_0402_16V4Z
C82

1
R37
2

100_0402_1%

0.1U_0402_16V4Z

C87

2
1
R42
2

H_SWNG0

100_0402_1%

H_VREF
200_0402_1%

R45

+VCCP

R481

+VCCP

V_DDR_MCH_REF
C663
0.1U_0402_16V4Z

<13,14> V_DDR_MCH_REF

+VCCP

+3VS

100_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Calistoga (1/6)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Friday, December 16, 2005

1

of

60

<13> DDR_A_DQS[0..7]

<13> DDR_A_DQS#[0..7]

<13> DDR_A_MA[0..13]

AU12
AV14
BA20

SA_BS0
SA_BS1
SA_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AY13
AW14
AY14
AK23
AK24

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

U31E
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR SYS MEMORY A

<13> DDR_A_DM[0..7]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

<13> DDR_A_CAS#
<13> DDR_A_RAS#
<13> DDR_A_WE#
T18 PAD
T19 PAD

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13>
<14> DDR_B_BS#0
<14> DDR_B_BS#1
<14> DDR_B_BS#2
<14> DDR_B_DM[0..7]

<14> DDR_B_DQS[0..7]

<14> DDR_B_DQS#[0..7]

<14> DDR_B_MA[0..13]

<14> DDR_B_CAS#
<14> DDR_B_RAS#
<14> DDR_B_WE#
T13 PAD
T15 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AT24
AV23
AY28

SB_BS0
SB_BS1
SB_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

AR24
AU23
AR27
AK16
AK18

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

DDR SYS MEMORY B

U31D
<13> DDR_A_BS#0
<13> DDR_A_BS#1
<13> DDR_A_BS#2

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D[0..63] <14>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

CALISTOGA_FCBGA1466~D

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Calistoga (2/6)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Friday, December 16, 2005

1

of

60

U31C

<16> LVDSA0<16> LVDSA1<16> LVDSA2-

<16> LVDSB0<16> LVDSB1<16> LVDSB2<16> LVDSAC+

<16> LVDSAC<16> LVDSBC+
<16> LVDSBCC

LA_DATA0
LA_DATA1
LA_DATA2

LVDSA0LVDSA1LVDSA2-

C37
B35
A37

LA_DATA#0
LA_DATA#1
LA_DATA#2

LVDSB0+
LVDSB1+
LVDSB2+

F30
D29
F28

LB_DATA0
LB_DATA1
LB_DATA2

LVDSB0LVDSB1LVDSB2-

G30
D30
F29

LB_DATA#0
LB_DATA#1
LB_DATA#2

LVDSAC+
LVDSACLVDSBC+
LVDSBC-

A32
A33
E26
E27

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

A16
C18
A19

TVDAC_A
TVDAC_B
TVDAC_C

EDID_CLK_LCD
EDID_DAT_LCD
GMCH_LVDDEN
2
1
R482 1.5K_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA
2 R58
1
4.99K_0402_1%

<17> CRT_VSYNC
<17> CRT_HSYNC
<17> CRT_B

<17> CRT_G
<17> CRT_R

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

J29
K30

TV_DCONSEL1
TV_DCONSEL0

3VDDCCL
3VDDCDA

C26
C25

DDCCLK
DDCDATA

CRT_VSYNC
CRT_HSYNC
CRT_B

H23
G23
E23
D23
C22
B22
A21
B21

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

J22

CRT_IREF

CRT_G
CRT_R

2 R65
1
255_0402_1%

CRT

<17> 3VDDCCL
<17> 3VDDCDA

J20
B16
B18
B19

TV

<17> TV_COMPS
<17> TV_LUMA
<17> TV_CRMA

B37
B34
A36

GMCH_ENBKL

<16> GMCH_ENBKL

<16> EDID_CLK_LCD
<16> EDID_DAT_LCD
<16> GMCH_LVDDEN

LVDSA0+
LVDSA1+
LVDSA2+

+1.5VS_PCIE
R89
24.9_0402_1%
2
PEG_RXP[0..15] <18>

D40
D38

PEGCOMP

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

C231
C661
C230
C659
C228
C657
C237
C655
C238
C653
C239
C651
C250
C649
C677
C648

G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

C229
C662
C232
C660
C233
C658
C234
C656
C235
C654
C236
C652
C249
C650
C678
C664

G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@
G71@

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

EXP_COMPI
EXP_COMPO

LVDS

<16> LVDSB0+
<16> LVDSB1+
<16> LVDSB2+

SDVOCTRL_DATA
SDVOCTRL_CLK

PCI-EXPRESS GRAPHICS

<16> LVDSA0+
<16> LVDSA1+
<16> LVDSA2+

H27
H28

PEG_RXN[0..15] <18>

PEG_M_TXP[0..15] <18>

PEG_M_TXN[0..15] <18>

CALISTOGA_FCBGA1466~D

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Calistoga (3/6)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Friday, December 16, 2005

1

of

60

+VCCP

+2.5VS

D5
D

H20
G20

+3VS_TVBG

C225
0.1U_0402_16V4Z

VCCA_TVBG
VSSA_TVBG

10U_1206_6.3V6M

+1.5VS_MPLL

10U_1206_6.3V6M
C665

AF2

220U_D2_4VM
C666

VCCA_MPLL

CRTDAC: Route caps within

250mil of Alviso. Route FB
within 3" of Calistoga

1
+

+1.5VS

L29
MBK160808_0603
2
1

1
+

+1.5VS

close pin A38

2
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+1.5VS_TVDAC
+3VS

2
B

PCI-E/MEM/PSB PLL decoupling

+1.5VS

+1.5VS_3GPLL

R99
0_0603_5%
2
1

+1.5VS

+1.5VS_MPLL

R459
0_0603_5%
2
1

45mA Max.
1
C604

CALISTOGA_FCBGA1466~D

+1.5VS_TVDAC

+1.5VS_HPLL
+1.5VS

+1.5VS

R46
0_0603_5%
2
1

C105
0.1U_0402_16V4Z

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

+3VS

R460
0_0603_5%
2
1

45mA Max.
1

+1.5VS

10U_1206_6.3V6M

VCCHV0
VCCHV1
VCCHV2

A23
B23
B25

R39
2
1
0_0805_5%

1
C594

D21
H19

+3VS_TVBG

0.1U_0402_16V4Z

VCCD_TVDAC
VCCDQ_TVDAC

+1.5VS

C614
2200P_0402_50V7K

A28
B28
C28

C605

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

C113
0.1U_0402_16V4Z

AH1
AH2

C280
0.1U_0402_16V4Z

VCCD_HMPLL0
VCCD_HMPLL1

+3VS
R44
2
1
0_0805_5%
C106
0.1U_0402_16V4Z

+3VS_TVDACC

+3VS_TVDACA
C107
2200P_0402_50V7K

1
2

+3VS
R55
2
1
0_0805_5%
C109
0.1U_0402_16V4Z

+3VS_TVDACB
C114
2200P_0402_50V7K

+3VS_TVDACB

+3VS
R52
2
1
0_0805_5%
C111
0.1U_0402_16V4Z

+3VS_TVDACA

+3VS_TVDACC

C110
2200P_0402_50V7K

E19
F19
C20
D20
E20
F20

C215
0.1U_0402_16V4Z

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

10U_1206_6.3V6M

+1.5VS

+2.5VS

close pin G41

+1.5VS_DPLLB

L28
MBK160808_0603
2
1

+2.5VS

P O W E R

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

A38
B39

C248
10U_1206_6.3V6M

VCCA_LVDS
VSSA_LVDS

+1.5VS_DPLLA

C593

C596
0.47U_0603_10V7K
MCH_AB1

MCH_D2

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

2
L7 BLM11A601S_0603
1
2
+2.5VS

0.1U_0402_16V4Z

1
C597
0.22U_0603_10V7K

C81
0.22U_0603_10V7K

B26
C39
AF1

C174
0.1U_0402_16V4Z

C607
0.47U_0603_10V7K

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

+2.5VS

C160
0.01U_0402_16V7K

C613
2.2U_0805_16V4Z

C612
4.7U_0805_10V4Z

+2.5VS_CRTDAC

UMA@ C645

MCH_A6

E21
F21
G21

330U_V_2.5VK_R9
C226

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

0.1U_0402_16V4Z

+1.5VS_3GPLL
+2.5VS

UMA@ C616

AC33
G41
H41

+1.5VS

330U_V_2.5VK_R9
C138

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

R490
0_0805_5%
2
1

0.1U_0402_16V4Z

@ 10_0402_5%

AB41
AJ41
L41
N41
R41
V41
Y41

C117
0.1U_0402_16V4Z

+1.5VS_PCIE

W=40 mils

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

C112
2200P_0402_50V7K

+2.5VS

C116
0.1U_0402_16V4Z

+3VS

B30
C30
A30

C115
2200P_0402_50V7K

1 1

@ CH751H-40_SC76

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

1
2
C162
0.1U_0402_16V4Z

C682

C610
220U_D2_4VM

D19

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

H22

C615
10U_1206_6.3V6M

2
2

+1.5VS

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

VCC_SYNC

C124
0.1U_0402_16V4Z

+2.5VS

R80
@ 10_0402_5%

R520

U31H

+VCCP

C163
0.1U_0402_16V4Z

1 1

@ CH751H-40_SC76

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Calistoga (4/6)

Size Document Number

Custom LA-2841
Date:

Re v
1.0

Friday, December 16, 2005

Sheet
1

10

of

60

Strap Pin Table

CFG[3:17] have internal pull up

C606
@ 220U_D2_4VM

C595
@ 220U_D2_4VM

1
+
2

1
+
2

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+VCCP

CALISTOGA_FCBGA1466~D

C602
0.47U_0603_10V7K

+1.8V
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

C603
0.47U_0603_10V7K

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16

Place near pin AV1 & AJ1

CFG[19:18] have internal pull down

MCH_AT41
MCH_AM41

011
001

C668
0.47U_0603_10V7K

CFG[2:0]

CFG5
CFG7

0 = Reserved
1 = Mobile Yonah CPU*(Default)

CFG9

0 = Lane Reversal Enable

1 = Normal Operation (Default)*

CFG6

0 = Reserved

Place near pin AT41 & AM41

C84

0.1U_0402_16V4Z

C128

0.1U_0402_16V4Z

C83
2

0.1U_0402_16V4Z

=
=
=
=

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation *(Default)

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled *(Default)

CFG16
1

1 = Calistoga
00
01
10
11

CFG[13:12]

= 667MT/s FSB
= 533MT/s FSB

0 = DMI x 2
1 = DMI x 4 *(Default)

PSB 4X CLK Enable

0.1U_0402_16V4Z

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

C669
0.47U_0603_10V7K

C85
0.22U_0603_10V7K

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

10 = 1.05V*(Default)
01 = 1.5V

CFG10 CFG18

0 = Normal Operation * (Default)

1 = DMI Lane Reversal Enable

CFG19

0 = No SDVO Device Present *

(Default)

SDVO_CTRLDATA

1 = SDVO Device Present

CFG20
(PCIE/SDVO select)

0 = Only PCIE or SDVO is

operational. *(Default)
1 = PCIE/SDVO are operating
simu.

Place near pin BA23

C599
330U_V_2.5VK_R9

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

C641
10U_1206_6.3V6M

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

C222

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C125
0.47U_0603_10V7K

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

+1.8V

U31G

C609
10U_1206_6.3V6M

C139
1U_0603_10V4Z

C164
0.22U_0603_10V7K

C600
10U_1206_6.3V6M

C173
10U_1206_6.3V6M

C86
0.22U_0603_10V7K

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18

+VCCP

+1.5VS

1
+

<7>

CFG5

<7>

CFG7

<7>

CFG9

<7>

CFG11

<7>

CFG12

<7>

CFG13

<7>

CFG16

R48

2 @

2.2K_0402_5%

R54

2 @

2.2K_0402_5%

R51

2 @

2.2K_0402_5%

R47

2 @

2.2K_0402_5%

R49

2 @

2.2K_0402_5%

R50

2 @

2.2K_0402_5%

R53

2 @

2.2K_0402_5%

+3VS
C104
0.47U_0603_10V7K

U31F

+VCCP

<7>
<7>
<7>

R74
R82
R87

CFG18
CFG19
CFG20

2 @ 1K_0402_5%
2 @ 1K_0402_5%
2 @ 1K_0402_5%

1
1
1

Place near pin BA15

CALISTOGA_FCBGA1466~D
A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Calistoga (5/6)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Friday, December 16, 2005

1

11

of

60

U31I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

U31J

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

CALISTOGA_FCBGA1466~D

CALISTOGA_FCBGA1466~D
A

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Calistoga (6/6)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Friday, December 16, 2005

1

12

of

60

+1.8V

+1.8V
V_DDR_MCH_REF

<8> DDR_A_DQS#[0..7]

Layout Note:
Place near JP41

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D9
DDR_A_D15

+1.8V

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_D16
DDR_A_D17

C187

C193

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C143

0.1U_0402_16V4Z

C180

C206

0.1U_0402_16V4Z

C204

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C131

2.2U_0805_16V4Z

C129

2.2U_0805_16V4Z

C130

2.2U_0805_16V4Z

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27

<7> DDR_CKE0_DIMMA
<8> DDR_A_BS#2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

<8> DDR_A_BS#0
<8> DDR_A_WE#

+0.9VS

<8> DDR_A_CAS#
<7> DDR_CS1_DIMMA#

M_ODT1

DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

C628

C136

C145

C158

C629

C630

C166

C175

C192

C639

C640

C642

C643

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7>

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_D35
DDR_A_D32
DDR_A_D40
DDR_A_D44

DDR_A_DM5
DDR_A_D41
DDR_A_D46
DDR_A_D49
DDR_A_D48
+0.9VS

DDR_A_MA5
DDR_A_MA8

RP25
1
2

DDR_A_MA1
DDR_A_MA3

RP24 56_0404_4P2R_5% RP15 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA7
2
3
3
2 DDR_A_MA6

4
3

Layout Note:
Pla ce these resistor
closely JP41,all
trace length Max=1.5"

RP27 56_0404_4P2R_5%
4
1 DDR_A_BS#2
3
2 DDR_CKE0_DIMMA

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
DDR_A_D61
DDR_A_D60
DDR_A_DM7

RP6 56_0404_4P2R_5% RP26 56_0404_4P2R_5%

DDR_A_RAS#
1
4
4
1 DDR_A_MA9
DDR_CS0_DIMMA# 2
3
3
2 DDR_A_MA12
DDR_A_BS#0
DDR_A_MA10

RP23 56_0404_4P2R_5% RP12 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA4
2
3
3
2 DDR_A_MA2

DDR_A_CAS#
DDR_A_WE#

RP22 56_0404_4P2R_5% RP9

1
4
4
2
3
3

56_0404_4P2R_5%
1 DDR_A_MA0
2 DDR_A_BS#1

RP21 56_0404_4P2R_5% RP3

DDR_CS1_DIMMA# 2
3
4
M_ODT1
1
4
3

56_0404_4P2R_5%
1 M_ODT0
2 DDR_A_MA13

DDR_A_D59
DDR_A_D58
<14,15> CLK_SMBDATA
<14,15> CLK_SMBCLK

CLK_SMBDATA
CLK_SMBCLK
+3VS
C80
0.1U_0402_16V4Z

56_0404_4P2R_5% RP18 56_0404_4P2R_5%

4
1 DDR_CKE1_DIMMA
3
2 DDR_A_MA11

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

FOX_ASOA426-M4R-TR
CONN@

SO-DIMM A
REVERSE

DDR_A_DM0
DDR_A_D5
DDR_A_D7

DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_A_D11
DDR_A_D10

DDR_A_D20
DDR_A_D21
PM_EXTTS#0 <7,14>

DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA <7>

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>
M_ODT0

<7>

DDR_A_D39
DDR_A_D38
DDR_A_DM4
DDR_A_D34
DDR_A_D33
DDR_A_D45
DDR_A_D43
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

Top side
Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

V_DDR_MCH_REF <7,14>

R35
10K_0402_5%
2
1

DDR_A_D8
DDR_A_D14

DDR_A_D6
DDR_A_D0

R33
10K_0402_5%
2
1

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C369

DDR_A_DQS#0
DDR_A_DQS0

<8> DDR_A_MA[0..13]

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C368

DDR_A_D4
DDR_A_D1

<8> DDR_A_DQS[0..7]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

0.1U_0402_16V4Z

<8> DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

JP21

<8> DDR_A_D[0..63]

Title

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

13

of

60

+1.8V

<8> DDR_B_DQS#[0..7]

+1.8V

<8> DDR_B_D[0..63]

V_DDR_MCH_REF

<8> DDR_B_DM[0..7]

DDR_B_D10
DDR_B_D11

+1.8V

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D17
DDR_B_D20

C140

C141

0.1U_0402_16V4Z

C142

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C169

0.1U_0402_16V4Z

C157

C159

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C205

2.2U_0805_16V4Z

C214

C132

2.2U_0805_16V4Z

2.2U_0805_16V4Z

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31

<7> DDR_CKE2_DIMMB

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

<8> DDR_B_BS#2

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9VS

<8> DDR_B_CAS#
<7> DDR_CS3_DIMMB#
1

<7>

M_ODT3

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33

2
C168

C176

C191

C133

C144

C147

C165

C170

C179

C202

C137

C146

C156

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<8> DDR_B_BS#0
<8> DDR_B_WE#

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43

+0.9VS

DDR_B_MA1
DDR_B_MA3

RP10
1
2

DDR_B_BS#0
DDR_B_MA10

RP7 56_0404_4P2R_5% RP17 56_0404_4P2R_5%

DDR_B_MA11
1
4
4
1
DDR_CKE3_DIMMB
2
3
3
2

DDR_B_BS#1
DDR_B_MA0

RP8 56_0404_4P2R_5% RP13 56_0404_4P2R_5%

DDR_B_MA5
1
4
4
1
DDR_B_MA8
2
3
3
2

4
3

4
3

RP16 56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2

DDR_B_D48
DDR_B_D49

Layout Note:
Pla ce these resistor
closely JP42,all
trace length Max=1.5"

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D56
DDR_B_D61
DDR_B_DM7
DDR_B_D59
DDR_B_D58

RP5 56_0404_4P2R_5% RP14 56_0404_4P2R_5%

DDR_CS2_DIMMB# 1
DDR_B_MA6
4
4
1
DDR_B_RAS#
DDR_B_MA7
2
3
3
2

<13,15> CLK_SMBDATA
<13,15> CLK_SMBCLK

+3VS

DDR_B_CAS#
DDR_B_WE#

56_0404_4P2R_5% RP19
4
3

1
2

C79
0.1U_0402_16V4Z

DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3

DDR_B_D21
DDR_B_D16
PM_EXTTS#0 <7,13>

DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D26
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <7>

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2
DDR_B_MA13

M_ODT2

<7>

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

FOX_ASOA426-M4R-TR
CONN@

SO-DIMM B
STANDARD

R32
1

+3VS

10K_0402_5%
A

Bottom side

DDR_B_BS#2
DDR_CKE2_DIMMB

Compal Secret Data

Security Classification

56_0404_4P2R_5%

2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_D14
DDR_B_D15

R34

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

10K_0402_5%

RP4 56_0404_4P2R_5% RP11 56_0404_4P2R_5%

DDR_B_MA2
1
4
4
1
DDR_B_MA4
2
3
3
2
RP1
56_0404_4P2R_5% RP2 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
DDR_B_MA13
3
4
1
M_ODT3
M_ODT2
1
4
3
2

CLK_SMBDATA
CLK_SMBCLK

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_D12
DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D6
DDR_B_D7

DDR_B_D8
DDR_B_D9

DDR_B_DM0

C367

DDR_B_D2
DDR_B_D3

Layout Note:
Place near JP42

DDR_B_D5
DDR_B_D4

C366

DDR_B_DQS#0
DDR_B_DQS0
D

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1

<8> DDR_B_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2.2U_0805_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<8> DDR_B_DQS[0..7]

V_DDR_MCH_REF <7,13>

JP24

Title

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

Size

Document Number

Rev
1.0

LA-2841
Date:

Sheet

Thursday, December 15, 2005

1

14

of

60

FSLC

FSLB

FSLA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

+3VS

133

100

166

100

33.3

2.2K_0402_5%
Q12
2N7002_SOT23

33.3
<29,34,37> ICH_SMBDATA

Table : ICS954306

2
0_0805_5%

C456

C422

C431

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS

CLK_Ra CLK_Rb CLK_Rc

No Stuff

CLK_Rd CLK_Re CLK_Rf

<29,34,37>

Stuff

CLK_Rd CLK_Re CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

Stuff

CLK_Rd CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

2
0_0805_5%

3
S

2
ICH_SMBCLK

+CK_VDD_48
1

C424
0.1U_0402_16V4Z

2
R237
8.2K_0402_5%
FSA 2
1

0.1U_0402_16V4Z

C417
0.1U_0402_16V4Z

C419 2

CLK_Rd

CLK_48M_ICH
CLK_48M_CB

<29> CLK_48M_ICH
<32> CLK_48M_CB

MCH_CLKSEL0 <7>

2
+CK_VDD_REF
12_0402_5%
1
1 FSA
12_0402_5%
FSB

R236
2
2
R243

R227
1K_0402_5%

<29> CLK_14M_ICH

1
R231
0_0402_5%

CLK_14M_ICH

1 CLKREF1
33_0402_5%

2
R230

2.4K_0402_1%1

X1

57

CLK_XTAL_IN

10

VDD48

X2

56

CLK_XTAL_OUT

VDDPCI

1
2
R305 9LP@ 0_0402_5%
1
2
R311 9LP@ 0_0402_5%

SATACLKT
SATACLKC

29

VDDSRC

CPUCLKT0

52

CPU_BCLK

VDDCPU

CPUCLKC0

51

CPU_BCLK#

CPUCLKT1

49

MCH_BCLK

CPUCLKC1

48

MCH_BCLK#

24

VDDSRC

33

VDDSATA

41
50
55

VDDREF

11

FSLA/USB_48MHz

15

FSLB/TEST_MODE

59

2 R266

CLKIREF

46

<27> CLK_PCI_ICH

R201

61

H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#
CLK_PCI_ICH

2 R229
1
33_0402_5%

PCI_ICH

@ 1K_0402_5%
FSB

MCH_CLKSEL1 <7>

R200
1K_0402_5%

+3VS

<36> CLK_PCI_MINI

CLK_Rb

@ R199

R589

64
18

LCDCLK_SSC/SRCCLKC0

19

IREF

1 R206

PCI_MINI

CPU_STOP#

PCI/SRC_STOP#

SRCCLKT2

22

Vtt_PwrGd#/PD

SRCCLKC2

23

**SEL_LCDCLK#/PCICLK_F1
SATA1/SRCCLKT4

30

SATA1/SRCCLKC4

31

60

REF0/PCICLK1

62

*REQ_SEL/PCICLK2

*SEL_PCI1/PCICLK3

**SEL_SATA1/PCICLK4

10K_0402_5%2

1 R216

<44> CLK_PCI_EC

33_0402_5% 2

1 R215

PCI_EC

<42> CLK_PCI_SIO

@ 33_0402_5% 2

1 R225

PCI_SIO

**SEL_SATA2/PCICLK5

<32> CLK_PCI_PCM

33_0402_5% 2

1 R224

PCI_PCM

PCICLK6

PCI_PCM

<13,14> CLK_SMBDATA
<13,14> CLK_SMBCLK

CLK_SMBDATA

54

SDATA

CLK_SMBCLK

53

SCLK

+VCCP
2

<7> CLK_MCH_DREFCLK
R202

R205
8.2K_0402_5%
CLKREF1 2
1
1
R177
0_0402_5%

<7> CLK_MCH_DREFCLK#

CLK_MCH_DREFCLK 1
R246
CLK_MCH_DREFCLK#1
R253

MCH_DREFCLK
2
UMA@ 10_0402_5%
MCH_DREFCLK#
2
UMA@ 10_0402_5%

13

DOTT_96MHz

14

DOTC_96MHz

@ 1K_0402_5%
2

MCH_CLKSEL2 <7>

0.1U_0402_16V4Z

R184
1K_0402_5%

CLK_MCH_BCLK
2
10_0402_5%
CLK_MCH_BCLK#
2
10_0402_5%
1
@ 10K_0402_5%
CLKREQA#
MCH_SSCDREFCLK
2
UMA@ 10_0402_5%
MCH_SSCDREFCLK#
2
UMA@ 10_0402_5%

PCIE_MCARD 1
R282
PCIE_MCARD#1
R284
PCIE_SATA

CLK_PCIE_MCARD
2
10_0402_5%
CLK_PCIE_MCARD#
2
10_0402_5%

1
R297
PCIE_SATA# 1
R304
2
R226

CLK_PCIE_SATA
2
10_0402_5%
CLK_PCIE_SATA#
2
10_0402_5%
1
@ 10K_0402_5%
CLKREQB#
CLK_PCIE_VGA
2
G71@ 10_0402_5%
CLK_PCIE_VGA#
2
G71@ 10_0402_5%

63
PCIE_VGA

SRCCLKC1

21

PCIE_VGA#
MCH_3GPLL

1
R288
MCH_3GPLL# 1
R292

CLK_MCH_3GPLL
2
10_0402_5%
CLK_MCH_3GPLL#
2
10_0402_5%

PCIE_ICH

CLK_PCIE_ICH
2
10_0402_5%
CLK_PCIE_ICH#
2
10_0402_5%

SRCCLKT3

26

SRCCLKC3

27

SATA2/SRCCLKT5

35

SATA2/SRCCLKC5

34

*CPUCLKT2_ITP/CLKREQC#

45
37
36

GND

SRCCLKT8

43

17

GND

SRCCLKC8

42

58

GND

47

GNDCPU

*CPUCLKC2_ITP/CLKREQD#

44

GND

1
R254
1
R258

20

SRCCLKT6

12

CLK_CPU_BCLK
2
10_0402_5%
CLK_CPU_BCLK#
2
10_0402_5%

SSCDREFCLK 1
R257
SSCDREFCLK#1
R270

1
R268
1
R276

Place crystal within

500 mils of CK410

Place near U54

Place these components
near each pin within 40
mils.

22P_0402_50V8J

SRCCLKT1

SRCCLKC6

*CLKREQB#

1
1

CLK_Rc

@ R183

CLK_Rf
LCD clock select

Pin44/45 function select

+3VS
1

+3VS

R235

25

GNDSRC

SRCCLKT7

39

+3VS

40

GNDSRC

SRCCLKC7

38

0_0402_5%

1
R294
PCIE_ICH#
1
R301

CLKREQC#
2
1
R273
10K_0402_5%
CPU_XDP
CLK_CPU_XDP
1
2
R278
@
10_0402_5%
PCIE_NC1
CLK_PCIE_NC1
1
2
R285 17@ 10_0402_5%
PCIE_NC1#
CLK_PCIE_NC1#
1
2
R289 17@ 10_0402_5%

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
+3VS

CLK_CPU_BCLK
2
R240
CLK_CPU_BCLK# 2
R248

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

CLK_MCH_BCLK 2
R255
CLK_MCH_BCLK# 2
R259

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

MCH_SSCDREFCLK 1
R256
MCH_SSCDREFCLK# 1
R269
CLK_PCIE_MCARD 1
R281
CLK_PCIE_MCARD#1
R283
CLK_MCH_3GPLL
1
R287
CLK_MCH_3GPLL#
1
R291
CLK_PCIE_VGA
1
R267
CLK_PCIE_VGA#
1
R275
CLK_PCIE_ICH
1
R295
CLK_PCIE_ICH#
1
R302
CLK_MCH_DREFCLK 1
R245
CLK_MCH_DREFCLK#1
R252
CLK_PCIE_SATA 1
R296
CLK_PCIE_SATA# 1
R303
CLK_CPU_XDP
2
R279
CLK_CPU_XDP#
2
R272
CLK_PCIE_NC1
2
R286
CLK_PCIE_NC1# 2
R290
CLK_PCIE_NC2
1
R318
CLK_PCIE_NC2# 1
R319

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
1
@49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLKREQA# <37>
MCH_SSCDREFCLK <7>
MCH_SSCDREFCLK# <7>
CLK_PCIE_MCARD <37>
CLK_PCIE_MCARD# <37>
CLK_PCIE_SATA <28>
CLK_PCIE_SATA# <28>
+3VS
CLKREQB# <7>
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>
CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>
CLK_PCIE_ICH <29>
CLK_PCIE_ICH# <29>
CLKREQC# <34>

CLK_PCIE_NC1 <34>
CLK_PCIE_NC1# <34>

32

GNDSATA

R233

2
R277
1
R271
PCIE_NC2
1
R309
PCIE_NC2#
1
R310
CPU_XDP#

CLKREQD#
10K_0402_5%
CLK_CPU_XDP#
@ 10_0402_5%
CLK_PCIE_NC2
2
15.4@ 10_0402_5%
CLK_PCIE_NC2#
2
15.4@ 10_0402_5%
1

CLKREQD# <34>

CLK_PCIE_NC2 <34>

CLKREQA# C802 1

2 1000P_0402_50V7K

CLK_PCIE_NC2# <34>

CLKREQB# C803 1

2 1000P_0402_50V7K

CLKREQC# C804 1

2 1000P_0402_50V7K

CLKREQD# C805 1

2 1000P_0402_50V7K

R312
ICS954306_TSSOP64

10K_0402_5%
PCI_MINI

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor

PCI_ICH

CLK_ENABLE#

@ 10K_0402_5%
2

10K_0402_5%
2

R308

10K_0402_5%

@ 10K_0402_5%

2005/03/10

Issued Date

High:Pin18/19 = 100MHz

*Low:Pin18/19 = 96MHz
5

High:Pin44/45 = CLKREQ

*Low:Pin44/45 = CPUCLK2_ITP
4

Compal Secret Data

Security Classification

R238

CPU_BSEL2

*CLKREQA#
LCDCLK_SST/SRCCLKT0

1
R239
1
R247

2
R218

FSLC/TEST_SEL/REF1

100K_0402_5%
2

0_0402_5%

CLK_Re

33_0402_5% 2

C421

28

<29> H_STP_CPU#
<29> H_STP_PCI#
<53> CLK_ENABLE#

+VCCP

1
R191
0_0402_5%

C430

1 22P_0402_50V8J

VDD

R228
@ 1K_0402_5%

CPU_BSEL1

0.1U_0402_16V4Z

2 +CK_VDD_REF
R188
1_0805_1%
1
2 +CK_VDD_48
R187
2.2_0805_1%

Y2
14.31818MHZ_20P_1BX14318BE1A

16

0.1U_0402_16V4Z

CLK_Ra

<5>

10U_0805_10V4Z

C418

U13

@ R232
56_0402_5%

<5>

C416

2N7002_SOT23
Q15

C425

CPU_BSEL0

C441

CLK_SMBCLK

+VCCP

0.1U_0402_16V4Z

1
1

2
G

Stuff

CLK_Re

<5>

1
R174

+3VS

+CK_VDD_MAIN1

667MHz

C450

533MHz

CLK_SMBDATA

2
G

*(Default)

0.1U_0402_16V4Z

+CK_VDD_MAIN2

FSB Frequency Selet:

CPU Driven

C440

2.2K_0402_5%

1
R324

+3VS

R323

+CK_VDD_MAIN1

R299

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.

Clock generator

Size

Document Number

Rev
1.0

LA-2841
Date:

Sheet

Thursday, December 15, 2005

1

15

of

60

LCD Panel & inverter Connector

<44>
<44>

INVT_PWM
DAC_BRIG

EDID_CLK_LCD
EDID_DAT_LCD

<9> EDID_CLK_LCD
<9> EDID_DAT_LCD
+5VS
+3VS
+LCDVDD

+3VS

LVDSAC+ <9>
LVDSAC- <9>

LVDSA1LVDSA1+

LVDSA1- <9>
LVDSA1+ <9>

LVDSBC+
LVDSBC-

R430
4.7K_0402_5%

LVDSBC+ <9>
LVDSBC- <9>

LVDSB1LVDSB1+
LVDSB0+
LVDSB0LVDSB2+
LVDSB2-

LVDSB1LVDSB1+
LVDSB0+
LVDSB0LVDSB2+
LVDSB2-

<9>
<9>
<9>
<9>
<9>
<9>

LVDSA0LVDSA0+
LVDSA2LVDSA2+

<9>
<9>
<9>
<9>

<44>

D17
CH751H-40_SC76
1
2

BKOFF#

DISPOFF#

D16
UMA@ CH751H-40_SC76
1
2

LVDSA0LVDSA0+
LVDSA2LVDSA2+

<9> GMCH_ENBKL

R431
UMA@ 100K_0402_5%
1

INVPWR_B+

LVDSAC+
LVDSAC-

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

R434
1
2 EDID_CLK_LCD
10K_0402_5%
R435
1
2 EDID_DAT_LCD
10K_0402_5%

UMA

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

WL_LED#
DISPOFF#
INVT_PWM
DAC_BRIG

<37,42> WL_LED#

+3VS

JP2

ACES_88107-4000G

B+

WL_LED#
DISPOFF#
INVT_PWM
DAC_BRIG

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

LCD_I2C_CLK_C
LCD_I2C_DAT_C

<18> LCD_I2C_CLK_C
<18> LCD_I2C_DAT_C
+5VS
+3VS
+LCDVDD

INVPWR_B+

INVPWR_B+

LVDS_ACLVDS_AC+

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

LVDS_AC- <18>
LVDS_AC+ <18>

LVDS_A2+
LVDS_A2LVDS_A1+
LVDS_A1LVDS_A0+
LVDS_A0-

LVDS_A2+
LVDS_A2LVDS_A1+
LVDS_A1LVDS_A0+
LVDS_A0-

LVDS_B1LVDS_B1+
LVDS_B2+
LVDS_B2LVDS_B0+
LVDS_B0-

L25

2 FBMA-L10-201209-301LMT

@ L24

2 FBMA-L10-201209-301LMT
1
1
C806
C807

Discrete

JP1

<18>
<18>
<18>
<18>
<18>
<18>

0.1U_0402_16V4Z

68P_0402_50V8K

LVDS_B1- <18>
LVDS_B1+ <18>
LVDS_B2+ <18>
LVDS_B2- <18>
LVDS_B0+ <18>
LVDS_B0- <18>

LVDS_BC+
LVDS_BC-

LVDS_BC+ <18>
LVDS_BC- <18>

ACES_88107-4000G

R429

+3VS
Q33
SI2301BDS_SOT23

+LCDVDD
R428
100K_0402_5%

2N7002_SOT23
Q32

2
G

0.047U_0402_16V4Z

2
G
S

C572

C574

2 R433
1
UMA@ 0_0402_5%

<9> GMCH_LVDDEN

ENVDD

ENVDD

Q31
DTC124EK_SC59

C575
4.7U_0805_10V4Z

C573
4.7U_0805_10V4Z

0.1U_0402_16V4Z

<18>

1 2

100_0402_1%

+5VALW
2

+LCDVDD
1

Issued Date

2005/03/10

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

LVDS Connector
Size Document Number
Custom LA-2841
Date:

Thursday, December 15, 2005

G

Rev
1.0
Sheet

16
H

of

60

+R_CRT_VCC , +CRTVDD (40mils)

+5VS
D1
2
RB411D_SOT23

R15

M_VSYNC

U28
Y

CRT_VSYNC_R

D46

16
17

CLOSE TO JP3
1

2
G71@ 0_0402_5%

3V_DDCDA

R21
2
UMA@ 0_0402_5%

74AHCT1G125GW_SOT353-5

M_DDCCLK <18>

3VDDCDA <9>

R445
3V_DDCCL

2
G

M_DDCDATA <18>

Q34
2N7002_SOT23

2
G
1

R20
2
G71@ 0_0402_5%
R446

CRT_VSYNCRFL
1
2
L26
FBM-L11-160808-800LMT_0603

Q1
2N7002_SOT23

220P_0402_25V8K

3
A

CRT_HSYNCRFL
1
2
L27
FBM-L11-160808-800LMT_0603

74AHCT1G125GW_SOT353-5

+CRTVDD

CRT_HSYNC_R

CRTL_B
1
R443 4.7K_0402_5%

R19

2
UMA@ 0_0402_5%

3VDDCCL <9>

R444
2.2K_0402_5%
2

+3VS

C577

<18>

CRTVSYNC
2
UMA@ 0_0402_5%
R448
1
2
G71@ 0_0402_5%
1

@
Y

<9> CRT_VSYNC

R447
2

220P_0402_25V8K

U29

M_HSYNC

CR THSYNC
2
UMA@ 0_0402_5%
R450
1
2
G71@ 0_0402_5%
1

OE#

<18>

R449
<9> CRT_HSYNC

OE#

C580
1
2
0.1U_0402_16V4Z

CRTB
1

C46

EMI

+5VS

CRTL_G

R16 4.7K_0402_5%

CRT_B

M_SEN#
CRTL_R

C579 10P_0402_50V8K

<9>

CRTG

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

EMI

C581
10P_0402_50V8K

CRT_G

L3
MBK2012800YZF
1
2
L2
MBK2012800YZF
1
2
L1
MBK2012800YZF
1
2

CRTR

C20
10P_0402_50V8K

<9>

R13
2
UMA@ 0_0402_5%
R12
1
2
UMA@ 0_0402_5%
R9
1
2
UMA@ 0_0402_5%

1
JP3
ALLTO_C10510-115A5-L_15P-s

R10
75_0402_5%
1
2

CRT_R

2
2

EMI

C29
10P_0402_50V8K

<9>

C582
0.1U_0402_16V4Z

C7
33P_0402_25V8K

M_BLU

3
2

1.1A_6VDC_FUSE

CRT CONNECTOR

C17
33P_0402_25V8K

M_GRN

<18>

R14
75_0402_5%
1
2

2
G71@ 0_0402_5%
R11
2
G71@ 0_0402_5%
R8
1
2
G71@ 0_0402_5%

C25
33P_0402_25V8K

<18>

C9
10P_0402_50V8K

R7
75_0402_5%
1
2

M_RED

<18>

NZQA5V6AXV5T1_SOT533-5

+CRTVDD
+R_CRT_VCC
F1
1
1

2.2K_0402_5%

R25

M_CRMA

<18>

M_COMP

2
G71@ 0_0402_5%
R30
1
2
G71@ 0_0402_5%
R27
1
2
G71@ 0_0402_5%

TVCRMA
TVCOMPS

TVLUMA

<46>

TVCRMA

<46>

TV-Out Connector
S-Video

TVCOMPS <46>

EMI

R24
<9>

TV_LUMA

2
UMA@ 0_0402_5%

TVLUMA

R31
<9>

TV_CRMA

2
UMA@ 0_0402_5%

TVCRMA

R26

C49
270P_0402_50V7K

C77
270P_0402_50V7K

TVCOMPS
C75
270P_0402_50V7K

2
UMA@ 0_0402_5%

R23
75_0402_5%
2
1

R29
75_0402_5%
2
1

TV_COMPS

R28
75_0402_5%
2
1

<9>

L4
MBC1608121YZF_0603
1
2

LUMA_CL

L6
MBC1608121YZF_0603
1
2

CRMA_CL

L5
MBC1608121YZF_0603
1
2

COMPS_CL

JP17

R22
1

1
2
3
4
5
6
7

C50
330P_0402_50V7K

<18>

TVLUMA

C76
330P_0402_50V7K

M_LUMA

C74
330P_0402_50V7K

<18>

1
2
3
4
5
6
7

GND
GND

8
9

SUYIN_030107FR007G317ZR

TVGND

0_0805_5%

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

CRT & TVout Connector

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

E

17

of

60

U33A
PEG_RXP[0:15]

R56 1
R77 1

2@ 10K_0402_5%
2 10K_0402_5%

AJ11
AK12
AL12
AK11
AL13

C161 1

AM4
2
128@ 0.1U_0402_16V4Z AK3
2
@ 0.1U_0402_16V4Z
XTALIN
U1
XTALOUT
U2

128@ 27MHz_16PF_6P27000126
2

C680
2 128@
22P_0402_50V8J

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_N

LVDS_AC+
LVDS_ACLVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2-

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

LVDS_BC+
LVDS_BCLVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-

PEX_CFG0 <26>

PEX_CFG1
PEX_CFG2

PEX_CFG1 <26>
PEX_CFG2 <26>

1
R101
1
R100

2
MIOA_VDDQ
@ 2K_0402_5%
2
@ 2K_0402_5%

MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT_N

AE4
AD4
AD5

PCI_DEVID3

XTALOUTBUFF

T1

XTALSSIN

2
R496
128@
22_0402_5%

IFPAB_RSET

AH3
2
R88 @ 1K_0402_5%

IFPCD_RSET

2
R90

1
128@ 10K_0402_5%

IFPC_TXC
IFPC_TXC_N
IFPC_TXD0
IFPC_TXD0_N
IFPC_TXD1
IFPC_TXD1_N
IFPC_TXD2
IFPC_TXD2_N
IFPD_TXC
IFPD_TXC_N
IFPD_TXD4
IFPD_TXD4_N
IFPD_TXD5
IFPD_TXD5_N
IFPD_TXD6
IFPD_TXD6_N

DACC_VREF

F3
AE26
AD26
AH31
AH32
T3
F1
M6
J1
K1

ROM_SCLK
ROM_SI
ROM_SO
ROMCS_N

1
R85

128@ R503
2.2K_0402_5%

M_HSYNC <17>
M_VSYNC <17>
M_RED
<17>
M_BLU
<17>
M_GRN
<17>

D+

2128@
124_0402_5%
DACAVREF
1
2
128@ C171
0.01U_0402_16V7K

R504
200_0402_5%
128@ U34
1 VDD
2

D2
128@ C683
2200P_0402_25V7K

AG7
AG5
AF6
AE5
AG6
AG4
AF5

Close to Sensor

DD+

128@

AA7
W2
AA6
AA4

+3VS

SCLK

LCD_I2C_CLK_C

SDATA

LCD_I2C_DAT_C

ALERT#

THER_ALERT#
1
2
R501 128@ 0_0402_5%

D+

R499
2.2K_0402_5%
128@

D-

OVERT#

GND

+3VS

DVI pull-high close to GPU

LCD_I2C_DAT_C
R502
LCD_I2C_CLK_C
R500
DVI_SCLK
R110
DVI_SDATA
R106
I2CH_SCL
R130
I2CH_SDA
R128

128@ MAX6649MUA_8UMAX
I2C address
1001 100x

1
1
1
1
1
1

128@
128@
128@
128@
128@
128@

2
2
2
2
2
2

2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%

AH4

DACB_RED
DACB_BLUE
DACB_GREEN
DACB_IDUMP
DACB_RSET

R6
T6
T5
V7
R7

DACB_VREF

R5

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA

K2
J3
H4
J4
G2
G1
G3
H3

M_CRMA
M_COMP
M_LUMA

M_CRMA
M_COMP
M_LUMA

<17>
<17>
<17>

DACB_RSET
DACBVREF

C270 1
128@
M_DDCCLK
M_DDCDATA
DVI_SCLK
DVI_SDATA
LCD_I2C_CLK_C
LCD_I2C_DAT_C
I2CH_SCL
I2CH_SDA

2
0.01U_0402_16V7K
M_DDCCLK <17>
M_DDCDATA <17>
LCD_I2C_CLK_C <16>
LCD_I2C_DAT_C <16>
R139
@ 316_0402_1%
1
2

OSC_SPREAD <26>
OSC_OUT <26>
R489
@10K_0402_5%

GPIO11

R140
@ 316_0402_1%
1
2

DACB_RSET

Q6
@ 2N7002_SOT23

2
G

R145
128@ 124_0402_5%

R146
88.7_0402_1%
@
2

If Spread spectrum not stuff than stuff resistor

R1178 R1180 are optional

trim resistor to provide finer
control of the RSET value

Compal Secret Data

2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

+3VS
R105
1
2
10K_0402_5%

Security Classification

FAE recommand 6/29

M_HSYNC
M_VSYNC
M_RED
M_BLU
M_GRN

C686
0.1U_0402_16V4Z
128@

AH10

BUFRST_N
MEMSTRAPSEL0
MEMSTRAPSEL1
MEMSTRAPSEL2
MEMSTRAPSEL3
STEREO
STRAP
SWAPRDY_A
THERMDN
THERMDP

Thermal sensor

DACA_VREF
DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_BLUE
DACC_GREEN
DACC_IDUMP
DACC_RSET

B32
C20
D1
J6
U3
U4
U5
U6
V1
V3
V4
V5
V6
W1
W3
W4
W5
Y5
Y6
Y30
AC26
AG12
AH13
AM8
AM9
AM10

SERIAL

+3VS

AF10
AK10
AH11
AH12
AJ12
AG9
AH9

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25

Part 4 of 6

G71@ NV72/73M_BGA820

Y2

DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_IDUMP
DACA_RSET

XTALIN
XTALOUT

PCI_DEVID3 <26>

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

AL5
2
@ 1K_0402_5%
AM2
AM3
AE2
AE1
AF1
AF2
AG1
AH1
AG3
AH2
AK1
AJ1
AL2
AL1
AJ2
AJ3

RAM_CFG0 <26>
RAM_CFG1 <26>
CRYSTAL_0 <26>
PCI_DEVID2 <26>
PCI_DEVID0 <26>
PCI_DEVID1 <26>
CRYSTAL_1 <26>
MOBILE_MODE <26>
RAM_CFG2 <26>
RAM_CFG3 <26>

G71@ NV72/73M_BGA820
C646
128@
22P_0402_50V8J

R467
1

R115
2
1
128@ 10K_0402_5%

RAM_CFG0
RAM_CFG1
CRYSTAL_0
PCI_DEVID2
PCI_DEVID0
PCI_DEVID1
CRYSTAL_1
MOBILE_MODE
RAM_CFG2
RAM_CFG3

AK9
AJ9
AH6
AJ6
AH8
AH7
AJ8
AK8
AJ5
AH5
AK4
AL4
AM6
AM5
AM7
AL7
AK6
AK5
AK7
AL8

NC

PEX_CFG0

<16>
<16>
<16>
<16>
<16>
PEX_PLL_TERM <26> <16>
SUB_VENDOR <26> <16>
<16>

GENERAL

AF3
AE3
AD1
AD3

IFPAB_VPROBE
IFPCD_VPROBE

T2

R492
@ 10K_0402_5%

PEX_PLL_TERM
SUB_VENDOR

U33D

GPIO11

GND

For VDD_CORE voltage select

THER_ALERT#

TESTMEMCLK
TESTMODE

OUT

IN

GND

PEG_M_TXN[0..15] <9>

LVDS/TMDS

DVO / GPIO

MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CTL3

Y5
4

PEG_M_TXP[0..15] <9>

PEG_M_TXN[0..15]

2 10K_0402_5%
2@ 10K_0402_5%

AC3
AC1
AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5
AB4
AA5

PEX_REFCLK
PEX_REFCLK_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

R81 1
R57 1

PEG_M_TXP[0..15]

ENVDD
<16>
NV_ENBKL <44>

L2

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11

MIOB_VREF

PEX_RST_N

A26
H2

MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT_N

M5
R4
P4

MIOA_VREF

AM12
AM11
2 10K_0402_5%
2 10K_0402_5%

C152 1

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

AH15

R5121 128@
R1131 128@

R3
R1
P1
P3

PEG_RXN[0:15] <9>

AH14
AJ14

MIOA_HSYNC
MIOA_VSYNC
MIOA_DE
MIOA_CTL3

ENVDD
NV_ENBKL

+3VS

CLK_PCIE_VGA
CLK_PCIE_VGA#
VGA_RST#

<27> VGA_RST#

PEG_DTXP0 AJ15
PEG_DTXN0 AK15
PEG_DTXP1 AH16
PEG_DTXN1 AG16
PEG_DTXP2 AG17
PEG_DTXN2 AH17
PEG_DTXP3 AG18
PEG_DTXN3 AH18
PEG_DTXP4 AK18
PEG_DTXN4 AJ18
PEG_DTXP5 AJ19
PEG_DTXN5 AH19
PEG_DTXP6 AG20
PEG_DTXN6 AH20
PEG_DTXP7 AG21
PEG_DTXN7 AH21
PEG_DTXP8 AK21
PEG_DTXN8 AJ21
PEG_DTXP9 AJ22
PEG_DTXN9 AH22
PEG_DTXP10 AG23
PEG_DTXN10 AH23
PEG_DTXP11 AK24
PEG_DTXN11 AJ24
PEG_DTXP12 AJ25
PEG_DTXN12 AH25
PEG_DTXP13 AH26
PEG_DTXN13AG26
PEG_DTXP14 AK27
PEG_DTXN14 AJ27
PEG_DTXP15 AJ28
PEG_DTXN15 AH27

P2
N2
N1
N3
M1
M3
P5
N6
N5
M4
L4
L5

PEG_RXP[0:15] <9>

PEG_RXN[0:15]

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

C122
C123
C626
C625
C88
C89
C90
C91
C92
C93
C624
C623
C94
C95
C96
C97
C622
C621
C98
C99
C100
C101
C620
C619
C102
C103
C126
C127
C618
C617
C134
C135

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11

DACs

0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1
0.1U_0402_16V4Z 1

K3
H1
K5
G5
E2
J5
G6
K6
E1
D2
H5
F4
E3

I2C

128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@
128@

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12

PCI EXPRESS

PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15

Part 1 of 6

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

TEST

AK13
AK14
AM14
AM15
AL15
AL16
AK16
AK17
AL17
AL18
AM18
AM19
AK19
AK20
AL20
AL21
AM21
AM22
AK22
AK23
AL23
AL24
AM24
AM25
AK25
AK26
AL26
AL27
AM27
AM28
AL28
AL29

CLK

PEG_M_TXP0
PEG_M_TXN0
PEG_M_TXP1
PEG_M_TXN1
PEG_M_TXP2
PEG_M_TXN2
PEG_M_TXP3
PEG_M_TXN3
PEG_M_TXP4
PEG_M_TXN4
PEG_M_TXP5
PEG_M_TXN5
PEG_M_TXP6
PEG_M_TXN6
PEG_M_TXP7
PEG_M_TXN7
PEG_M_TXP8
PEG_M_TXN8
PEG_M_TXP9
PEG_M_TXN9
PEG_M_TXP10
PEG_M_TXN10
PEG_M_TXP11
PEG_M_TXN11
PEG_M_TXP12
PEG_M_TXN12
PEG_M_TXP13
PEG_M_TXN13
PEG_M_TXP14
PEG_M_TXN14
PEG_M_TXP15
PEG_M_TXN15

Title

Compal Electronics, Inc.

G72/73VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

18

of

60

FBAD[63..0]
FBAA[12..0]
FBBA[2..5]

FBAD[63..0] <22,23>

FBCD[63..0]

FBAA[12..0] <22,23>

FBCA[12..0]

FBBA[2..5] <23>

FBDA[2..5]

DQSA#[7..0] <22,23>

DQSC#[7..0]

1
DQSA[7..0]

R487
@ 10K_0402_5%

DQSA[7..0] <22,23>

DQSC[7..0]

12

ODTA0

DQMA#[7..0] <22,23>

DQMC#[7..0]

+1.8VS

DQSC#[7..0] <24,25>

R161
@ 10K_0402_5%
ODTC0

R160
256@ 10K_0402_5%

DQMC#[7..0] <24,25>

R484
128@ 10K_0402_5%

FBCA[12..0] <24,25>

DQSC[7..0] <24,25>

DQMA#[7..0]

FBCD[63..0] <24,25>

FBDA[2..5] <25>

+1.8VS
DQSA#[7..0]

12

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

L28
K31
G32
G28
AB28
AL32
AF32
AH30

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

E32

FBA_VREF1

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_REFCLK
FBA_REFCLK_N
FBA_DEBUG

P28
R28
Y27
AA27
D32
D31
AC27

1
10mil

CLKA0
CLKA0#
CLKA1
CLKA1#

10mil

R506
1K_0402_1%

FB_VREF1

+1.8VS

CLKA0
CLKA0#
CLKA1
CLKA1#

<22>
<22>
<23>
<23>

C687
0.1U_0402_16V4Z

R505
1K_0402_1%

R94

ODTA0
2
@ 0_0402_5%

ODTA0

<22,23>

G71@ NV72/73M_BGA820

FBCA3
FBCA0
FBCA2
FBCA1
FBDA3
FBDA4
FBDA5
FBCCS1#
PAD T24
FBCCS0#
FBCCS0#
FBCWE#
FBCWE#
FBC_BA0
FBC_BA0
FBC_CKE
R142 2 ODTC0
1
FBDA2 256@ 0_0402_5%
FBCA12
FBCRAS#
FBCRAS#
FBCA11
FBCA10
FBC_BA1
FBC_BA1
FBCA8
FBCA9
FBCA6
FBCA5
FBCA7
FBCA4
FBCCAS#
FBCCAS#

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

A4
E11
F5
C9
C28
F24
C24
E20

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

C6
E9
E6
A8
B29
E25
A25
F21

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

C5
E10
E5
B8
A29
D25
B25
F20

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

FB_VREF2

A28

FBA_VREF2

FBC_CLK0
FBC_CLK0_N
FBC_CLK1
FBC_CLK1_N
FBC_REFCLK
FBC_REFCLK_N
FBC_DEBUG

E13
F13
F18
E17
B1
C1
F12

CLKC0
CLKC0#
CLKC1
CLKC1#

1
R141

<24,25>
<24,25>
<24,25>
FBC_CKE <24,25>

R135
10K_0402_5%
256@

<24,25>
<24,25>

<24,25>

+1.8VS
1

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

<22,23>

C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26

R138
1K_0402_1%
@
2

M28
K32
G31
G27
AA28
AL31
AF31
AH29

<22,23>

Part 3 of 6

10mil
CLKC0
CLKC0#
CLKC1
CLKC1#

ODTC0
2
@ 0_0402_5%

<24>
1
<24>
C355
<25>
@
<25>
0.1U_0402_16V4Z
2

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

<22,23>

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

R143
1K_0402_1%
@
2

M29
M30
G30
F29
AA29
AK30
AC30
AG30

FBA_CKE <22,23>
R97
10K_0402_5%
128@

B7
A7
C7
A2
B2
C4
A5
B5
F9
F10
D12
D9
E12
D11
E8
D8
E7
F7
D6
D5
D3
E4
C3
B4
C10
B10
C8
A10
C11
C12
A11
B11
B28
C27
C26
B26
C30
B31
C29
A31
D28
D27
F26
D24
E23
E26
E24
F23
B23
A23
C25
C23
A22
C22
C21
B22
E22
D22
D21
E21
E18
D19
D18
E19

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

<22,23>
<22,23>
<22,23>

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

FBAA3
FBAA0
FBAA2
FBAA1
FBBA3
FBBA4
FBBA5
FBACS1#
PAD T21
FBACS0#
FBACS0#
FBAWE#
FBAWE#
FBA_BA0
FBA_BA0
FBA_CKE
R96 2 ODTA0
1
FBBA2 128@ 0_0402_5%
FBAA12
FBARAS#
FBARAS#
FBAA11
FBAA10
FBA_BA1
FBA_BA1
FBAA8
FBAA9
FBAA6
FBAA5
FBAA7
FBAA4
FBACAS#
FBACAS#

P32
U27
P31
U30
Y31
W32
W31
T32
V27
T28
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

Part 2 of 6

U33C

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

MEMORY INTERFACE A

N27
M27
N28
L29
K27
K28
J29
J28
P30
N31
N30
N32
L31
L30
J30
L32
H30
K30
H31
F30
H32
E31
D30
E30
H28
H29
E29
J27
F27
E27
E28
F28
AD29
AE29
AD28
AC28
AB29
AA30
Y28
AB30
AM30
AF30
AJ31
AJ30
AJ32
AK29
AM31
AL30
AE32
AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29
AD27
AF27
AE28

MEMORY INTERFACE B

U33B
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

ODTC0

<24,25>

G71@ NV72/73M_BGA820

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G72/73VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

19

of

60

+1.2VS

1808mA

(+1.1VS)
VID_PLLVDDPLLVDD
IFPAB_PLLVDD at G71/72
is +2.5VS

0.022U_0402_16V7K

+VGA_CORE
U33E
C265 1
128@

0.1U_0402_16V4Z 0.1U_0402_16V4Z
C289 1
128@

C286
2 128@ 2

+2.5VS

330U_V_2.5VK_R9
1
C706
1
128@ +

1 C287 1
128@
C269
128@ 2

C266
128@ 2

L17
D

VID_PLLVDD

1
2
BLM11A121SPT_0603
128@
1
C278
128@
4700P_0402_25V7K
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

40mA
C267

C279

128@
470P_0402_50V7K
220P_0402_50V7K

128@
2.2U_0603_6.3V6K

100P_0402_50V8J

C243 1
128@

C264
128@ 2

+2.5VS

1
2
BLM11A121SPT_0603
128@
1
C247
128@
4700P_0402_25V7K
2

1 C257 1
128@
C263
128@ 2

C241
2 128@ 2

100P_0402_50V8J
100P_0402_50V8J

L16
PLLVDD

100P_0402_50V8J

C281 1
128@

220P_0402_50V7K

40mA
C227

C255

128@
470P_0402_50V7K

220P_0402_50V7K

2
C321
128@
220P_0402_50V7K

128@
2.2U_0603_6.3V6K

220P_0402_50V7K

C320 1
128@

C284 1
128@

C245
128@ 2

+1.2VS
L19

FBA_PLLAVDD

1
2
BLM11A121SPT_0603
128@
1
C306
128@
2.2U_0603_6.3V6K
2

C336

C335

128@
4700P_0402_25V7K
C254
128@
10U_0805_10V4Z

128@
4700P_0402_25V7K

+3VS
L21
1
2
@ BLM11A121SPT_0603

C339

C346

1
@ 4700P_0402_25V7K

@ 2.2U_0603_6.3V6K

C181
128@ 2

@ 4700P_0402_25V7K
L22
FBC_PLLAVDD
C334

C290
128@
1U_0603_10V4Z

100P_0402_50V8J
C258 1
128@

C219
128@ 2

C288
128@ 2

0.022U_0402_16V7K
0.1U_0402_16V4Z
C322 1
128@

C340
2
128@ 2
0.1U_0402_16V4Z

R102 1
128@

C317
@ 2.2U_0603_6.3V6K

R95

FBC_PLLVDD
1
1

C344

C337

@ 4700P_0402_25V7K

0.022U_0402_16V7K +VGA_FBVTT
1 C223 1
1
128@

2
0_0603_5%
128@

C262
128@ 2

2.2U_0603_6.3V6K
1

128@ 1
C120

L9
1
2
BLM11A121SPT_0603
1 128@

C256 4700P_0402_25V7K
2 128@ 2

0.1U_0402_16V4Z

@ 4700P_0402_25V7K

DACA_VDD

H7
J7
K7
L7
L8
L10
M10
AC11
AC12
AC24
AD24
AE11
AE12

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12

FBA_PLLAVDD
FBC_PLLAVDD
FBA_PLLVDD
FBC_PLLVDD
2
40.2_0603_1%

+1.8VS

+1.8VS

L20
1
2
@ BLM11A121SPT_0603

VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
VDD_LP_4
VDD_LP_5

VID_PLLVDD T10
PLLVDD
T9

C788
4700P_0402_25V7K
128@

+3VS

C200
128@
470P_0402_50V7K

0.022U_0402_16V7K

128@
4700P_0402_25V7K

0.022U_0402_16V7K
C291 1
128@

+3VS
T33
PAD

128@ C199
4700P_0402_25V7K

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37

P20
T20
T23
U20
U23
W20

C244
C251
2
128@ 2
128@ 2
0.1U_0402_16V4Z 220P_0402_50V7K

4700P_0402_25V7K
0.022U_0402_16V7K
C209 1
C296 1
1
1
128@
128@

4700P_0402_25V7K

+1.2VS
1
2
BLM11A121SPT_0603
128@
1
C332
128@
2.2U_0603_6.3V6K
2

+3VS

FBA_PLLVDD
1

C294

220P_0402_50V7K

K16
K17
N13
N14
N16
N17
N19
N20
P13
P14
P16
P17
P19
R16
R17
NV
R104
T13
1
2
@ 0_0402_5%
T14
T15
T18
T19
U13
U14
U15
U19
V16
V17
W13
W14
W16
W17
W19
Y13
Y14
Y16
Y17
Y19
Y20
U18

G25
G10
G23
G8
K26
H16
H17
J9
J10
J23
J24
K9
K11
K12
K21
K22
K24
L23
M23
T25
U25
AA23
AB23
F6

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

AD23
AF23
AF24
AF25
AG24
AG25

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10

AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF21
AF22

PEX_PLLAVDD
PEX_PLLDVDD

AF15
AE15

Part 5 of 6

MIOA_VDDQ_0
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4
MIOACAL_PD_VDDQ
MIOBCAL_PD_VDDQ
IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD
IFPAB_PLLVDD
IFPCD_PLLVDD
DACA_VDD
DACB_VDD
DACC_VDD

VID_PLLVDD
PLLVDD

FBVDD_0
FBVDD_1
FBVDD_2
FBVDD_3
FBVDD_4
FBVDD_5
FBVDD_6
FBVDD_7
FBVDD_8
FBVDD_9
FBVDD_10
FBVDD_11
FBVDD_12
FBVDD_13
FBVDD_14
FBVDD_15
FBVDD_16
FBVDD_17
FBVDD_18
FBVDD_19

POWER

0.1U_0402_16V4Z

FBA_PLLAVDD
FBC_PLLAVDD
FBA_PLLVDD
FBC_PLLVDD
FBCAL_PD_VDDQ

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23

FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9
FBVTT_10
FBVTT_11
FBVTT_12
FBVTT_13
FBVTT_14
FBVTT_15
FBVTT_16
FBVTT_17
CLAMP

C197
1 128@ 1
C178
128@ 2

C195
128@ 1

C220
128@ 2

C172
128@ 2
0.022U_0402_16V7K

0.01U_0402_16V7K

1
C190
128@
2 2.2U_0603_6.3V6K

0.022U_0402_16V7K

0.01U_0402_16V7K
0.01U_0402_16V7K
C184 1
C177 1
1
1
128@
128@

C198 2
128@

PEX_PLLAVDD
PEX_PLLDVDD

0.022U_0402_16V7K

0.022U_0402_16V7K

C212 2
128@

0.01U_0402_16V7K

0.01U_0402_16V7K
C183 1
1
128@

C182 2
128@

0.01U_0402_16V7K

C242 2
128@

10U_0805_10V4Z
C260 1
1
128@
C277
128@
10U_0805_10V4Z
2
2

+1.2VS
L14
1
2
BLM11A121SPT_0603
1 128@

10U_0805_10V4Z
PEX_PLLAVDD
470P_0402_50V7K

180mA
20mA

1 C189 1
+1.8VS
MIOA_VDDQ
128@
M7
128@ L10
C221
M8
C188
2.2U_0603_6.3V6K
128@
R8
1
2
2
2 128@
2 2.2U_0603_6.3V6K
BLM11A121SPT_0603
T8
1 C121 1
1
4700P_0402_25V7K
128@
U9
MIOB_VDDQ
L15
AA8
4700P_0402_25V7K
C185
C186
AB7
1
2
2
BLM11A121SPT_0603
128@ 2
128@ 2
AB8
128@
C203
470P_0402_50V7K
4700P_0402_25V7K
AC6
1
1
1
1
128@
T22
C218
AC7
MIOACAL_PD_VDDQ PAD
C196
128@
L1
MIOBCAL_PD_VDDQ T20
2.2U_0603_6.3V6K
128@
Y1
2
2 2.2U_0603_6.3V6K
2
PAD
C210 2
128@
AF9 120mA IFPA_IOVDD
IFPB_IOVDD
AF8
470P_0402_50V7K
10K_0402_5%
AD6 128@ 1 R61
2
+2.5VS
10K_0402_5%
AE7 128@ 1 R62
2
L13
2.2U_0603_6.3V6K
AC9 40mA IFPAB_PLLVDD
1
2
+3VS
C201 1
BLM11A121SPT_0603
AA10 40mA1 R93
2
1
1
128@ 10K_0402_5%
128@
128@
MIOA_VDDQ L18
DACA_VDD 70mA
AD10
DACB_VDD 140mA C213
C208
MIOA_VDDQ
V8
1
2
2
BLM11A121SPT_0603
128@ 2
128@ 2
AD7
2 R91
1
128@ 10K_0402_5%
128@
470P_0402_50V7K
4700P_0402_25V7K
1
A3
128@ C268
A6
0.1U_0402_16V4Z
A9
2
A12
A15
A18
A21
A24
A27
A30
C32
F32
J32
M32
R32
V32
AA32
AD32
AG32
AK32
G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
L25
L26
M25
M26
R25
R26
V25
V26
AA25
AA26
AB25
AB26
H22

IFPA_IOVDDIFPB_IOVDD
at G71/72 is +1.8VS
at NV43/44 is +LCDVDD

MIOB_VDDQ

MIOB_VDDQ L11
1
2
BLM11A121SPT_0603
128@
1

128@ C211
0.1U_0402_16V4Z

+1.8VS
4700P_0402_25V7K
C276 1
1
128@
C293
128@ 2

4700P_0402_25V7K

4700P_0402_25V7K
C217 1
1
128@

C253
128@ 2

C319
128@ 2

4700P_0402_25V7K

0.022U_0402_16V7K
C326 1
1
1
128@

0.022U_0402_16V7K 0.022U_0402_16V7K 4.7U_0805_10V4Z

C282 1
C338 1
C667 1
1
1
1
128@
128@
128@

0.1U_0402_16V4Z
C342 1
1
128@

C324
C325
2
128@ 2
128@ 2
0.022U_0402_16V7K 0.1U_0402_16V4Z

C271
128@ 2

4700P_0402_25V7K 0.022U_0402_16V7K
0.1U_0402_16V4Z
C240 1
1
128@

C343
2
128@ 2
0.1U_0402_16V4Z

C285
128@ 2
4.7U_0805_10V4Z

C627
128@ 2
330U_V_2.5VK_R9

0.1U_0402_16V4Z
C292 1
1
128@

C216
2
128@ 2
0.1U_0402_16V4Z

C345
128@ 2
0.1U_0402_16V4Z

G71@ NV72/73M_BGA820
DACB_VDD
C252
128@
470P_0402_50V7K

2.2U_0603_6.3V6K
1

128@ 1
C119
2

L8
1
2
BLM11A121SPT_0603
1 128@

128@ C261
4700P_0402_25V7K

L12
+1.2VS

NV

128@ BLM11A121SPT_0603
128@

C207

4.7U_0603_6.3V6M
1
2

C283
0.022U_0402_16V7K
128@

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G72/73VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0

Thursday, December 15, 2005

Sheet
1

20

of

60

U33F

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83

Part 6 of 6

GND

B3
B6
B9
B12
B15
B18
B21
B24
B27
B30
C2
C31
D4
D7
D10
D13
D17
D20
D23
D26
D29
F2
F8
F11
F14
F19
F22
F25
F31
G4
G7
G26
G29
H27
H6
J2
J16
J17
J31
K10
K23
K29
K4
L6
L27
M2
M12
M21
M31
N4
N15
N18
N29
P6
P15
P18
P27
R2
R13
R14
R15
R18
R19
R20
R31
T4
T16
T17
T24
T29
U8
U16
U17
U24
U29
V2
V13
V14
V15
V18
V19
V20
V31
W6

GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154

W18
Y4
Y15
Y18
Y29
AA2
AA12
AA21
AA31
AB6
AB27
AC4
AC10
AC23
AC29
AD2
AD16
AD17
AD31
AE6
AE17
AE27
AF4
AF7
AF11
AF26
AF29
AG2
AG8
AG10
AG11
AG13
AG14
AG15
AG19
AG22
AG31
AH24
AJ4
AJ7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ26
AJ29
AK2
AL3
AL6
AL9
AL10
AK28
AK31
AL11
AL14
AL19
AL22
AL25
AM13
AM16
AM17
AM20
AM23
AM26
AM29
D16
W27
W15

IFPAB_PLLGND
IFPCD_PLLGND

AD9
AB10

MIOACAL_PU_GND
MIOBCAL_PU_GND
PEX_PLLGND

L3
Y3
AE16

PLLGND

U10

FBA_PLLGND
FBC_PLLGND

G24
G9

FBCAL_PU_GND
FBCAL_TERM_GND

H26
J26

For NV73 R116 change to 40.2_0603_1%(SD014402A80)

128@ 1
128@ 1

R116 2 30_0603_1%
R103 2 40.2_0402_1%

G71@ NV72/73M_BGA820

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G72/73VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

21

of

60

CLKA0#
CLKA0

K8
J8

CK
CK

FBA_CKE

K2

FBACS0#

L8

CS

FBAWE#

K3

WE

FBARAS#

K7

RAS

FBACAS#

L7

CAS

DQMA#2
DQMA#0

F3
B3

LDM
UDM

ODTA0
+1.8VS

VRAM_VREFA

R485
1K_0402_1%
128@

K9

ODT

DQSA2
DQSA#2

F7
E8

LDQS
LDQS

DQSA0
DQSA#0

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

R486
1K_0402_1%
128@

CKE

C672
0.047U_0402_16V4Z
128@

Close to U76

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

L2
L3

BA0
BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

K8
J8

CK
CK

FBA_CKE

K2

CKE

+1.8VS

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

FBA_BA0
FBA_BA1

1
C675
0.1U_0402_16V4Z
128@

FBACS0#

L8

CS

FBAWE#

K3

WE

FBARAS#

K7

RAS

FBACAS#

L7

CAS

DQMA#1
DQMA#3

F3
B3

LDM
UDM

ODTA0
C676
1U_0402_6.3V4Z
128@

VRAM_VREFA

K9

ODT

DQSA1
DQSA#1

F7
E8

LDQS
LDQS

DQSA3
DQSA#3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

C362
0.047U_0402_16V4Z
128@

Close to U77

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

FBAD25
FBAD27
FBAD26
FBAD30
FBAD29
FBAD24
FBAD28
FBAD31
FBAD11
FBAD14
FBAD8
FBAD12
FBAD13
FBAD10
FBAD15
FBAD9

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBAA[12..0]

<19,23> FBAA[12..0]

DQSA#[7..0]

<19,23> DQSA#[7..0]

DQSA[7..0]

<19,23> DQSA[7..0]

DQMA#[7..0]
FBA_BA[1..0]

<19,23> FBA_BA[1..0]
+1.8VS

ODTA0

<19,23> ODTA0

FBA_CKE

<19,23> FBA_CKE

FBARAS#

<19,23> FBARAS#

FBACAS#

<19,23> FBACAS#

FBAWE#

<19,23> FBAWE#
1
C359
0.1U_0402_16V4Z
128@

FBACS0#

<19,23> FBACS0#

C358
1U_0402_6.3V4Z
128@

Close to U10
<19>

CLKA0

CLKA0
R513
@ 120_0402_5%
+1.8VS

R510
120_0402_5%
128@

<19>
128@ HY5PS561621F-25

FBAD[63..0]

<19,23> FBAD[63..0]

<19,23> DQMA#[7..0]

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBAD5
FBAD1
FBAD7
FBAD0
FBAD3
FBAD6
FBAD2
FBAD4
FBAD21
FBAD19
FBAD18
FBAD17
FBAD16
FBAD22
FBAD23
FBAD20

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0

U2
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

1
1

BA0
BA1

R515
120_0402_5%
@

L2
L3

CLKA0#

C365
0.1U_0402_16V4Z
@
CLKA0#

U35
FBA_BA0
FBA_BA1

128@ HY5PS561621F-25

For NV73 R510 change to 481_0402_1%(SD00000CA80)

DDR2 BGA MEMORY

DDR2 BGA MEMORY

+1.8VS

128@
C674
1000P_0402_50V7K

+1.8VS

128@ C692
0.01U_0402_16V7K
1
1

2
2
128@ C684
0.01U_0402_16V7K

128@ C705
1U_0402_6.3V4Z
1
1

2
2
128@ C671
0.1U_0402_16V4Z

128@ C703
0.1U_0402_16V4Z
1
1

2
2
128@ C704
0.1U_0402_16V4Z

C702
0.01U_0402_16V7K
128@

128@
C360
1000P_0402_50V7K

128@ C363
0.01U_0402_16V7K
1
1

2
2
128@ C361
0.01U_0402_16V7K

128@ C274
1U_0402_6.3V4Z
1
1

2
2
128@ C364
0.1U_0402_16V4Z

128@ C323
0.01U_0402_16V7K
1
1

2
2
128@ C673
0.1U_0402_16V4Z

C354
0.01U_0402_16V7K
128@

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G72/73VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

22

of

60

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

FBA_CKE

K2

FBACS0#

L8

FBAWE#

K3

FBARAS#

K7

FBACAS#
DQMA#5
DQMA#4
ODTA0

+1.8VS

VRAM_VREFB

R574
1K_0402_1%
128@

CS
WE

L7

CAS

F3
B3

LDM
UDM
ODT

DQSA5
DQSA#5

F7
E8

LDQS
LDQS

DQSA4
DQSA#4

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

C636
0.047U_0402_16V4Z
128@

Close to U78

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

RAS

K9

(SSTL-1.8) VREF = .5*VDDQ

R575
1K_0402_1%
128@

CKE

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

FBAD39
FBAD35
FBAD38
FBAD34
FBAD32
FBAD37
FBAD33
FBAD36
FBAD45
FBAD46
FBAD41
FBAD40
FBAD47
FBAD42
FBAD44
FBAD43

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

L2
L3

BA0
BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4
FBBA3
FBBA2
FBAA1
FBAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

FBA_CKE

K2

CKE

+1.8VS
FBACS0#

L8

FBAWE#

K3

FBARAS#

K7

FBACAS#
DQMA#6
DQMA#7
1

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

FBA_BA0
FBA_BA1

1
C633
0.1U_0402_16V4Z
128@

C632
1U_0402_6.3V4Z
128@

ODTA0

VRAM_VREFB

CS
WE

L7

CAS

F3
B3

LDM
UDM
ODT

DQSA6
DQSA#6

F7
E8

LDQS
LDQS

DQSA7
DQSA#7

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

C670
0.047U_0402_16V4Z
128@

Close to U79

128@ HY5PS561621F-25

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

RAS

K9

(SSTL-1.8) VREF = .5*VDDQ

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

FBAD57
FBAD56
FBAD58
FBAD63
FBAD61
FBAD59
FBAD60
FBAD62
FBAD51
FBAD55
FBAD50
FBAD54
FBAD52
FBAD48
FBAD53
FBAD49

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBAA[12..0]

<19,22> FBAA[12..0]

FBBA[2..5]

<19> FBBA[2..5]

DQSA#[7..0]

<19,22> DQSA#[7..0]

DQSA[7..0]

<19,22> DQSA[7..0]

DQMA#[7..0]

<19,22> DQMA#[7..0]
<19,22> FBA_BA[1..0]
+1.8VS

<19,22>

FBA_BA[1..0]

ODTA0

FBARAS#

<19,22> FBARAS#

FBACAS#

<19,22> FBACAS#

FBAWE#

<19,22> FBAWE#

FBACS0#

<19,22> FBACS0#
1

ODTA0
FBA_CKE

<19,22> FBA_CKE

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

FBAD[63..0]

<19,22> FBAD[63..0]

1
C272
0.1U_0402_16V4Z
128@

<19>

C273
1U_0402_6.3V4Z
128@

CLKA1

R75
120_0402_5%
128@

128@ HY5PS561621F-25

R70
120_0402_5%
+1.8VS
@
1
R69
120_0402_5%
@

CLKA1#

C154
0.1U_0402_16V4Z
@

CLKA1#

<19>

CLKA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4
FBBA3
FBBA2
FBAA1
FBAA0

U1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BA0
BA1

L2
L3

U32
FBA_BA0
FBA_BA1

Close to U11

For NV73 R75 change to 481_0402_1%(SD00000CA80)

DDR2 BGA MEMORY

+1.8VS

1
128@
C631
1000P_0402_50V7K

128@ C634
0.01U_0402_16V7K
1
1

2
2
128@ C635
0.01U_0402_16V7K

128@ C259
1U_0402_6.3V4Z
1
1

2
2
128@ C638
0.1U_0402_16V4Z

DDR BGA MEMORY

+1.8VS
128@ C246
0.1U_0402_16V4Z
1
1

2
2
128@ C194
0.1U_0402_16V4Z

1
128@ C224
0.01U_0402_16V7K

128@ C155
1000P_0402_50V7K

128@ C637
0.01U_0402_16V7K
1
1

2
2
128@ C275
0.01U_0402_16V7K

128@ C153
1U_0402_6.3V4Z
1
1

2
2
128@ C151
0.1U_0402_16V4Z

128@ C150
0.01U_0402_16V7K
1
1

2
2
128@ C149
0.1U_0402_16V4Z

128@ C148
0.01U_0402_16V7K

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G72/73VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

23

of

60

CLKC0#
CLKC0

K8
J8

FBC_CKE

K2

FBCCS0#

L8

CS

K3

WE

FBCRAS#

K7

RAS

L7

CAS

F3
B3

LDM
UDM

DQMC#0
DQMC#1
ODTC0
+1.8VS

R163
1K_0402_1%
256@

VRAM_VREFC

K9

ODT

DQSC0
DQSC#0

F7
E8

LDQS
LDQS

DQSC1
DQSC#1

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

R162
1K_0402_1%
256@

CKE

FBCWE#

FBCCAS#
C

CK
CK

C388
0.047U_0402_16V4Z
256@

Close to U80

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

+1.8VS

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

L2
L3

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKC0#
CLKC0

K8
J8

FBC_CKE

K2

1
C385
0.1U_0402_16V4Z
256@

L8

CS

K3

WE

FBCRAS#

K7

RAS

L7

CAS

F3
B3

LDM
UDM

ODTC0

VRAM_VREFC

CKE

FBCCS0#

DQMC#3
DQMC#2
1 C384
1U_0402_6.3V4Z
256@

CK
CK

FBCWE#

FBCCAS#

2
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

FBC_BA0
FBC_BA1

K9

ODT

DQSC3
DQSC#3

F7
E8

LDQS
LDQS

DQSC2
DQSC#2

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

C728
0.047U_0402_16V4Z
256@

Close to U81

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBCD19
FBCD18
FBCD17
FBCD22
FBCD20
FBCD23
FBCD21
FBCD16
FBCD27
FBCD31
FBCD25
FBCD30
FBCD29
FBCD26
FBCD28
FBCD24

FBCD[63..0]

<19,25> FBCD[63..0]

FBCA[12..0]

<19,25> FBCA[12..0]

DQSC#[7..0]

<19,25> DQSC#[7..0]

DQSC[7..0]

<19,25> DQSC[7..0]

DQMC#[7..0]

<19,25> DQMC#[7..0]
+1.8VS

ODTC0

<19,25> ODTC0

FBC_CKE

<19,25> FBC_CKE

FBCRAS#

<19,25> FBCRAS#

FBCCAS#

<19,25> FBCCAS#

FBCWE#

<19,25> FBCWE#
1

FBCCS0#

<19,25> FBCCS0#
1 C726
1U_0402_6.3V4Z
256@

C725
0.1U_0402_16V4Z
256@

Close to U14
<19>

CLKC0

R533
481_0402_1%
256@

<19>
256@ HY5PS561621F-25

FBC_BA[1..0]

<19,25> FBC_BA[1..0]

CLKC0#

CLKC0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCD13
FBCD10
FBCD11
FBCD14
FBCD15
FBCD12
FBCD9
FBCD8
FBCD4
FBCD1
FBCD7
FBCD0
FBCD3
FBCD6
FBCD2
FBCD5

R531
120_0402_5%
+1.8VS
@
2

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

1
1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

U37
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

R534
120_0402_5%
@

C733
0.1U_0402_16V4Z
2 @
CLKC0#

BA0
BA1

L2
L3

U7
FBC_BA0
FBC_BA1
D

256@ HY5PS561621F-25

For NV73 R533 change to 481_0402_1%(SD00000CA80)

DDR2 BGA MEMORY

+1.8VS

1
256@ C398
1000P_0402_50V7K

256@ C412
0.01U_0402_16V7K
1
1

2
2
256@ C383
0.01U_0402_16V7K

256@ C413
1U_0402_6.3V4Z
1
1

2
2
256@ C411
0.1U_0402_16V4Z

2
2
256@ C395
0.1U_0402_16V4Z

DDR BGA MEMORY

+1.8VS

256@ C382
0.1U_0402_16V4Z
1
1
256@ C410
0.01U_0402_16V7K

1
256@
C735
1000P_0402_50V7K

256@ C716
0.01U_0402_16V7K
1
1

2
2
256@ C718
0.01U_0402_16V7K

256@ C751
1U_0402_6.3V4Z
1
1

2
2
256@ C750
0.1U_0402_16V4Z

256@ C753
0.01U_0402_16V7K
1
1

2
2
256@ C752
0.1U_0402_16V4Z

256@ C717
0.01U_0402_16V7K

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G71/72VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

24

of

60

FBDA[2..5]

<19> FBDA[2..5]

CK
CK

L8

CS

FBCWE#

K3

WE

FBCRAS#

K7

RAS

FBCCAS#

L7

CAS

F3
B3

LDM
UDM

ODTC0
DQSC5
DQSC#5

+1.8VS

VRAM_VREFD

R576
1K_0402_1%
256@

DQSC4
DQSC#4

(SSTL-1.8) VREF = .5*VDDQ

R577
1K_0402_1%
256@

CKE

FBCCS0#

DQMC#5
DQMC#4

C392
0.047U_0402_16V4Z
256@

Close to U82

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

K9

ODT

F7
E8

LDQS
LDQS

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSS1
VSS2
VSS3
VSS4
VSS5

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKC1#
CLKC1

K8
J8

CK
CK

FBC_CKE

K2

CKE

FBCCS0#

L8

CS

FBCWE#

K3

WE

FBCRAS#

K7

RAS

FBCCAS#

L7

CAS

F3
B3

LDM
UDM

+1.8VS

DQMC#7
DQMC#6
1

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

BA0
BA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

C386
0.1U_0402_16V4Z
256@

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

1 C390
1U_0402_6.3V4Z
256@
2

VRAM_VREFD

ODTC0

K9

ODT

DQSC7
DQSC#7

F7
E8

LDQS
LDQS

DQSC6
DQSC#6

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

A3
E3
J3
N1
P9

C724
0.047U_0402_16V4Z
256@

Close to U83

256@ HY5PS561621F-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

<19,24> FBCD[63..0]

FBCA[12..0]

<19,24> FBCA[12..0]

DQSC#[7..0]

<19,24> DQSC#[7..0]

DQSC[7..0]

<19,24> DQSC[7..0]

DQMC#[7..0]

<19,24> DQMC#[7..0]

FBC_BA[1..0]

<19,24> FBC_BA[1..0]

ODTC0

<19,24> ODTC0

+1.8VS

FBC_CKE

<19,24> FBC_CKE

FBCRAS#

<19,24> FBCRAS#

FBCCAS#

<19,24> FBCCAS#

FBCWE#

<19,24> FBCWE#

FBCCS0#

<19,24> FBCCS0#
1

1
C722
0.1U_0402_16V4Z
256@

C719
1U_0402_6.3V4Z
256@

<19>

CLKC1

R168
481_0402_1%
256@

256@ HY5PS561621F-25
<19>

CLKC1

K8
J8
K2

L2
L3

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBDA5
FBDA4
FBDA3
FBDA2
FBCA1
FBCA0

R167
120_0402_5%
+1.8VS
@
2

CLKC1#
CLKC1
FBC_CKE

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

FBCD[63..0]

1
1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BA0
BA1

FBCD54
FBCD49
FBCD52
FBCD48
FBCD51
FBCD53
FBCD50
FBCD55
FBCD62
FBCD56
FBCD61
FBCD57
FBCD58
FBCD63
FBCD59
FBCD60

R169
120_0402_5%
@

CLKC1#

C710
0.1U_0402_16V4Z
2 @
CLKC1#

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

FBC_BA0
FBC_BA1

L2
L3

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBDA5
FBDA4
FBDA3
FBDA2
FBCA1
FBCA0

U36
FBCD36
FBCD33
FBCD39
FBCD34
FBCD35
FBCD37
FBCD32
FBCD38
FBCD45
FBCD43
FBCD42
FBCD46
FBCD47
FBCD40
FBCD44
FBCD41

U8
FBC_BA0
FBC_BA1

Close to U15

For NV73 R168 change to 481_0402_1%(SD00000CA80)

DDR2 BGA MEMORY

+1.8VS

1
256@ C406
1000P_0402_50V7K

DDR2 BGA MEMORY

+1.8VS

256@ C409
0.01U_0402_16V7K
1
1

2
2
256@ C407
0.01U_0402_16V7K

256@ C378
1U_0402_6.3V4Z
1
1

2
2
256@ C402
0.1U_0402_16V4Z

256@ C403
0.1U_0402_16V4Z
1
1

2
2
256@ C374
0.1U_0402_16V4Z

1
256@ C405
0.01U_0402_16V7K

256@ C745
1000P_0402_50V7K

256@ C748
0.01U_0402_16V7K
1
1

2
2
256@ C744
0.01U_0402_16V7K

256@ C749
1U_0402_6.3V4Z
1
1

2
2
256@ C747
0.1U_0402_16V4Z

256@ C713
0.01U_0402_16V7K
1
1

2
2
256@ C746
0.1U_0402_16V4Z

256@ C404
0.01U_0402_16V7K

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G71/72VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

25

of

60

STRAPS

+3VS

CRYSTAL_1

<18> CRYSTAL_1

1
R78

CRYSTAL_0

<18> CRYSTAL_0

PIN

Value

DESCRIPTION

CRYSTAL[1:0]

MIOBD[6,2] 27MHz=10, 14.318MHz=01, 13.5MHz=00

10

ROM_TYPE[1:0]

MIOBD
[11:10]

Parallel=00, SERIAL M25P10=01,

Serial SST45VF=10

01

SUB_VENDOR

MIOAD1

VBIOS on card (pull high)

VBIOS with system BIOS (pull down)

PEX_PLL_TERM

MIOAD0

PEX_CFG[2:0]

MIOAD
[9,8,6]

2
@ 2K_0402_5%

1
R468

2
@ 2K_0402_5%

0
Overridden

001

16Mx16 (1.8V or 2.5V)Hynix X 4pcs

0011

16Mx16 (1.8V or 2.5V)Infineon X 4pcs

0010

16Mx16 (1.8V or 2.5V)Samsung X 4pcs

0001

16Mx16 (1.8V or 2.5V)Hynix X 8pcs

1011

16Mx16 (1.8V or 2.5V)Infineon X 8pcs

1010

16Mx16 (1.8V or 2.5V)Samsung X 8pcs

1001

NV72M

1000

NV73M

1000

RAM_CFG[3:0]

PCI_DEVID[3:0]

A01
VIPD[5:3]
MIOA_HSYNC

@
2K_0402_5%

128@
2K_0402_5%

R498
2

@ 2K_0402_5%

R84
@ 2K_0402_5%

R494

@ 2K_0402_5%

1
2

2
1

@
2K_0402_5%

R111

R497
@ 2K_0402_5%

R83

@
2K_0402_5%

R118
@ 2K_0402_5%

R117

1
2

R493
@ 2K_0402_5%
2

2
1
2

@ 2K_0402_5%

1
2

R108
128@
2K_0402_5%

R66
2

128@
2K_0402_5%

R112
@
2K_0402_5%

R107

@
2K_0402_5%

R477

1
2

@ 2K_0402_5%

R470

@
2K_0402_5%

R63

R67
128@
2K_0402_5%

R469
@ 2K_0402_5%

R475

128@
2K_0402_5%

R473

R474
@ 2K_0402_5%

R59

R72
@ 2K_0402_5%

R60
@ 2K_0402_5%

R476
@ 2K_0402_5%

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
PCI_DEVID0
PCI_DEVID1
PCI_DEVID2
PCI_DEVID3
PEX_CFG0
PEX_CFG1
PEX_CFG2
PEX_PLL_TERM
MOBILE_MODE
SUB_VENDOR

<18> RAM_CFG0
<18> RAM_CFG1
<18> RAM_CFG2
<18> RAM_CFG3
<18> PCI_DEVID0
<18> PCI_DEVID1
<18> PCI_DEVID2
<18> PCI_DEVID3
<18> PEX_CFG0
<18> PEX_CFG1
<18> PEX_CFG2
<18> PEX_PLL_TERM
<18> MOBILE_MODE
<18> SUB_VENDOR

R64
@ 2K_0402_5%
2

R472
128@
2K_0402_5%

R73
128@
2K_0402_5%

+3VS

128@
2K_0402_5%

+3VS

Spread spectrum

1
128@ C376
0.1U_0402_16V4Z

<18>

OSC_OUT

U3
7

VDD

XIN MODOUT

4 R133 1 128@

2 22_0402_5%

XOUT

NC

3 R134 2

1@ 10K_0402_5%

PD#

6 R148 2

1@ 10K_0402_5%

VSS

REF

5
OSC_SPREAD <18>

ASM3P1819N-SR_SO8
128@

EMI request 6/7

Compal Secret Data

Security Classification
2005/03/01

Issued Date

2006/03/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

G71/72 VGA Board

Size Document Number

Custom LA-2841
Date:

Rev
1.0

Thursday, December 15, 2005

Sheet
1

26

of

60

+3VS

2 8.2K_0402_5%

PCI_PLOCK#

R540 1

2 8.2K_0402_5%

PCI _IRDY#

R538 1

2 8.2K_0402_5%

PCI_SERR#

R213 1

2 8.2K_0402_5%

PCI_PERR#

R178 1

2 8.2K_0402_5%

PCI_REQ4#

R527 1

2 8.2K_0402_5%

PCI_REQ3#

U6B

<32,36> PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3VS

R195 1

2 8.2K_0402_5%

PCI_PIRQA#

R196 1

2 8.2K_0402_5%

PCI_PIRQB#

R194 1

2 8.2K_0402_5%

PCI_PIRQC#

R193 1

2 8.2K_0402_5%

PCI_PIRQD#

R197 1

2 8.2K_0402_5%

PCI_PIRQE#

R524 1

2 8.2K_0402_5%

PCI_PIRQF#

R525 1

2 8.2K_0402_5%

PCI_PIRQG#

R198 1

2 8.2K_0402_5%

PCI_PIRQH#

R192 1

2 8.2K_0402_5%

PCI_REQ0#

R211 1

2 8.2K_0402_5%

PCI_REQ1#

R210 1

2 8.2K_0402_5%

PCI_REQ2#

R212 1

2 8.2K_0402_5%

PCI_REQ5#

<32> PCI_PIRQC#
<32> PCI_PIRQD#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

PCI_REQ0#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

B15
C12
D12
C15

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

C26
A9
B19

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

G8
F7
F8
G7

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI

Interrupt
PIRQA#
PIRQB#
PIRQC#
PIRQD#

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

PCI_REQ1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ2# <32>
PCI_GNT2# <32>

PCI_REQ4#

+3VS

PCI_REQ5#
5

PCI_FRAME#

R526 1

AE9
AG8
AH8
F21
AH20

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_PCIRST#

<32,36>
<32,36>
<32,36>
<32,36>

PCI_IRDY# <32>
PCI_PAR <32>

R186
0_0402_5%
1

PCI_DEVSEL# <32>
PCI_PERR# <32>

U10

2 8.2K_0402_5%

PCI_RST#

PCI_RST# <32,33,36,42,44>

PCI_TRDY#

R530 1

@ TC7SH08FU_SSOP5

2 8.2K_0402_5%

+3VS

PCI_SERR# <32>
PCI_STOP# <32>
PCI_TRDY# <32,36>
PCI_FRAME# <32,36>

PCI_STOP#

R528 1

PCI_PLTRST#

1
2

B
A

CLK_PCI_ICH <15>
PCI_PME# <32,44>

PCI_PIRQE# <32>

R203
2
1
0_0402_5%

U11

PCI_DEVSEL#

2 8.2K_0402_5%

2 8.2K_0402_5%

R529 1

PLT_RST#

VGA_RST# <18>
PLT_RST# <7,31,32,34,37>

@ TC7SH08FU_SSOP5

R179 1

R185
0_0402_5%
1

PCI_PIRQG# <32>

MCH_ICH_SYNC# <7>

Place closely pin A9

ICH7_BGA652~D

CLK_PCI_ICH
B

R176

@ 10_0402_5%

C415
@ 8.2P_0402_50V

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH7-M(1/4)

Size

Document Number

Rev
1.0

LA-2841
Date:

Sheet

Thursday, December 15, 2005

1

27

of

60

C370
18P_0402_50V8J
2
1

OUT

R517 1
20K_0402_5%

ICH_RTCX2
ICH_RTCRST#

ICH_INTVRMEN
SM_INTRUDER#

+3VALW

CLRP1
1
2

0.1U_0402_16V4Z
2

VCC
NC
NC
GND

CS
SK
DI
DO

EEP_CS
EEP_SK
EEP_DOUT
EEP_DIN

1
2
3
4

AT93C46-10SI-2.7_SO8

G
1

R608
@ 47K_0402_5%

V3

LAN_CLK

U3

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2

U5
V4
T5

LAN_RXD0
LAN_RXD1
LAN_RXD2

ACZ_SDIN0

ACZ_SDOUT

<38> ACZ_SDOUT

AC3
AA5

LPC_DRQ0#

LFRAME#

AB3

LPC_FRAME#

A20GATE
A20M#

AE22
AH28

GATEA20
H_A20M#

U7
V6
V7

ACZ_BCLK
ACZ_SYNC

R5

ACZ_RST#

T2
T3
T1

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

T4

IDE_LED#

<31> PSATA_IRX_DTX_N0_C
<31> PSATA_IRX_DTX_P0_C

H_CPUSLP_R#

AF24
AH25

DPRSLP#
H_DPSLP#

FERR#

AG26

H_FERR#

GPIO49 / CPUPWRGD

AG24

H_PW RGOOD

IGNNE#
INIT3_3V#
INIT#
INTR

AG22
AG21
AF22
AF25

H_IGNNE#

<31> SSATA_IRX_DTX_N0_C
<31> SSATA_IRX_DTX_P0_C

R516
1M_0402_5%
SM_INTRUDER#

<15> CLK_PCIE_SATA#
<15> CLK_PCIE_SATA

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

AF3
AE3
AG2
AH2

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SSATA_IRX_DTX_N0_C
SSATA_IRX_DTX_P0_C
SSATA_ITX_DRX_N0_C
SSATA_ITX_DRX_P0_C

AF7
AE7
AG6
AH6

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF1
AE1

SATA_CLKN
SATA_CLKP

CLK_PCIE_SATA#
CLK_PCIE_SATA
R127

+RTCVCC

+3VS

AH10
AG10

SATARBIASN
SATARBIASP

PD _IORDY
PD_IRQ

1 R126
1 R125

ICH_INTVRMEN

<31>
<31>
<31>
<31>
<31>

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

PD _IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

AG16
AH16
AF16
AH15
AF15

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

H_INIT#
H_INTR
2

AF23
AH24

H_SMI#
H_NMI

STPCLK#

H_STPCLK#

THERMTRIP#

AF26

THRMTRIP_ICH#

DA0
DA1
DA2

AH17
AE17
AF17

PD_A0
PD_A1
PD_A2

DCS1#
DCS3#

AE16
AD16

PD_CS#1
PD_CS#3

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

DDREQ

AE15

PD_DREQ

IDE

T23

1 R121 0_0402_5%
H_DPRSTP# <4,53>
H_DPSLP# <4>
56_0402_5% +VCCP
1
R114
H_FERR# <4>

H_IGNNE# <4>

H_INIT#
H_INTR

AH22

4.7K_0402_5% 2
8.2K_0402_5% 2

332K_0402_1%

+3VS

H_PWRGOOD <4>

SMI#
NMI

24.9_0402_1%
R519

KB_RST#

RCIN#

1 R122 10K_0402_5%
GATEA20 <44>
H_A20M# <4>
PAD

AG23

SATA

+RTCVCC

SATALED#

LPC_FRAME# <42,44>
2

AG27

ACZ_SDOUT

AF18

LPC_DRQ#0 <42>

CPUSLP#

LAN_TXD0
LAN_TXD1
LAN_TXD2

U1
R6

TP1 / DPRSTP#
TP2 / DPSLP#

EC_RTCRESET
<43> IDE_LED#

LAN_JCLK

C381 @ 10P_0402_25V8K
2
1
1 R150
2
@ 10_0402_5%
ACZ_BITCLK
<38> ACZ_BITCLK
ACZ _SYNC
<38> ACZ_SYNC
R155
33_0402_5% 1
2 ACZRST#
<38,44> ACZ_RST#
<38> ACZ_SDIN0

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_RSTSYNC

LAN_TXD0
LAN_TXD1
LAN_TXD2

<35> LAN_TXD0
<35> LAN_TXD1
<35> LAN_TXD2

<44> EC_RTCRESET

LDRQ0#
LDRQ1# / GPIO23

AC-97/AZALIA

INTVRMEN
INTRUDER#

W1
Y1
Y2
W3

<35> LAN_JCLK

<35> LAN_RXD0
<35> LAN_RXD1
<35> LAN_RXD2

Q52
@ 2N7002_SOT23

0.1U_0402_16V4Z

W4
Y5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CPU

C372

8
7
6
5

<35> LAN_RSTSYNC

RTCRST#

AA6
AB5
AC4
Y6

LAN

C707
1U_0603_10V4Z
1
2

C828

AA3

LPC_AD[0..3] <42,44>
LAD0
LAD1
LAD2
LAD3

U4

SHORT PADS

RTXC1
RTCX2

RTC

+RTCVCC

U6A
AB1
AB2

<4>
<4>

1 R508 10K_0402_5%
KB_RST# <44>

+VCCP

+3VS

IN

NC

LPC

NC

H_SMI#
H_NMI

<4>
<4>

R119

1 R120
2
24.9_0402_1%
PD_A0
PD_A1
PD_A2

56_0402_5%

H_STPCLK# <4>
2

R144
10M_0402_5%
2
1

C356
18P_0402_50V8J
2
1

ICH_RTCX1

Y1
32.768KHZ_12.5P_1TJS125BJ4A421P

H_THERMTRIP# <4,7>

<31>
<31>
<31>

PD_CS#1 <31>
PD_CS#3 <31>

PD_DREQ <31>

ICH7_BGA652~D
PD_D[0..15]
<31> PSATA_ITX_DRX_N0
<31> PSATA_ITX_DRX_P0

PSATA_ITX_DRX_N0

1
C353

PSATA_ITX_DRX_N0_C
2
3900P_0402_50V7K

PSATA_ITX_DRX_P0

1
C351

PSATA_ITX_DRX_P0_C
2
3900P_0402_50V7K

SSATA_ITX_DRX_N0

1
C348

SSATA_ITX_DRX_N0_C
2
3900P_0402_50V7K

SSATA_ITX_DRX_P0

1
C341

SSATA_ITX_DRX_P0_C
2
3900P_0402_50V7K

PD_D[0..15] <31>

LDO3
+RTCVCC
<31> SSATA_ITX_DRX_N0

JP23
D26

<31> SSATA_ITX_DRX_P0

BATT1.1

R488

1
3 1
2

close ICH7

DAN202U_SC70

W=20mils

+
1

BATT1
2

1K_0402_5%

C679
1U_0603_10V4Z

CR2032 RTC BATTERY

SUYIN_060003FA002TX00NL~D

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH7-M(2/4)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

28

of

60

Place closely pin B2

+3VS

I CH_RI#

A28

RI#

SB_SPKR
SUS_STAT#
ITP_DBRESET#

A19
A27
A22

SPKR
SUS_STAT#
SYS_RST#

+3VALW
R172
1
2
8.2K_0402_5%

10K_0402_5%
R173 1
2 LINKALERT#
<38>

150_0402_5%
R221 1
2 ITP_DBRESET#
10K_0402_5%
R219 1
2 OCP#

<7> PM_BMBUSY#
<4>

<15> H_STP_PCI#
<15> H_STP_CPU#

10K_0402_5%
R159 1
2 SPI_CS#
10K_0402_5%
R223 1
2 BT_DET#

<45> EC_FLASH#

1K_0402_5%
R182 1
2 ICH_PCIE_WAKE#

<32> PCI_CLKRUN#

AB18

GPIO0 / BM_BUSY#

B23

H_STP_PCI#
H_STP_CPU#

EC_FLASH#
PCI_CLKRUN#

<34,37> ICH_PCIE_WAKE#
<32,42,44> SIRQ
<44> EC_THERM#

10K_0402_5%
R578 1
2 SPI_MOSI

<44,53>

VGATE

AC20
AF21

GPIO18 / STPPCI#
GPIO20 / STPCPU#

A21

GPIO26

B21
E23

GPIO27
GPIO28

AG18

GPIO32 / CLKRUN#

PCBEEP
<44>

EC_SMI#

EC_SMI#

CLK14
CLK48

AF19
AH18
AH19
AE19

AC1
B2

WAKE#
SERIRQ
THRM#

AD22

VRMPWRGD

AC21
AC18
E21

GPIO6
GPIO7
GPIO8

R136

@ 10_0402_5%

@ 10_0402_5%

GPIO

ICH7_BGA652~D

CLK_14M_ICH
CLK_48M_ICH

C20

ICH_SUSCLK

B24
D23
F22

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

AA4

ICH_POK

AC22

DPRSLPVR

TP0 / BATLOW#

C21

ICH_LOW_BAT#

PWRBTN#

C23

PWRBTN_OUT#

LAN_RST#

C19

LAN_RST#

RSMRST#

Y4

EC_RSMRST#
R514 10K_0402_5%
1
2

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

EC_SCI#
BT_DET#
PCBEEP
LID_OUT#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

@ 4.7P_0402_50V8C

C350
@ 4.7P_0402_50V8C

CLK_14M_ICH <15>
CLK_48M_ICH <15>

SUSCLK

GPIO16 / DPRSLPVR

C740

1 R507
2
100_0402_5%

SLP_S3#
SLP_S4#
SLP_S5#

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#

ICH_PCIE_WAKE# F20
SIRQ
AH21
EC_THERM#
AF20
VGATE

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO11 / SMBALERT#

AC19
U2

8.2K_0402_5%
R209 2
1 ICH_LOW_BAT#
10K_0402_5%
R153 1
WL_ON
2

10K_0402_5%
R590 1
2

OCP#

GPIO

10K_0402_5%
R156 1
2 SPI_MISO

OCP#

PM_BMBUSY#

SYS

SB_SPKR
PAD T25
<4> ITP_DBRESET#

SATA
GPIO

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

SMB

C22
B22
A26
B25
A25

Clocks

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

R539

U6C

2.2K_0402_5%

<15,34,37> ICH_SMBCLK
<15,34,37> ICH_SMBDATA

10K_0402_5%

+3VALW

R220

2.2K_0402_5%
10K_0402_5%

R222
R207

POWER MGT

R208

10K_0402_5%
R123 1
2 SIRQ
8.2K_0402_5%
R124 1
2 PCI_CLKRUN#

CLK_14M_ICH
1

+3VALW
1

+3VALW

Place closely pin AC1

CLK_48M_ICH

T28 PAD
SLP_S3#
SLP_S4#
SLP_S5#

<44>
<44>
<44>

R511
ICH_POK <7,44>
1
2 10K_0402_5%
DPRSLPVR <7,53>

PWRBTN_OUT# <44>
LAN_RST# <44>

CPUSB#
WL_ON
BT_ON#

EC_RSMRST# <44>

EC_SCI#
BT_DET#
PCBEEP
LID_OUT#

<44>
<41>
<40>
<44>

CPUSB#
WL_ON
BT_ON#

<34,44>
<37>
<41>

DPRSLPVR 2

1
R509
@ 100K_0402_5%

Need update symbol

<34>
<34>
<34>
<34>

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

<37>
<37>
<37>
<37>

PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3

2
2

1 C399
1 C396

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

F26
F25
E28
E27

PERn1
PERp1
PETn1
PETp1

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

1 C391
1 C393

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

H26
H25
G28
G27

PERn2
PERp2
PETn2
PETp2

1 C389
1 C387

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

K26
K25
J28
J27

PERn3
PERp3
PETn3
PETp3

M26
M25
L28
L27

PERn4
PERp4
PETn4
PETp4

P26
P25
N28
N27

PERn5
PERp5
PETn5
PETp5

T25
T24
R28
R27

PERn6
PERp6
PETn6
PETp6

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
2

SPI_CS#

SPI_CLK
SPI_CS#
SPI_ARB

P5
P2

SPI_MOSI
SPI_MISO

D3
C4
D5
D4
E5
C3
A2
B3

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

SPI_MOSI
SPI_MISO

<41>

USB_OC#0

<41>
<42>
<42>

USB_OC#3
USB_OC#4
USB_OC#5

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

SPI

R2
P6
P1

PCI-EXPRESS

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

DIRECT MEDIA INTERFACE

U6D
<34>
<34>
<34>
<34>

USB

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V26
V25
U28
U27

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y26
Y25
W28
W27

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA28
AA27

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD25
AD24
AC28
AC27

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_CLKN
DMI_CLKP

AE28
AE27

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_ZCOMP
DMI_IRCOMP

C25
D25

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USB20_N0
USB20_P0
USB20_N1
USB20_P1

USBRBIAS#
USBRBIAS

D2
D1

USBRBIAS

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

<7>
<7>
<7>
<7>

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

<7>
<7>
<7>
<7>

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

<7>
<7>
<7>
<7>

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

<7>
<7>
<7>
<7>

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
R166 24.9_0402_1%
1
2

Within 500 mils

+1.5VS

USB20_N0
USB20_P0
USB20_N1
USB20_P1

<41>
<41>
<46>
<46>

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

<41>
<41>
<42>
<42>
<42>
<42>
<41>
<41>
<34>
<34>

RP20
USB_OC#7
USB_OC#1
USB_OC#2
USB_OC#4

4
3
2
1

5
6
7
8

+3VALW

10K_1206_8P4R_5%
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

R175
10K_0402_5%
USB_OC#6 1
2

R165 22.6_0402_1%
1
2

Within 500 mils

A

ICH7_BGA652~D

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH7-M(3/4)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

29

of

60

+VCCP
U6F

F6

+3VS
2

220U_D2_4VM

+5VS
1

0.1U_0402_16V4Z

R518

C693

D18

C715

C739

0.1U_0402_16V4Z

CH751H-40_SC76

2
0.1U_0402_16V4Z

100_0402_5%

C714

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

ICH_V5REF_RUN
1

C697
0.1U_0402_16V4Z

Place closely pin

D28,T28,AD28.

C729
0.1U_0402_16V4Z

+5VALW +3VALW

R164

D8

CH751H-40_SC76
2

10_0402_5%

ICH_V5REF_SUS
C732
0.1U_0402_16V4Z

+3VS

C743
0.1U_0402_16V4Z

Place closely pin AG28 within 100mlis.

+1.5VS_DMIPLL
R129
1

0.5_0805_1%

2
0_0805_5%

C698

+1.5VS
1

+3VALW
C734
0.1U_0402_16V4Z

0.1U_0402_16V4Z

AG28

+1.5VS

C691
0.1U_0402_16V4Z

Place closely pin AG5.

+3VS
1

+1.5VS
C696
1U_0603_10V4Z

+1.5VS
C742
0.1U_0402_16V4Z

1
T30
T31

PAD
PAD

ICH_AA2
ICH_ Y7

Vcc3_3 / VccHDA

U6

VccSus3_3/VccSusHDA

R7

Vcc3_3[1]
VccDMIPLL

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

V5
V1
W2
W7

+3VALW

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

AA2
Y7

V5REF_Sus

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

Place closely pin AG9.

B27
+1.5VS_DMIPLL

C688
0.1U_0402_16V4Z

C349
10U_0805_10V4Z

R109
1

C352
0.01U_0402_16V7K

+1.5VS_DMIPLLR

+1.5VS

V5REF[2]

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

1
C721

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

A24
C24
D19
D22
G19

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

220U_D2_4VM

+3VS

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

P7

+ C708

+3VALW

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

W5

1U_0603_10V4Z

AE23
AE26
AH26

VccRTC

C711

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

VccSus3_3[1]

C695
1
2

C701
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
2

+3VS
1

C694
0.1U_0402_16V4Z
1
2

C700
0.1U_0402_16V4Z

C690
4.7U_0805_10V4Z

+3VS

+RTCVCC
1

Vcc1_5_A[19]
Vcc1_5_A[20]

AB17
AC17

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

T7
F17
G17

Vcc1_5_A[24]
Vcc1_5_A[25]

AB8
AC8

C741
0.1U_0402_16V4Z

C723
0.1U_0402_16V4Z

+3VALW
C738
0.1U_0402_16V4Z

+3VALW
C720
0.1U_0402_16V4Z

+1.5VS

VccSus1_05[1]

K7

C699 0.1U_0402_16V4Z
ICH_K7
PAD

T32

VccSus1_05[2]
VccSus1_05[3]

C28
G20

ICH_C28
ICH_G20

T26
T29

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

+VCCP

C709
0.1U_0402_16V4Z

ICH_V5REF_SUS

0.1U_0402_16V4Z

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C712
0.1U_0402_16V4Z

+1.5VS
D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C730
0.1U_0402_16V4Z

AD17

U6E

V5REF[1]

C737
0.1U_0402_16V4Z

G10

C731
0.1U_0402_16V4Z

ICH_V5REF_RUN

A1
H6
H7
J6
J7

PAD
PAD
+1.5VS
1

C727
0.1U_0402_16V4Z

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

ICH7_BGA652~D

ICH7_BGA652~D
C375

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH7-M(4/4)

Size Document Number

Custom LA-2841
Date:

Rev
1.0

Thursday, December 15, 2005

Sheet
1

30

of

60

+3VS

1
C464

Pleace near HD CONN

1
C447

2
1U_0603_10V4Z

Pleace near HD CONN

0.1U_0402_16V4Z
1

1
C518

1
C513

2
1U_0603_10V4Z

C482
1000P_0402_50V7K

2
1U_0603_10V4Z

C465
22U_1206_6.3V6M

+3VS

0.1U_0402_16V4Z
1

C524
0.1U_0402_16V4Z

C445

C514
1000P_0402_50V7K

C449

C500
22U_1206_6.3V6M

C460
0.1U_0402_16V4Z

C468
1000P_0402_50V7K

C434
22U_1206_6.3V6M

C457
0.1U_0402_16V4Z

C453
1000P_0402_50V7K

C439
22U_1206_6.3V6M

+5VS

0.1U_0402_16V4Z

Pleace near HD CONN

0.1U_0402_16V4Z
1

1
C485

1
C473

2
1U_0603_10V4Z

C486
0.1U_0402_16V4Z

+5VS

Pleace near HD CONN

JP33
JP31

C505
3900P_0402_50V7K
2

<28> PSATA_IRX_DTX_N0_C
<28> PSATA_IRX_DTX_P0_C

1
2
3
4
5
6
7

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

<28> PSATA_ITX_DRX_P0
<28> PSATA_ITX_DRX_N0

PSATA_IRX_DTX_N0

PSATA_IRX_DTX_P0

C503
3900P_0402_50V7K

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

close SATA connector

+5VS

GND
A+
AGND
BB+
GND

SSATA_ITX_DRX_P0
SSATA_ITX_DRX_N0

<28> SSATA_ITX_DRX_P0
C480
<28> SSATA_ITX_DRX_N0
3900P_0402_50V7K
2
1
<28> SSATA_IRX_DTX_N0_C
2

<28> SSATA_IRX_DTX_P0_C
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1
2
3
4
5
6
7

SSATA_IRX_DTX_N0
SSATA_IRX_DTX_P0

C484
3900P_0402_50V7K

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

close SATA connector

+5VS

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

SUYIN_127059FR022S305ZL
SUYIN_127059FR022S305ZL

Main HDD

2nd HDD

Need update symbol

Need update symbol

Main SATA +5V Default

PD_D[0..15]

Main SATA +5V Default

PD_D[0..15] <28>

CD_AGND <38>
JP25
<38> CDROM_L
<7,27,32,34,37> PLT_RST#

PLT_RST#

2 R217

1 33_0402_5%
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_IOW#
PD _IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
ACT_LED#

<28> PD_IOW#
<28> PD_IORDY
<28> PD_IRQ
<28> PD_A1
<28> PD_A0
<28> PD_CS#1
<43> ACT_LED#
+5VS

PRI_CSEL

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
GND
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
GND
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

CDROM_R <38>
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DREQ <28>
PD_IOR# <28>

PD_DACK#

+5VS

R157
PD_DACK# <28>
100K_0402_5%
1
2
PD_A2
<28>
PD_CS#3 <28>

PDIAG#
PD_A2
PD_CS#3

+5VS

2
2

1
C371
1U_0603_10V4Z

C357
10U_0805_10V4Z

+5VS

C380
0.1U_0402_16V4Z
A

SUYIN_800059MR050S119ZL

R147
470_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

CD-ROM Connector
Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HDD & CDROM

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

31

of

60

+3VS

2
22K_0402_5%

2
1

1
3

PCI_PME# <27,44>

D30
D31
D32

CH751H-40_SC76
1
2 D33
CH751H-40_SC76
1
2 D34
CH751H-40_SC76
1
2 D35
CH751H-40_SC76
1
2 D36

CH751H-40_SC76 1

CH751H-40_SC76 1

CH751H-40_SC76 1

CH751H-40_SC76 1

2
C

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

34
33
32
31
21
22
23
24

MSCLK_SDCLK_SMELWP#

PCI_PAR <27>
PCI_FRAME# <27,36> +VCC_SM_XD
PCI_TRDY# <27,36>
PCI_IRDY# <27>
PCI_STOP# <27>
PCI_DEVSEL# <27>
1
C771
PCI_PERR# <27>
CR@
PCI_SERR# <27>
0.1U_0402_16V4Z
PCI_REQ2# <27>
2
PCI_GNT2# <27>

CLK_PCI_PCM
PCI_RST#
GRST#
R321 1
2
@ 0_0402_5%
CB_PME#

SPKROUT

H3

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

G1
H5
H2
H1
J1
J2
J3

SCL
SDA

G2
G3

R328
R344

2
2

1 7412@ 220_0402_5%
1 7412@ 220_0402_5%

VR_EN#

K2

R320

1 7412@ 220_0402_5%

25
3
29
26
27
28
30
2
38
45
46

SM_CD#
SM_RB#
SDCLK_SMRE#
SDWP#_SMCE#
SMCLE

CLK_PCI_PCM <15>
PCI_RST# <27,33,36,42,44>
PLT_RST# <7,27,31,34,37>

15
14
16
18
19
17
13
20
40
39
1
44

R595 CR@
1 33_0402_5%
2MSD3_SDD3_SMD3
R596 CR@
1 33_0402_5%
2MSD2_SDD2_SMD2
R597 CR@
1 33_0402_5%
2MSD1_SDD1_SMD1
R598 CR@
1 33_0402_5%
2MSD0_SDD0_SMD0
SDWP#_SMCE#
R599 CR@
1 33_0402_5%
2MSBS_SDCMD_SMWE#
MSCLK_SDCLK_SMELWP#
C826 1
SD_CD#

21000P_0402_50V7K

+VCC_SD

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
+VCC_MS
MS_CD#
MSBS_SDCMD_SMWE#
+VCC_SM_XD

XD_CD#

TAITN_R007-N3P-15-S

R315

1 0_0402_5%
1 0_0402_5%
1 0_0402_5%
1 0_0402_5%
1 0_0402_5%
CARD_LED <43>

PCI_PIRQC# <27>
PCI_PIRQD# <27>
PCI_PIRQG# <27>
SIRQ
<29,42,44>
PCI_PIRQE# <27>

+VCC_MS

CARD_LED

7412@
7412@
7412@
7412@
7412@

PCI_RST# 1
2 GRST#
7412@ 0_0402_5%

R389
R602
@ 470_0402_5%

7412@ 10K_0402_5%
1

PCI_CLKRUN# <29>
PCM_SPK

MC_PWRON#

1 1

+3VS
PCM_SPK <38>

2
2
2
2
2

35
43
36
37

SD-DAT3
SD-DAT2
SD-DAT1
5 IN 1 CONN SD-DAT0
SD-WP-SW
SD-CMD
SD_CLK
SD-VCC
NC
SM_WP-IN / XD_WP-IN
SD-CD-SW
SM-WP-SW
SD-CD-COM
#SM_-WE / XD_-WE
#SM-ALE / XD-ALE
MS-DATA0
MS-DATA1
SM-LVD
MS-DATA2
SM-CD-SW
MS-DATA3
SM_-VCC / XD_-VCC
MS-SCLK
#SM_R/-B / XD_R/-B
MS-INS
#SM_-RE / XD_-RE
MS-BS
#SM_-CE / XD_-CE
MS-VCC
#SM_-CD
SM-CD-COM
XD-VCC
SM-CLE / XD-CLE
XD-CD
GND
GND
GND
GND

R329
7412@ 43K_0402_5%

SM_PHYS_WP#
MSBS_SDCMD_SMWE#
SDCMD_SMALE

11
12
6
7
5
10
8
9
4
42
41

SM-D0
SM-D1 / XD-D1
SM-D2 / XD-D2
SM-D3 / XD-D3
SM-D4 / XD-D4
SM-D5 / XD-D5
SM-D6 / XD-D6
SM-D7 / XD-D7

Q24
S @ 2N7002_SOT23

2
G

2
R588
7412@ 43K_0402_5%
+3VS

+3VS
+VCC_MS

CLK_PCI_PCM

PCI7412ZHK_PBGA257
7412@
+VDDPLL

U42

R567
R214

GND
IN
IN
EN#

OUT
OUT
OUT
OC#

8
7
6
5

CR@ 10K_0402_5%

MC_PWRON#

@ 10_0402_5%

1
2
3
4

VSSPLL

Q22
Q19
CR@ 2N7002_SOT23 CR@ 2N7002_SOT23
Q23
S @ 2N7002_SOT23
SD_CD#
2
1
D9
@ CH751H-40_SC76
SM_CD#
2
1
D10
@ CH751H-40_SC76
D29

@ 10_0402_5%
C470

CR@ TPS2041BDR_SO8

C420

PWR_CTRL_1/SM_R/B#
1

@ 10P_0402_50V8J

@ 15P_0402_50V8J

C781 2

1 CR@ 10U_0805_10V4Z

C778 2

1 CR@ 0.01U_0402_16V7K

XD_CD#/SM_PHYS_WP#

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

R358
CR@ 10K_0402_5%

JP32

SUSPEND#

SM_PHYS_WP#R363 1
2
CR@ 0_0402_5%
R362 1
2
CR@ 0_0402_5%
R361 1
2 SM_CD#
@ 0_0402_5%

+VCC_MS
3

J5

R352 1
2
CR@ 0_0402_5%

SD_CD#

Q8
@ 2N7002_SOT23

XD_CD#

R559
1
CR@

2
CB_PME#

XTPBIAS1
XTPA1+
XTPA1XTPB1+
XTPB12 SM_RB#
@ 0_0402_5%

R556
1
2
CR@ 100K_0402_5%

1
@ 10K_0402_5%

CLK_48M_CB

SM_RB#/SC_RFU R3491

R557
1
2
CR@ 100K_0402_5%

R554
1
2
CR@ 100K_0402_5%

near
JP32 pin1
1

R334

<33> SM_RB#/SC_RFU

MS_CD#

R241

L1
K3
K5
L5

R17

AGND
AGND
AGND
R14
U13
U14

Y3
7412@
24.576MHZ_16P_1BG24576CK1A
X_IN

+3VS

2 R249
1 PCI_AD22
7412@ 100_0402_5%

R314
R190
R204
R313
R189
CARD_LED

MC_PWRON#

+VCC_SM_XD

CARD_LED 2
G
2 C823
2 C824
1000P_0402_50V7K
1000P_0402_50V7K

PCLK
PRST#
GRST#
RI_OUT#/PME#

XO
XI

X_OUT

U7
R6
W5
V5
V6
U6
N5
R7
W6
L3
L2

+VCC_SD

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

R374
CR@ 10K_0402_5%

P2
U5
V7
W10

SM_RB#

VCCP
VCCP

R0
R1
TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N
TPBIAS1
TPA1P
TPA1N
TPB1P
TPB1N
CPS

R342 1
2 CPS
7412@ 4.7K_0402_5%

C444 1
2
7412@
10P_0402_50V8J

C/BE3#
C/BE2#
C/BE1#
C/BE0#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#

+3VS

C451 1
2
7412@
10P_0402_50V8J
R298
@ 1M_0402_5%

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

56.2_0603_1%

7412@ R250
2
1

56.2_0603_1%

7412@ R251
2
1

1U_0603_10V4Z

VR_PORT
VR_PORT

U19
P15

P13
P14
U15
AVDD_33
AVDD_33
AVDD_33

XTPA1+
XTPA1XTPB1+
XTPB1-

7412@ R244 7412@ R260

5.1K_0603_1% 56.2_0603_1%
2
1
2
1

<46>
<46>
<46>
<46>

7412@ C428 7412@ R261

270P_0603_50V8J 56.2_0603_1%
2
1

7412@ C423

CLOSE TO CHIP

R18
R19

PCI7412

TEST0
CLK_48
PHY_TEST_MA

1
2

CLOSE TO CHIP

X_OUT
X_IN

1394@ R262
56.2_0603_1%

1
2

1394@ R263
56.2_0603_1%

1394@ C426
1U_0603_10V4Z

1394@ R242
1394@ R265
5.1K_0603_1% 56.2_0603_1%
2
1
2
1

1394@ C427
1394@ R264
270P_0603_50V8J 56.2_0603_1%
2
1

8
7
6
5
GND4
GND3
GND2
GND1

JP28
SUYIN_020204FR004S506ZL

R280 7412@ 6.34K_0402_1%

T18
1
2
T19
XTPBIAS0
R13
XTPA0+
V14
XTPA0W14
XTPB0+
V13
XTPB0W13
XTPBIAS1
W17
XTPA1+
V16
XTPA1W16
XTPB1+
V15
XTPB1W15
CPS
R12

SM_CLE
XD_CD#/SM_PHYS_WP#

M1
M2
M3
M6
M5
N1
N2
N3
P3
R1
R2
P5
R3
T1
T2
W4
W7
R8
U8
V8
W9
V9
U9
R9
V10
U10
R10
W11
V11
U11
P11
R11

SC_PWR_CTRL

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

1
4
3
2
1

MS_CLK/SD_CLK/SM_EL_WP#
MS_BS/SD_CMD/SM_WE#
MS_DATA3/SD_DAT3/SM_D3
MS_DATA2/SD_DAT2/SM_D2
MS_DATA1/SD_DAT1/SM_D1
MS_SDIO(DATA0)/SD_DAT0/SM_D0

G5
SMCLE
B4
A3
2
10_0402_5%
1
2
@ C827 10P_0402_50V8J
P12
CLK_48M_CB
F1
<15> CLK_48M_CB
1
2 R316 P17
+3VS
7412@ 4.7K_0402_5%

4
3
2
1

SD_CD#
MS_CD#
SM_CD#

SD_CLK/SM_RE#
SD_CMD/SM_ALE
SD_DAT0/SM_D4
SD_DAT1/SM_D5
SD_DAT2/SM_D6
SD_DAT3/SM_D7
SD_WP/SM_CE#

XD_CD#/SM_PHYS_WP#1
R607

MC_PWR_CTRL_0
MC_PWR_CTRL_1/SM_R/B#

A4
C5
C6
A5
B5
E6
E7

+3VS

R564

SDCLK_SMRE#
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

CR@ 10K_0402_5%

+3VS

CR@ 10U_0805_10V4Z

SDWP#_SMCE#

15P_0402_50V8J

R566
@47K_0402_5%

+3VS

SDCLK_SMRE#

C825

A7
MSBS_SDCMD_SMWE# E8
MSD3_SDD3_SMD3
B6
MSD2_SDD2_SMD2
A6
MSD1_SDD1_SMD1
C7
MSD0_SDD0_SMD0
B7

CR@ 10U_0805_10V4Z

MSBS_SDCMD_SMWE#
7412@
2 0.1U_0402_16V4Z

@47K_0402_5%

R360
MSCLK_SDCLK_SMELWP# 1
2
CR@ 22_0402_5%

E9
A8
B8

Q44
CR@
1
R565 SI2301BDS_SOT23C782

1
C779

SD_CD#
MS_CD#
SM_CD#

C8
F8

R293
7412@
0.1U_0402_16V4Z
7412@ 0_0805_5%
1
1
C435
C448

U18B

MC_PWRON#
PWR_CTRL_1/SM_R/B#

7412@
K1 C452 1U_0603_10V4Z
K19
7412@
1U_0603_10V4ZC467
P1
W8

VDDPLL_33
VDDPLL_15

1U_0603_10V4Z
C433

7412@
0.01U_0402_16V7K

7412@

C429

7412@
10U_0805_10V4Z
C432

2
D

Q43
CR@
SI2301BDS_SOT23

+VCC_SM_XD

<27,36> PCI_CBE#[0..3]

+VCC_MS

PCI_CBE#[0..3]

+3VS

+VCC_SD

PCI_AD[0..31]

<27,36> PCI_AD[0..31]

+3VS_CBVCCP
1

+VCC_MS

7412@ 0_0805_5%

+VCC_MS

R234

L23
1
2
7412@ MBK160808_0603
+VDD_PLL2
1 +VDDPLL
C458
7412@ 0.1U_0402_16V4Z

+3VS_CBPLL

+3VS

Title

Compal Electronics, Inc.

PCI7412

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

32

of

60

R343
S1_A16_C 1
2
7412@ 33_0402_5%

C443
1

S1_CD1#

S1_REG#
S1_A12
S1_A8
S1_CE1#

E13
E18
H18
L17

CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16
S1_RDY#

H14
E19
G15
F17
G18
F19
H15
G19
C12
C14
G17
A12
A11
F18
E12

CPAR/A13
CFRAME#/A23
CTRDY#/A22
CIRDY#/A15
CSTOP#/A20
CDEVSEL#/A21
CBLOCK#/A19
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/A16
CINT#/READY(IREQ#)

S1_RST

C15

CRST#/RESET

S1_BVD2

B12

CAUDIO/BVD2(SPKR#)

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

N15
B11
A13
B16

CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#

E10

A_USB_EN#

C488
1

S1_CD2#

7412@
0.1U_0402_16V4Z

7412@
0.1U_0402_16V4Z
C469

7412@
0.1U_0402_16V4Z
C478

7412@
0.1U_0402_16V4Z
C436

7412@
0.1U_0402_16V4Z
C481

F6
F9
F12
F14
J6
J14
L6
L14
P6
P8
P10

PCI 7412

F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

B9
A9
C9

DATA/VD2/VPPD1
CLOCK/VD1/VCCD0#
LATCH/VD3/VPPD0

7412@ 100P_0402_50V8J

7412@ 100P_0402_50V8J

U20
CB_DAT
CB_CLK
CB_LATCH
PCI_RST#

3
4
5
12
15
21

DATA
CLOCK
LATCH
RESET#
OC#
SHDN#

+S1_VPP

8
19

AVPP
NC0

+S1_VCC

9
10
17
18

<27,32,36,42,44> PCI_RST#

RSVD/D2
RSVD/VD0/VCCD1#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

B10
C4
D1
E1
E2
E3
F2
F3
F5
G6
H17
M19

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

A2
A17
A18
B1
B2
B3
B17
B18
B19
C1
C2
C3
C16
C17
C18
C19
D2
D3
D17
D18
E5
N14
P18
T3
T17
U1
U2
U3
U4
U12
U16
U17
U18
V1
V2
V3
V4
V12
V17
V18
V19
W2
W3
W12
W18

CB_DAT
CB_CLK
CB_LATCH

S1_D2
SM_RB#/SC_RFU

SM_RB#/SC_RFU <32>

12V
12V

20
7

NC3
3.3V

14
13

NC4
5V
5V

24
2
1

AVCC
AVCC

GND

11

NC1
NC2

NC5
NC6
NC7
NC8

23
22
16
6

+3VS
D

JP10

+S1_VCC

+3VS

7412@TPS2220ADBRG4_SSOP24

+3VS
43K_0402_5%
R350 1
2
@ 43K_0402_5%
R351 1
2
7412@

Near to PCMCIA slot.

S1_A18
S1_D14

+5VS

7412@ 0.1U_0402_16V4Z

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

C495

C10
A10
F11
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19
J17
J15
J18
K15
K17
K18
L15
L18
L19
M17
M18
N19
M15
N17
N18
P19

7412@ 0.1U_0402_16V4Z
C523

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

+3VS

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U18A

A15
J19

2 7412@
0.1U_0402_16V4Z

VCCB
VCCB

2
7412@
0.1U_0402_16V4Z

7412@
0.1U_0402_16V4Z
C483

C461

1
C489

C487

7412@
0.1U_0402_16V4Z
C490

C780
7412@10U_0805_10V4Z

CardBus Power Switch

+S1_VCC

C491
7412@
10U_0805_10V4Z

C492
7412@
0.1U_0402_16V4Z

+S1_VPP

C494
7412@
10U_0805_10V4Z

C493
7412@
0.1U_0402_16V4Z

7412@ PCI7412ZHK_PBGA257

69
70
71
72

GND
GND
DATA3
CD1#
DATA4
DATA11
DATA5
DATA12
DATA6
DATA13
DATA7
DATA14
CE1#
DATA15
ADD10
CE2#
OE#
VS1#
ADD11
IORD#
ADD9
IOWR#
ADD8
ADD17
ADD13
ADD18
ADD14
ADD19
WE#
ADD20
READY
ADD21
VCC
VCC
VPP
VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24
ADD7
ADD25
ADD6
VS2#
ADD5
RESET
ADD4
WAIT#
ADD3
INPACK#
ADD2
REG#
ADD1
BVD2
ADD0
BVD1
DATA0
DATA8
DATA1
GND DATA9
GND DATA2
GND DATA10
GND
WP
CD2#
GND
GND

1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21
S1_VCC

+S1_VCC

S1_VPP
S1_A16_C
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#

+S1_VPP

SANTA_130609-1_LT

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

PCI7412

Size Document Number

Custom LA-2841
Date:

Rev
1.0

Thursday, December 15, 2005

Sheet
1

33

of

60

Express Card Power Switch

EXP@
C471
0.1U_0402_16V4Z
2
1
1

5
6

0.1U_0402_16V4Z
2 R180

+3VALW
<29,44> CPUSB#

21

3.3Vaux_in

18
19

1.5Vin1
1.5Vin2

1EXP@ 100K_0402_5%
14 CPUSB#
15 CPPE#
SUSP#
4 STBY#
SYSON
3 SHDN#
PLTRST#
2 SYSRST#

11

close to JP36
<29>
<29>

USB20_N7
USB20_P7

17_EXP@

0_0402_5%
1
2
1
2

<29,37> ICH_PCIE_WAKE#

R391 1

USB7USB7+
CPUSB#
ICH_SMBCLK
ICH_SMBDATA

+1.5VS_PEC
+1.5VS_PEC

+3V_PEC

17_EXP@
0_0402_5%

PCIE_PME#_R
PERST#

+3VS_PEC
CLKREQC#
CPUSB#
CLK_PCIE_NC1#
CLK_PCIE_NC1

<15> CLKREQC#
<15> CLK_PCIE_NC1#
<15> CLK_PCIE_NC1

PCIE_RXN1
PCIE_RXP1

<29> PCIE_RXN1
<29> PCIE_RXP1

PCIE_TXN1
PCIE_TXP1

<29> PCIE_TXN1
<29> PCIE_TXP1

1.5Vout1
1.5Vout2

16
17

OC#

23

RCLKEN
PERST#

22
9

R307 @ 0_0402_5%
EXPCRD_RST#
2
1
PERST#

EXPCRD_RST# <44>

EXP@
TPS2231PWPR_PWP24

JP14

0_0402_5%

<15,29,37> ICH_SMBCLK
<15,29,37> ICH_SMBDATA

Aux_out

20

NC1
NC2
NC3
NC4
NC5

2N7002_SOT23
Q51

17_EXP@
USB20_N7
R413
USB20_P7
R412

7
8

+1.5VS_PEC

GND

EXP@

3.3Vout1
3.3Vout2

1
10
12
13
24

<7,27,31,32,37> PLT_RST#

<44,45,47,51,52,54> SUSP#
<44,47,51> SYSON
1

3.3Vin1
3.3Vin2

+3V_PEC

EXP@
C454
+3VALW
0.1U_0402_16V4Z
2
1
+1.5VS
EXP@
C466
2
1
+3VS

+3VS_PEC

U16

+3VS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Near to Express Card slot. 17

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

+3VS_PEC

+3V_PEC

4.7U_0805_10V4Z

1
17_EXP@
C530
0.1U_0402_16V4Z

1
C532

17_EXP@
2

17_EXP@
C542
0.1U_0402_16V4Z

C543 17_EXP@
4.7U_0805_10V4Z

+1.5VS_PEC
4.7U_0805_10V4Z
1
17_EXP@
C558
0.1U_0402_16V4Z

1
C555

17_EXP@
2

GND
GND
FOX_1CH4110C

JP13
USB20_N7
USB20_P7
CPUSB#
ICH_SMBCLK
ICH_SMBDATA
+1.5VS_PEC
+1.5VS_PEC
+3V_PEC

PCIE_PME#_R
PERST#

+3VS_PEC
<15> CLKREQD#
<15> CLK_PCIE_NC2#
<15> CLK_PCIE_NC2
<29> PCIE_RXN2
<29> PCIE_RXP2
<29> PCIE_TXN2
<29> PCIE_TXP2

CLKREQD#
CPUSB#
CLK_PCIE_NC2#
CLK_PCIE_NC2
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Near to Express Card slot. 15.4

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

+3VS_PEC

+3V_PEC
4.7U_0805_10V4Z

1
15_EXP@
C528
0.1U_0402_16V4Z

1
C529

15_EXP@
2

15_EXP@
C537
0.1U_0402_16V4Z

C545
15_EXP@
4.7U_0805_10V4Z

+1.5VS_PEC
4.7U_0805_10V4Z
1
15_EXP@
C554
0.1U_0402_16V4Z

1
C553

15_EXP@
2

GND
GND

FOX_1CH4110C

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Express Card

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

E

34

of

60

R36
300_0603_5%
1
2

ACTLED#
R583
75_0402_5%
1
2

+3VALW

RJ45_GND
R561
110_0402_1%

TDN
15 mil

2
1
L31
BLM11A121SPT_0603

R43
300_0603_5%
LINK_LED100# 1
2

PR4+
PR2-

PR3-

PR3+

MDO1+

PR2+

MDO0-

PR1-

MDO0+

PR1+

+3VALW

RDP

R606
@ 110_0402_1%

10U_0805_6.3V4Z
C766

0.1U_0402_16V4Z
C769

0.1U_0402_16V4Z
C768

1
R558

2
200_0402_5%

JRXD2
JRXD1
JRXD0
JRSTSYNC

37
35
34
42

LAN_RXD2
LAN_RXD1
LAN_RXD0
LAN_RSTSYNC

LAN_RXD2 <28>
LAN_RXD1 <28>
LAN_RXD0 <28>
LAN_RSTSYNC <28>

JTXD2
JTXD1
JTXD0
JCLK

45
44
43
39

LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_JCLK

LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_JCLK

ACTLED#
LINK_LED100#

19
23

VCCR
VCCR

8
13
18
24
48
33
38
3
6
20
22

VSS
VSS
VSS
VSS
VSS
VSSP
VSSP
VSSA
VSSA2
VSSR
VSSR

28
30
29
21

ISOL_TI
ISOL_TCK
ISOL_EXEC
TESTEN

X1

41

ADV10

X2

TOUT

<28>
<28>
<28>
<28>

RDN
RDP

8
7
6

TDTD+
CT

TXTX+
CT

9
10
11

MDO0MDO0+
MCT0

3
2
1

CT
RDRD+

CT
RXRX+

14
15
16

MCT1
MDO1MDO1+

RBIAS100

R562

2 619_0402_1%

RBIAS10

R563

2 619_0402_1%

46

LAN1_XO

Green LED-

13

Green LED+

MDO0MDO0+

MDO1MDO1+

R171
<46>
75_0402_5%
<46>
2
1

C414
RJ45_GND 2

1000P_1206_2KV7K

2
1
R170
<46>
75_0402_5%
<46>

close to U12

RDP
R560
110_0402_1%

26
5

10

NS0013_16P

@
1

0.01U_0402_16V7K

+3V_LAN

31
32
27

0.01U_0402_16V7K

R555
0_0603_5%

SPDLED#
ACTLED#
LILED#

14

SHLD1

RDN

RDN

C777
2

22P_0402_50V8J
Y6
25MHZ_20P_1BG25000CK1A

47
LAN1_XI

82562GT_SSOP48

0.1U_0402_16V4Z
C770

0.1U_0402_16V4Z
C775

0.1U_0402_16V4Z
C773

0.1U_0402_16V4Z
C772

TDP
TDN
RDP
RDN

SHLD2

U12

TDN
TDP

C757

0.1U_0402_16V4Z
C774

VCC
VCC
VCCP
VCCP
VCCA
VCCA2
VCCT
VCCT
VCCT
VCCT

TDP
TDN
RDP
RDN

C756

+3VLAN

10U_0805_6.3V4Z
C767

10
11
15
16

15

CONN@ SUYIN_100073FR012S100ZL

R582
@ 0_0402_5%

2
U41

1
25
36
40
2
7
9
12
14
17

16

SHLD3

+3VLAN

+3VLAN

SHLD4

close to U41chip(Intel rule)

PR4-

R584
75_0402_5%
1
2

+3VLAN

Amber LED+

7
MDO1-

TDP

Amber LED-

11
8

close to U41chip(Intel rule)

+3VALW

JP19
12

C776
1
2
22P_0402_50V8J

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

82562EZ LAN

Size Document Number

Custom LA-2841
Date:

Rev
1.0

Thursday, December 15, 2005

Sheet
1

35

of

60

Port 80 Debug Card Connector

JP27
D

<27,32> PCI_CBE#0
<27,32> PCI_AD6
<27,32> PCI_AD4
<27,32> PCI_AD2
<27,32> PCI_AD0
<27,32> PCI_AD1
<27,32> PCI_AD3
<27,32> PCI_AD5
<27,32> PCI_AD7
<27,32> PCI_AD8
<27,32> PCI_CBE#1
<27,32> PCI_CBE#2
<27,32> PCI_CBE#3

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

<15> CLK_PCI_MINI
+5VS
<27,32,33,42,44> PCI_RST#
<27,32> PCI_FRAME#
<27,32> PCI_TRDY#
<27,32> PCI_AD9

@ HEADER 20

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Debug port

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

36

of

60

Mini-Express Card(Slot 1-WLAN)

2

1 C608
0.1U_0402_16V4Z

JP18

C797 1

@ 0.1U_0402_16V4Z

WL_ON
<29>
PLT_RST# <7,27,31,32,34>

PLT_RST#
+3VALW
ICH_SMBCLK
ICH_SMBDATA

+3VS
ICH_SMBCLK <15,29,34>
ICH_SMBDATA <15,29,34>

47K

D2
2

LED_WLANOUT#

10K

LED_WLAN_OUT# 1

WLED#
Q48

DTA114YKA_SC59
BAS16_SOT23

MOLEX_67910-0002

<29> PCIE_TXN3
<29> PCIE_TXP3

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

<29> PCIE_RXN3
<29> PCIE_RXP3

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

+1.5VS
1

R592
470_0402_5%
2
1

WL_LED# <16,42>

2
G
Q49
S
2N7002_SOT23
3

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

+3VS

2
4
6
8
10
12
14
16

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

2
4
6
8
10
12
14
16

0.1U_0402_16V4Z

2 100_0402_5%

1
3
5
7
9
11
13
15

0.1U_0402_16V4Z
C167

<15> CLK_PCIE_MCARD#
<15> CLK_PCIE_MCARD

1 R600

1
3
5
7
9
11
13
15

C78

<29,34> ICH_PCIE_WAKE#
<41> WL_PRIORITY
<41> BT_PRIORITY
<15> CLKREQA#

R593
100K_0402_5%

R594
100K_0402_5%

2
G
Q50
S
2N7002_SOT23
3

<41> WIRELESS_LED_BT

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Mini Card

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

E

37

of

60

+3VAMP_CODEC
+VDDA_CODEC
U26

W=40Mil

Q29
Q28
MMBT3904_SOT23
MMBT3904_SOT23

DELAY

R422
560_0402_5%
2 1
2

(3.33V)

250mA

10K_0402_5%

SENSE or ADJ

CNOISE

GND

R385 7

ERROR
SD

1
2
R392
47K_0603_1%

R403
27K_0603_1%

1
C565

SI9182DH-AD_MSOP8

C533
1U_0603_10V4Z

@ C538
0.1U_0402_16V4Z

0.01U_0402_16V7K

SB_SPKR <29>

@ C502
0.1U_0402_16V4Z
1
2

For Layout:
Place decoupling caps near the
power pins of SmartAMC
device.

R407
R158
R421
R151

1
1
1
1

2
2
2
2

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

13
10
8
7

BCLK
SYNC
SDI
SDO

43

PCBEEP

MONO_INR

<40,42,46>

25
35
AVDD1
AVDD2

VREF_FILT
VREF
VC

DVSS1
DVSS2
DVSS3
VSUB

23
19
18

R387
2.2K_0402_5%

GND

GNDA

C539 1
C540 1
+CODEC_REFF
+CODEC_REFC

MIC_INR
MIC_INL

2 10U_0805_10V4Z
2 10U_0805_10V4Z

MIC_R
MIC_L
MICBIAS_F
MICBIAS_C
MICBIAS_B

26
27
20
21
22

CD_L
CD_GND
CD_R

28
29
30

CDROM_RC_L
C DGNDA
CDROM_RC_R

PORT-A_L
PORT-A_R

40
39

LINE_OUTL
LINE_OUTR

PORT-B_L
PORT-B_R

38
37

PORT-C_L
PORT-C_R

34
33

DOCK_LOUTL
DOCK_LOUTR
C541
R380
DOCKMIC 1
2DOCK_MICR2

PORT-D_L
PORT-D_R

32
31

EAPD
SPDIF_OUT

45
44

EAPD
SPDIFO

SENSEA
SENSEB

41
42

SENSEA
SENSEB

C536 2
C535 2
C534 2

MIC_R
MIC_L

LINE_OUTL <40>
LINE_OUTR <40>

<42>
<42>

CDROM_R_L
CD_GNA
CDROM_R_R

1 2.2U_0603_6.3V4Z
1 2.2U_0603_6.3V4Z
1 2.2U_0603_6.3V4Z

R377 1
R376 1
R375 1

CDROM_L <31>
CD_AGND <31>
CDROM_R <31>

DOCK_MIC <46>

2 R384
1
2K_0402_5%
SPDIFO

DOCK_MICR

1 R388
2
2.2K_0402_5%

+CODEC_REFC

<42,46>
DOCK_LOUTR C521 1

1 R356

DOCK_LOUT_R

DOCK_LOUT_R <46>

150U_D2_6.3VM
33_0805_5%
DOCK_LOUTL C520 1
2
1 R355
2 DOCK_LOUT_L

R414
SENSEA

2 @ 6.8K_0402_5%
2 0_0402_5%
2 @ 6.8K_0402_5%

18K_0402_5%

10U_0805_10V4Z

1
2
20K_0402_5%

HP_DET# <40>

150U_D2_6.3VM

DOCK_LOUT_L <46>

33_0805_5%
R354

R415
1
2
10K_0402_5%

CX20551-22_TQFP48

2
5
46
6

0.1U_0402_16V4Z
C562

0.1U_0402_16V4Z
C549

1U_0603_10V4Z
C547

0.1U_0402_16V4Z
C548

REF_FILT
VREF
VC
1

XTALIN
XTALOUT

15
16

R386
2.2K_0402_5%

1K_0402_5%
R410
1.5K_0402_5%

SENSEB

R405
1
2
5.1K_0402_5%

R393
0_0402_5%

R357

JACK_DET# <46>
2

DIBN
DIBP
PWRCLKP
PWRCLKN

GNDA

R379
6.8K_0402_5%
2
1

47
48
3
4

@ R300
0_1206_5%
1
2

+CODEC_REFF

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2
2
2
2

R152
10K_0402_5%

R149
10K_0402_5%

1
1
1
1

R423
0_1206_5%
1
2

R381
0_0402_5%
2
1

ACZ_BITCLK
ACZ_SYNC
ACZ_SDIN0
ACZ_SDOUT

R418
R417
R420
R419

VSSCK

<28>
<28>
<28>
<28>

2
C570
150P_0402_50V8J

RST#

@C516
0.1U_0402_16V4Z
1
2

+VDDA_CODEC

R378
6.8K_0402_5%
2
1

<39> DIB_DATAN
<39> DIB_DATAP

<39> PWRCLKP
<39> PWRCLKN

11

R404
0_0805_5%
1
2

ACZ_RST#

<28,44> ACZ_RST#

17

C571
150P_0402_50V8J

AVSS1
AVSS2

24
36

DVDD1
DVDD2
DVDD3

C559
1U_0603_10V4Z

U27

C546
0.1U_0402_16V4Z

C564
0.1U_0402_16V4Z

14

VDDCK

+3VAMP_CODEC

1
9
12

C568
0.1U_0402_16V4Z

C569
0.1U_0402_16V4Z

C566
0.1U_0402_16V4Z

C560
10U_0805_10V4Z

C567
0.1U_0402_16V4Z

+3VDD_CODEC

R401
0_0805_5%
1
2

+3VALW

@ C519
0_0402_5%
1
2

R416
560_0402_5%
1
2 2

R409
5.1K_0402_5%
2

PCM_SPK

<32>

MONO_INR <40>

VOUT

MONO_IN1

VIN

MONO_IN

C563
1U_0603_10V4Z
1
2 MONO_INR

R411
0_0402_5%
1
2

R408
10K_0402_1%

C526
0.1U_0402_16V4Z

C504
10U_0805_10V4Z

+5VS

1K_0402_5%

MIC_DET <42>

+3VS

JACK_DET#

PORT-A

ON

PORT-B
OFF

Disable

EQ

NC

ON

OFF

Disable

NC

OFF

ON

Disable

R591
100_0402_5%
1

HP_DET#

MIC_DET

ON

PORT-C

PORT-F

ON

OFF

NC

OFF

ON

OFF

Enable

NC

NC

MUTE_LED <42,46>
EAPD

S Q47
2N7002_SOT23

2
G

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMOM_codec

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

E

38

of

60

MTP28

MTP52

VDD
MTP26

MTP59

BR908_CC
1

MC928

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8

2
0_0402_5%
MR924
MTP61

PRI

SEC

@ 30U_82154R_1%_1:1.67
MC974
@ 0.001U_0402_50V7M

@ HEADER8
MJ1B
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8

MC944

24

1
2

DIB_P

27

DIB_N2

28

DIB_N

MTP62

MC976

2
2
0.001U_0402_50V7M
0.1U_0402_10V6K
AGND_LSD

Vc

VRef

8
22
25

NC1
NC2
NC3

29

PADDLE

AGnd

DVdd

1
DIB_P2

Vref_LSD
MC940
1U_0603_6.3V6M
MTP63
1
1
1

18

Vc_LSD

TAC2
TRDC

12

EIC

11

RXI

GPIO1

RBias

VZ

10

EIO

17

2
1
E&T_3800-02

MTP42

2
4

MJ1

PWR+

EIF

16

TXO

14

TXF

13

CX20493-58_QFN28

1 3

MTP73

MJ2

MTP65

MR938
110_0603_5%

MTP31

MR928
27_0805_5%
2

DIB_N1

MT922

MR922
0_0402_5%
2

19

2 10P_1808_3KV

MTP25

RAC2

DIB_P1

20

MTP41

MC924 1

AGND_LSD

TAC1

MTP72

2 10P_1808_3KV

1 MTP35
1 MTP38
MFB902
RING_2
MOD_RING
1
2
1 MTP39
MR902
MMZ1608D301BT_0603
1M_0805_5%
MC902
RAC1
MC906
1
2 RAC1/RING
1
2 0.033U_1206_100V7K
1
470P_1808_3KV
MC904
TAC1
MBR904
2
1 TAC1/TIP
1
2 0.033U_1206_100V7K
MMBD3004S_SOT23
1M_0805_5%
2
MTP34
MR904
TIP_2
1
MTP40 1
TRDC
MR906 1
2 6.8M_0805_5%
1
MTP33
1
MC958
MC918
AGND_LSD
GND
1
1 MTP32
EIC
1
2
0.1U_0603_16V7K
MBR906
MC908
0.015U_0603_25V7K 2
MR910
MMBD3004S_SOT23 470P_1808_3KV
2
237K_0805_1%
AGND_LSD
RXI 1
RXI-1
2
1 MTP71
MFB904
TIP_2
MOD_TIP
1
2
1 MTP70
MMZ1608D301BT_0603
AGND_LSD
RBias 1
MR9542
59K_0402_1%
1
2 MC966
MTP69
MC910
0.01U_0805_100V7M
VZ 1 1 MR908 2
BRIDGE_CC
1
2
0.047U_1206_100V7K
348K_0805_1%
AGND_LSD
MTP68
MTP67
C
1
EIO 1
MQ902
2
B
PMBTA42_SOT23
Use 59K_0402_1% for MR954
E
EIF
MQ904
C
1
TXO
MQ906
2
B
PMBTA42_SOT23
FZT458TA_SOT223
E
MTP66
1
TXF
1 MTP64
1

1
MC922 1

<38> DIB_DATAN

AVdd

1
<38> DIB_DATAP

21

MTP30
PWR+
MTP60

Check 0.047u or 10p cap

C906 and C908 must be Y3 type

Capacitors for Nordic
Countries only

MTP37

30U_82154R_1%_1:1.67
MTP27

CLK

RAC1

DGnd

SEC

26

MTP36

DGND_LSD

23

PRI

MC970
0.1U_0402_10V6K

DC_GND

MTP24

PCLK

1
2
MMZ1608D301BT_0603

1
MBR908B
BAV99DW-7_SOT363

15

PWRCLKP

MC962
47P_0603_50V8J

<38>

MFB906

MTP58

MU902

MRV902
TB3100M-13-01_SMB

MTP23

AGND_LSD

PWRCLKN

MR932
MC926
15K_0402_5%
10P_0402_50V8J
1
2CLK2 1
2 CLK

<38>

4BR908_AC1
1

MT902

MC978
0.1U_0402_10V6K
2

VDD
1

MC930
2.2U_0805_10V6K

1
MTP29

MTP22

MBR908A
BAV99DW-7_SOT363

0.1U_0402_10V6K

1
2

@ HEADER8
GND

MTP49

AGND_LSD
DGND_LSD AGND_LSD
AGND_LSD

Compal Secret Data

Security Classification
Issued Date

AGND_LSD

2005/03/10

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

AMOM_modem

Size Document Number

Custom LA-2841
Date:

Thursday, December 15, 2005

Rev
1.0
Sheet

39

of

60

+5VAMP

R322
0_1206_5%
1
2

0.1U_0402_16V4Z

1
C462
10U_0805_10V4Z

+5VS

HEADPHONE OUT/LINE OUT

C479
2

Gain Settings

C501
2

GAIN0

GAIN1

SE/BTL#

Av(inv)

0.1U_0402_16V4Z

C509 1

HP_C_OUTR

20

2 0.47U_0603_16V7K

19

RHPIN
RIN

LOUTLOUT+
ROUTROUT+

9
4
16
21

SPKLSPKL+
SPKRSPKR+

SPKL+

<42>

SPKR+

<42>

10 dB

LHPIN

LLINEIN

HP/LINE#

U45
PCBEEP

+5VS

1
2
3

6
5
4

IN
NO
V+
COM
GND
NC

C477 1

2 0.47U_0603_16V7K

14
22

<44> EC_MUTE#

17

GAIN1
GAIN0
PC-BEEP
BYPASS

<38> MONO_INR

21.6 dB

4.1 dB

@ R368
100K_0402_5%

JP11

11

SHUTDOWN#

PI5A4599ACEX

15.6 dB

3
2

GND1
GND2
GND3
GND4

<29>

R371
100K_0402_5%

1
12
13
24

@ R373
100K_0402_5%

C511
0.1U_0402_16V4Z

TPA0312PWPRG4_TSSOP24

R364
100K_0402_5%

SPKL+
SPKLSPKR+
SPKR-

1
2
3
4

+5V

+5VS

1
2
3
4

ACES_85205-0400
C496
47P_0402_50V8J

HP_C_OUTL

HP_DET

15

2 0.047U_0603_16V7K LINE_C_OUTL

SE/BTL#

2 0.47U_0603_16V7K

C507 1

LIN

C508 1

10

<38> LINE_OUTL

2 0.47U_0603_16V7K

C510 1

+5VS

C499
47P_0402_50V8J

2 0.47U_0603_16V7K

6 dB
* 10 dB

C498
47P_0402_50V8J

C476 1

RLINEIN

C497
47P_0402_50V8J

2 0.047U_0603_16V7K LINE_C_OUTR 23

PVDD2
PVDD1

C475 1

VDD

U21
<38> LINE_OUTR

18
7

R353
10K_0402_5%
R345
10K_0402_5%

HP_DET
D
Q13

HPDET#

2
G
3

2N7002_SOT23 S

HPDET# <42>

+5V
C785
1

U44
74AHCT1G125GW_SOT353-5

1
4

OE#

HP_DET#

<38>

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMP & Audio Jack

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

E

40

of

60

+5V
+USB_VCCB

U38
3
4

0.1U_0402_16V4Z

VIN
VOUT
VIN/CE VOUT

1
5

C754
2
1

R542

GND
RT9701PBL_SOT25

10K_0402_5%
USB_OC#0

1 R543
2
0_0402_5%

USB_OC#0 <29>

USB_OC#3

USB_OC#3 <29>

R544
20K_0402_5%

USB CONNECTOR (Left side)

JP26

5
6
7
8

USBP3+
USBP3-

R523 1
R532 1

W=40mils

GND
GND
GND
GND

SUYIN_020122MR008S573ZR

D1+

D2+

GND

VCC

D2-

D1-

1
+
2

USBP3-

<29>

BT_ON#
1

BT CONNECTOR

U9
USBP0+

2 0_0603_5% USB20_P3
USB20_P3 <29>
2 0_0603_5% USB20_N3
USB20_N3 <29>
+USB_VCCB
C408
100U_D2_10VM

9
10
11
12

5
6
7
8

C394
0.1U_0402_16V4Z

W=40mils
1

1
2
3
4

C397
1000P_0402_50V7K

C400
1000P_0402_50V7K

1
2
3
4

2 0_0603_5% USBP0+
2 0_0603_5% USBP0-

C401
0.1U_0402_16V4Z

C736
100U_6.3V_M

USB20_P0 R535 1
USB20_P0
USB20_N0 R537 1
USB20_N0
+USB_VCCB
1
1
C789
150U_D_6.3VM

<29>
<29>

+USB_VCCB

R541
100K_0402_5%
G

USBP0-

@ IP4220CZ6_SO6

USBP3+

1 +3V_BT

3
1

C108
1U_0603_10V4Z
1
2

C118
1U_0603_10V4Z

+3VALW

AO3419_SOT23
Q2
2
JP6

<29> USB20_P6
<29> USB20_N6
<37> WIRELESS_LED_BT
<37> WL_PRIORITY

1 R601
<37> BT_PRIORITY
<29> BT_DET#

USB20_P6
USB20_N6
WIRELESS_LED_BT
2 100_0402_5%
BT_DET#

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8

ACES_87213-0800
C808
@ 0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

C611
0.1U_0402_16V4Z

2005/03/10

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

Bluetooth & USB CONN.

Size Document Number

Custom LA-2841
Date:

Thursday, December 15, 2005

Rev
1.0
Sheet

41

of

60

D38
KSO2 1

D39

KSO7

Power BTN

KSI1 1

5 KSO9

D11
DAN202U_SC70

INT_KBD CONN.( TYPE "D" KB)

R396
1

ON/OFF#

3
2

ON/OFFBTN#

100K_0402_5%
2
LDO3
ON/OFF# <44>

1
1

<44>

KSO_D_17

KSO6 1

5 KSO12

KSI4 1

5 KSO0

KSO3 3

4 KSO13

KSI5 3

NZQA5V6AXV5T1_SOT533-5
D42
KSO141

4 KSI2

NZQA5V6AXV5T1_SOT533-5
D43
5 KSO15

KSI3 1

5 KSO1

4 KSO10

<44,50>

EC_ON

EC_ON

R603
2
1
0_0402_5%

1
C544

D12
RLZ20A_LL34

1000P_0402_50V7K

R604
@ 0_0402_5%

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

2
G

Q25
@ 2N7002_SOT23

ACES_85201-2405

KSO113

R383
4.7K_0402_5%

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

Q26
DTC124EK_SC59

KSO5 3

LDO5

Consumer IR

4 KSI0

ACES_85201-2605
CONN@

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

JP4

EC_PWR_ON# <48>

LDO3

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

NZQA5V6AXV5T1_SOT533-5
D41

NZQA5V6AXV5T1_SOT533-5
D40

C809
0.1U_0402_16V4Z

JP8

KSO[0..16] <44>

KSI7
KSI0
KSI5
KSI1
KSI4
KSI6
KSI3
KSI2
KSO1
KSO2
KSO4
KSO0
KSO16
KSO5
KSO6
KSO3
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO_D_17

ESD

15.4 ( TYPE "C" KB)

4 KSI6

KSI7 3

KSO8

KSO4 3

KSO[0..16]

<44>

KSI[0..7]

KSI[0..7]

NZQA5V6AXV5T1_SOT533-5
D44

NZQA5V6AXV5T1_SOT533-5

C442
0.1U_0402_10V6K

+5V
KSO161

@
2

KSO_D_173

CIR@ R569
100_0402_5%

TP to MB CONN(15.4)

1
<44>
<44>
2

1
2
3
4
5
6
7
JP7 8
ACES_87152-0807

CIR@
C784
10U_0805_10V4Z

TP_DATA
TP_CLK

TP_DATA
TP_CLK

<44,46>

CIR@ C783
0.1U_0402_10V6K
U43 CIR@
3
4

CIR_ IN

CIR_IN

Vs
OUT

GND
GND

1
2

TSOP36236TR_4P

R612
10K_0402_5%
1
2

LDO3

NZQA5V6AXV5T1_SOT533-5

D45

Switch board conn

JP5

JP15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

FOR LPC SIO DEBUG PORT

+5VS

PWR_ACTIVE#

<44> PWR_ACTIVE#
+5VALW
<43,44> PA_LED_ALW
<43> PR_LED_ALW
+5V
<43> PA_LED
<43> PR_LED
+5VS
<43> PA_LED_VS
<43> PR_LED_VS
+3VALW

PA_LED_ALW
PR_LED_ALW
PA_LED
PR_LED
PA_LED_VS
PR_LED_VS

+3VS

LPC_AD[0..3] <28,44>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#

LPC_FRAME# <28,44>
LPC_DRQ#0 <28>
PCI_RST# <27,32,33,36,44>

VOL_DWN#

KSI0 1

<29>

KSI3

KSI1 3

<29>

4KSO_D_17

USB_OC#4

USB_OC#4

L32
NUP5120X6T1_SOT563-6

<38,46> SPDIFO

NUMLED# C795

2 100P_0402_50V8J

C796

2 100P_0402_50V8J

+5VALW

JP9

WL_LED#
LID_SW#
MUTE_LED
PWR_ACTIVE#
PA_LED_ALW
PR_LED_ALW
PA_LED
PR_LED
PA_LED_VS
PR_LED_VS

C810
C813
C814
C815
C816
C817
C818
C819
C820
C821

1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2

2
G

<29>
2N7002_SOT23
<29>

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

USB20_P4
USB20_N4
OVCUR#4

USB20_P4
USB20_N4

USB20_P5
USB20_N5

USB20_P5
USB20_N5
SPDIFO_R

1
2
FBMA-L10-201209-301LMT
1
<38>
C822
220P_0402_25V8K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5V
<29>
<29>
3

MIC_L

MIC_L

<38>
2

+5VS
MIC_R

<38>
<40>
<40>
<40>

MIC_DET
HPDET#
SPKR+
SPKL+

MIC_R
MIC_DET
HPDET#
SPKR+
SPKL+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_87213-2000

SM05_SOT23

@ R424
10K_0402_5%
2
1

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ACES_85201-2005

+5V

Q10

CLK_PCI_SIO <15>
SIRQ
<29,32,44>

SIRQ

Audio board conn

USB_OC#5

USB_OC#5

5 KSI4

ESD

R274
0_0402_5%

ACES_85201-2505

D47
VOL_UP#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

<16,37> WL_LED#
<44> VOL_UP#
<44> VOL_DWN#
<44>
LID_SW#
<44> NUMLED#
<38,46> MUTE_LED

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

ON/OFFBTN#
KSI0
KSI1
KSI3
KSI4
KSO_D_17
WL_LED#
VOL_UP#
VOL_DWN#
LID_SW#
NUMLED#
MUTE_LED

KSI0
KSI1
KSI3
KSI4

<44>
<44>
<44>
<44>

Title

Compal Electronics, Inc.

KBD,ON/OFF,T/P,LED/B,DEBUG

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

42

of

60

For PA

For PR

FOR POWER BUTTON BACKLIGHT SYSTEM POWER

FOR POWER BUTTON BACKLIGHT SYSTEM POWER

"Vertical"
R573
PALED@ 220_0402_5%
PMLED_1# 1
2

<44> PMLED_1#

"Right Angle"

D23
1

PA_LED

<42>

R425
PRLED@ 560_0402_5%
PMLED_1# 1
2

+5VS

D13
2

PR_LED

<42>

HT-170NBQA_0805
2

15.4@ 12-21UYOC/S530-A2/TR8_YEL
R570
20K_0402_5%

+5VS

PA_LED_ALW <42,44>

R426
PRLED@ 560_0402_5%
BATLED_0# 2
1

PA_LED_VS <42>

<31>

ACT_LED#

IDE_LED#

ACT_LED#

O
B

IDE_LED#

HT-170NBQA_0805

U48

<28>

D24

PR_LED_ALW <42>

15.4@ 12-21UYOC/S530-A2/TR8_YEL
1

R571
PALED@ 220_0402_5%
IDE_ACT_LED#
1
2

2
3

R568
10K_0402_5%

HT-170NBQA_0805

D14
1

R427
PRLED@ 560_0402_5%
IDE_ACT_LED#
1
2

D15
2

PR_LED_VS <42>

1
3

<44> BATLED_0#

+3VS

D25
1

R572
PALED@ 220_0402_5%
BATLED_0# 2
1

SN74AHCT1G08DCKR_SC70

15.4@ 12-21UYOC/S530-A2/TR8_YEL

C830 1
0.1U_0402_16V4Z

R86
D@
470_0402_5%
CAPSLED# 1
2

<44> CAPSLED#

D6
1

R92
PRLED@ 560_0402_5%
CAPSLED# 1
2

PA_LED_VS

D7
1

PR_LED_VS
C

15.4@ 17-21UYOC/S530-A2/TR8_ORG
D@ HT-170NBQA_0805
R76
PALED@ 470_0402_5%
CAPSLED# 1
2

D4
1

PA_LED_VS

15.4@ HT-170NBQA_0805

PR_LED_VS

PA_LED_VS

D21
HT-110NBQA_0805

D20
17-21UYOC/S530-A2/TR8_ORG
15.4@

R550
1K_0402_5%
CARD_LED 2
1

Q39
MMBT3904_SOT23

<32> CARD_LED

R548
330_0402_5%
1

15.4@ R547
560_0402_5%

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

INDICATE LED

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

43

of

60

0.1U_0402_16V4Z

0.01U_0402_16V7K

<42,43> PA_LED_ALW

LDO3
C472
4.7U_0805_6.3V6K

C527
2

C512

C551

C550
2

0.1U_0402_16V4Z

1
5
CD

+3VALW

<29>
EC_SCI#
C525
0.1U_0402_16V4Z

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO[0..16]

KSO[0..16]

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO_D_17

GM_PM#DET

R587
G71@ 100K_0402_5%
2

@ C556
15P_0402_50V8J
<42>

INVT_PWM/GPIO0F/PWM1
BEEP#/GPIO10/PWM2
OUT BEEP/GPIO12/PWM3
ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

25
27
30
31
32
33

INVT_PWM
CONA#
PGD_IN
ACOFF
FAN_SPEED1
VOL_DWN#

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

91
92
93
94
95
96

EXPCRD_RST#
PWR_ACTIVE#
DOCK_VOL_UP#
TP_CLK
TP_DATA

ADB0/D0
ADB1/D1
ADB2/D2
ADB3/ D3
ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

SELIO2#/ GPIO43
SELIO#/ GPIO50
FRD#/RD#
FWR#/WR#
FSEL#/SELMEM#

84
97
135
136
144

KSO_D_17

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
89
90

key Matrix
scan
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
EC URXD/KSO16/GPIO48
EC UTXD/KSO17/GPIO49

88
87
86
85

EC SMD2/ GPIO47/SDA2
EC SMC2/GPIO46/SCL2
EC SMD1/GPIO44/SDA1
EC SMC1/GPIO44/SCL1

PS2 interface

Data
BUS

+3VS

TP_CLK

R372
10K_0402_5%
1
2 VOL_UP#

R330
10K_0402_5%
1
2 DOCK_VOL_DWN#

140
138

EC_RSMRST#/ GPIO02
BKOFF#/GPIO03
PM SLP S3#/GPIO04
EC LID OUT#/GPIO06
PM SLP S05#/ GPIO07
EC SMI#/GPIO08
EC SWI#/GPIO09
LID SW#/ GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC PME#/GPIO0D

XCLKO
XCLKI

EC ON/ GPIO1B
AC IN/ GPIO1C
ECTHERM#/GPIO11
ONOFF/GPIO18
PCMRST#/GPIO1E
WL OFF#/GPIO1F

KB910LQF_LQFP144

ALI/MH#/GPIO40
FSTCHG/GPIO41
VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

D@ R325
1K_0402_5%
2

BID

C463
0.22U_0603_10V7K
2

R333
2K_0402_5%

C517
10P_0402_50V8K

INVT_PWM <16>
CONA#
<46>
PGD_IN <53>
ACOFF
<49>
FAN_SPEED1 <4>
VOL_DWN# <42>
ACZ_RST# <28,38>
EXPCRD_RST# <34>
PWR_ACTIVE# <42>
DOCK_VOL_UP# <46>
TP_CLK
<42>
TP_DATA <42>
ADB[0..7]

KBA[0..19]

ADB[0..7] <45>

KBA[0..19] <45>

EC_ON
ACIN
EC_THERM#
ON/OFF#
VOL_UP#
ICH_POK

NV_ENBKL <18>
DOCK_VOL_DWN# <46>
FRD#
<45>
FWR#
<45>
FSEL#
<45>
EC_ON
<42,50>
ACIN
<48,50>
EC_THERM# <29>
ON/OFF# <42>
VOL_UP# <42>
ICH_POK <7,29>

NV_ENBKL

R581
100K_0402_5%

AIR_ACIN
81
AIR_ACIN <49>
FSTCHG
82
FSTCHG <49>
VR_ON
83
VR_ON
<53>
137 R365 2
1 0_0402_5%
VGATE
<29,53>
CIR_ IN
142
CIR_IN
<42,46>
EC_MUTE#
143
EC_MUTE# <40>

LDO3
1
0_0603_5%
R327

C RY1
C RY2

R326
2
1
0_0603_5%

EC DEBUG port

ECAGND

C474
2

+EC_AVCC

0.1U_0402_16V4Z
C522
10P_0402_50V8K

JP20
1
2
3
4

1
2
3
4

ACES_85205-0400

LDO5
UTXD

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

<49>

ADP_I

2
R332
10K_0402_5%

NV_ENBKL
DOCK_VOL_DWN#
FR D#
FWR#
FSEL#

41
43
29
36
45
46

32.768KHZ_12.5P_MC-146

R402
10K_0402_5%
1
2 VOL_DWN#
R331
10K_0402_5%
1
2 DOCK_VOL_UP#

C RY2
C RY1

Y7

TP_DATA

4
7
8
16
17
18
19
20
21
22
23

PCM_SPK#/EMAIL_LED#/ GPIO16
SB_SPKR/PWR_SUSP_LED#/ GPIO17
PWRLED#/ GPIO19
NUMLED#/ GPIO1A
BATT CHGI LED#/ E51CS#
BATT LOW LED#/ E51MR0
CAPS LED#/ E51TMR1
ARROW LED#/ E51 INT0
SYSON/GPIO56/ E51 INT1

AGND

EC_RSMRST#
BKOFF#
SLP_S3#
LID_OUT#
SLP_S5#
EC_SMI#
LAN_RST#
LID_SW#
SUSP#
PWRBTN_OUT#
PCI_PME#

<29> EC_RSMRST#
<16>
BKOFF#
<29>
SLP_S3#
<29>
LID_OUT#
<29>
SLP_S5#
<29>
EC_SMI#
<29>
LAN_RST#
<42>
LID_SW#
<34,45,47,51,52,54> SUSP#
<29> PWRBTN_OUT#
<27,32> PCI_PME#

34
35
38
40
99
101
100
102
104

77

<43> CAPSLED#
<29,34> CPUSB#
<34,47,51> SYSON

2 R394
1 FSEL#
10K_0402_5%
2 R390
1 FR D#
10K_0402_5%
2 R585
1 LID_SW#
@ 10K_0402_5%

UTXD
SLP_S4#
PMLED_1#
NUMLED#
BATLED_0#
GM_PM#DET
CAPSLED#
CPUSB#
SYSON

Address
BUS
SM BUS

GND
GND
GND
GND
GND
GND

+5VALW
B

EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1

EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1

<29>
SLP_S4#
<43> PMLED_1#
<42>
NUMLED#
<43> BATLED_0#

LDO3

DAC_BRIG <16>
EN_FAN1 <4>
IREF
<49>
EC_RTCRESET <28>

1
DAC_BRIG
EN_FAN1
IR EF

139
129
103
13
28
39

<4>
<4>
<45,56>
<45,56>

2 R339
1 EC_SMD_1
10K_0402_5%
2 R340
1 EC_SMC_1
10K_0402_5%

76
78
79
80

+3VALW
2 R337
1 EC_SMD_2
10K_0402_5%
2 R338
1 EC_SMC_2
10K_0402_5%
2 R400
1 EC_SMI#
@ 10K_0402_5%
2 R397
1 EC_SCI#
@ 10K_0402_5%

C@ R605
2K_0402_5%

BATT_TEMP <56>
BATT_OVP <49>
1

DAC_BRIG/DA0/GPIO3D
EN DFAN1/DA1/GPIO3D
IREF2/DA2
EN DFAN2/DA3/ GPIO3F
DA output or GPO

PWR

KSI[0..7]

KSI[0..7]

2
1

R586 2
1
UMA@ 10K_0402_5%

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPI032
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPI035
KSI6/GPIO36
KSI7/GPIO37

BATT_TEMP
BATT_OVP
ADP_IR
BID

71
72
73
74

<42>

<42>

@ R399
10_0402_5%

63
64
65
66
67
68
69
70

BATTEMP/AD0/GPIO38
BATT OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD BID0/AD3/GPIO3B
AD INtput or GPI

FAN/PWM
2

+3VALW

GA20/ GPIO00/GA20
KBRST#/GPIO01/KBRST#
SERIRQ
LPC_FRAME# / LFRAME#
LPC AD3/LAD3
LPC AD2/LAD2
Host
LPC AD1/LAD1 INTERFACE
LPC AD0/LAD0
CLK_PCI_EC/PCICLK
PCIRST#
EC RST#/ ECRST#
EC SCI#/SCI#/GPIO0E
PM_CLKRUN#/ CLKRUN#

@ 100K_0402_5%

+5V
R335
10K_0402_5% 2
R336
10K_0402_5% 2

JOPEN

J1

1
2
3
5
6
9
10
12
14
15
42
24
44

EC_AVCC / AVCC

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PCI_RST#
EC_RST#
EC_SCI#
PA_PR#DET

75

11
26
37
105
127
141

RESET

U24

R611

2.2V(R325=1K,R333=2K): After PV type D KB(17")

1.65V(R605=2K,R333=2K): After PV type C KB(15")

+EC_AVCC

C51
2200P_0603_50V7K~D

<28>
GATEA20
<28> KB_RST#
<29,32,42> SIRQ
<28,42> LPC_FRAME#
<28,42> LPC_AD3
<28,42> LPC_AD2
<28,42> LPC_AD1
<28,42> LPC_AD0
<15> CLK_PCI_EC
<27,32,33,36,42> PCI_RST#

1
2
47K_0402_5%

CLK_PCI_EC

BID definition,
High (3.3V): Before SI2 type D KB(17")
Low (0V): Before SI2 type C KB(15")

R382
LDO3

2
0.1U_0402_16V4Z
LDO3

N.C.
VCC

GND

G696L263T1UF_SOT23-5

PA_PR#DET

R580
2K_0402_5%

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC

U47

R579 2
1
1K_0402_5%

Title

Compal Electronics, Inc.

EC KB910L(LPC)

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

44

of

60

<44>

ADB[0..7]

<44>

KBA[0..19]

ADB[0..7]
KBA[0..19]

JP12
KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWR#
RESET#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

KBA17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
LDO3
ADB3
ADB2
ADB1
ADB0
FR D#
FSEL#
KBA0

SUYIN-80065A-040G2T

LDO3

10
11
12
29
38

RESET#

GND0
GND1

23
39

+3VALW
1

RP#
NC
READY/BUSY#
NC0
NC1

+3VALW

C531
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
R366
100K_0402_5%

2
LDO3
<44,56> EC_SMC_1
<44,56> EC_SMD_1
1

R370
100K_0402_5%

LDO3

C829
@ 0.1U_0402_16V4Z

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

AT24C16AN-10SI-2.7_SO8
SUSP#

R609
@ 10K_0402_5%

U22
8
7
6
5

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

SUSP#

<34,44,47,51,52,54>

D0
D1
D2
D3
D4
D5
D6
D7

25
26
27
28
32
33
34
35

C437

R367
100K_0402_5%

SST39VF080-70_TSOP40
@

SN74AHC1G32DCKR_SC70-5

@ 2N7002_SOT23

EC_FLASH#

FWR#

Q53
A

U46
FWE#

2
G

CE#
OE#
WE#

LDO3
2

22
24
9

31
30

FSEL#
FR D#
FWE#

VCC0
VCC1

FSEL#
FRD#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

EC_FLASH# <29>

<44>
<44>

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

U14
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FWR#

<44>

2
0_0402_5%

R610

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

BIOS & EC I/O Port

Size Document Number

Custom LA-2841
Date:

Thursday, December 15, 2005

Rev
1.0
Sheet

45

of

60

L30
DOCK@
KC FBM-L18-453215-900LMA90T_1812
1
2

DOCK_VIN

DOCK@
C689
1000P_0402_50V7K

DOCKVIN
1

C685
DOCK@
1000P_0402_50V7K

Tampa 2
JP22

<38,42>

SPDIFO

<35>
MDO1+
<35>
MDO1<38> JACK_DET#

R478 DOCK@
22_0402_5%
1
2

DOCK@

1
@ C644
1000P_0402_50V7K

R479 1
+5VS
<38,42> MUTE_LED
<32>
XTPA1+
<32>
XTPA1<32>
XTPB1+
<32>
XTPB1-

MDO1+
MDO1JACK_DET#
SPDIFO_L
2 100_0402_5%
MUTE_LED
XTPA1+
XTPA1XTPB1+
XTPB1-

EMI
2

+5V
DOCK_PRESENT
+3VALW

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

DOCK_PRES_GND
MDO0+
MDO0-

MDO0+ <35>
MDO0- <35>

DOCK_MIC

DOCK_MIC <38>

DOCK_LOUT_R
DOCK_LOUT_L

R480 DOCK@
200_0402_5%
1
2

DOCK_LOUT_R <38>
DOCK_LOUT_L <38>

USB20_N1
USB20_P1

USB20_N1 <29>
USB20_P1 <29>

DOCK_VOL_UP# <44>

C647
DOCK@
1000P_0402_50V7K

TVCOMPS
TVLUMA
TVCRMA
CIR_ IN

CIR_IN
+5V

V_Bat

TVCOMPS <17>
TVLUMA <17>
TVCRMA <17>

R491 DOCK@
200_0402_5%
2
1

<42,44>

1K_0402_5% 2
V_Bat
<48,49>

DOCK@
1 R495

DOCKVIN

DOCK_VOL_DWN# <44>

1
C681
DOCK@
1000P_0402_50V7K

DOCKVIN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

FOX_QL11293-H212CR-FR
R471 DOCK@
10K_0402_5%
2

need change to reverse type connector

CONA#
1

<44>

Q36 DOCK@
MMBT3904_SOT23

2
3

DOCK_PRESENT

+5V
C333
DOCK@
10U_0805_10V4Z

DOCK_PRES_GND

DOCK@
C318
0.1U_0402_16V4Z

@
C295
1000P_0402_50V7K

Compal Secret Data

Security Classification
2005/03/10

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DOCK CONN

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

E

46

of

60

B+

+5VALW to +5V Transfer

R341

+3VALW to +3VS Transfer

+3VS

SI4800DY_SO8

1
C760
10U_0805_10V4Z

C759

8
7
6
5

D
D
D
D

S
S
S
G

1
2
3
4

SI4800DY_SO8

470_0402_5%

C459
10U_0805_10V4Z

C455

2
G

<34,44,51> SYSON
1

C438
10U_0805_10V4Z
R549

0.1U_0402_16V4Z

U17

0.1U_0402_16V4Z
1
2
3
4

S
S
S
G

R306

Q16
2N7002_SOT23

470_0402_5%

B+

SYSON# 2
G

S
S

2 SUSP
G
Q11
2N7002_SOT23

R406

2
330K_0402_5%
<52,55>

SUSP

SUSP

470_0402_5%

Q40
2N7002_SOT23

RUNON
2 SYSON#
G
Q41
2N7002_SOT23

2
G

<34,44,45,51,52,54> SUSP#

C755
0.01U_0402_16V7K

R546

1
1

SUSON

R545
330K_0402_5%

D
D
D
D

8
7
6
5

C758
10U_0805_10V4Z

SYSON#

+5V
U39
B+

330K_0402_5%

+3VALW

+5VALW

Q27
2N7002_SOT23

FM3

FM1

FM2

FM5
1

FM6
1

FM4
1

+5VALW to +5VS Transfer

+1.8V to +1.8VS Transfer

CF3

CF8

CF4

CF6

CF12 CF14 CF7

CF1

CF13

CF9

1
CF2

CF11

H15
H3
H16
H19
H20
H12
H7
H14
H22
H13
H8
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

S
2 SUSP
G
Q18
2N7002_SOT23

2 SUSP
G
Q7
G71@
2N7002_SOT23

H11
H2
HOLEA HOLEA

2
C557
0.01U_0402_16V7K

1
3

S
470_0402_5%

CF10 CF5
R154
G71@
470_0402_5%

RUNON

R395

C377

G71@ SI4800DY_SO8

C379
G71@
10U_0805_10V4Z

470_0402_5%

1
1
3

SUSP 2
G
Q21
2N7002_SOT23

1
2
3
4

R347

RUNON
D

S
S
S
G

C552

D
D
D
D

C561
10U_0805_10V4Z

8
7
6
5

SI4800DY_SO8

R398
330K_0402_5%

C373
G71@
10U_0805_10V4Z

0.1U_0402_16V4Z
1
2
3
4

S
S
S
G

D
D
D
D

B+

8
7
6
5

G71@
0.1U_0402_16V4Z

U25
C515
10U_0805_10V4Z

U5

+1.8VS
+5VS

+1.8V
+5VALW

H23
HOLEA

H24
HOLEA

470_0402_5%
1 2

2 SUSP
G
Q17
2N7002_SOT23

470_0402_5%

1 2

R68

470_0402_5%
D

D
2 SUSP
G
Q38
2N7002_SOT23

SUSP
2
G
Q3
2N7002_SOT23

Compal Secret Data

Security Classification

Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H21
HOLEA

+0.9VS

R536

1 2

H6
HOLEA

+VGA_CORE

2 SUSP
G
Q37
2N7002_SOT23

2 SYSON#
G
Q4
2N7002_SOT23

H18
HOLEA

2 SUSP
G
S

R346

H17
HOLEA

1
470_0402_5%
1 2

R522

470_0402_5%
1 2

R131

470_0402_5%
D
Q5
2N7002_SOT23

+VCCP

R137

1 2

+1.5VS

+1.8V

+2.5VS

H5
H10
H4
H9
HOLEA HOLEA HOLEA HOLEA

Compal Electronics, Inc.

DC/DC Circuit
Size Document Number
Custom LA-2841
Date:

Thursday, December 15, 2005

Rev
1.0
Sheet

of

47

60

Detector/Precharge

PD27
@ SBM1040-13_POWERMITE3
2
1
3
PJP1
@ JUMP_43X118
1 1
2 2

V_Bat

<46,49>

PC4
1000P_0402_50V7K
2
1

PR10
1
1
PR11
47_1206_5%

N58

2
8
-

PR4
1K_0402_5%
2

PACIN

1
1

PU1A
LM393M_SO8
PZD1
RLZ4.3B_LL34

PC7
1000P_0402_50V7K

ACIN

<44,50>

PACIN

<49>

PR7
10K_0402_5%
2

PR9
10K_0402_5%
1

RTCVREF

3.3V

1N4148_SOD80

Titan: PR5= 22K; PR6= 19.6K

Altima:PR5= 47K; PR6= 27K
2

1K_1206_5%

N3

PR3
10K_0805_5%

N5

N4

PR12
1

N2

PD2
2

1K_1206_5%

PJP27

PR6
19.6K_0603_0.1%
2
1

B+

PC6
0.047U_0603_50V7K

2
1K_1206_5%

VIN

PR5
22K_0603_1%
2

PR8

@ JUMP_43X39

PC5
1

N1

VIN

PR2
82.5K_0603_0.1%

BATT+

VS

PC3
100P_0402_50V8J
2
1

1
2

PC2
1000P_0402_50V7K

PC1
100P_0402_50V8J

VIN

PCN1
ACES_88290-0400M

PD3
1N4148_SOD80

PR1
1M_0603_0.5%
1
2

PD1
@ SBM1040-13_POWERMITE3

1
3

ADPIN2

PD31
EC31QS04

Vin Detector : Altima

14.698 14.285 13.879
13.818 13.411 13.000

17.449
16.813

PL1
FBM-L18-453215-900LMA90T_1812

Vin Detector : Titan

18.234 17.841
17.597 17.210

0.01U_0402_25V7Z

ADPIN

VIN

PJP2
@ JUMP_43X118
1 1
2 2

ADPIN

DOCK_VIN

PR14
1

<42> EC_PWR_ON#

1
2

VS
PD4
1N4148_SOD80

PC9
0.1U_0603_25V7K

PR13
100K_0603_1%

PC8
0.22U_1206_25V7K
2
1

CHGRTCP

PR215
47_1206_5%
2
1

PQ1
TP0610K-T1-E3_SOT23

N6

VL

PR15
10K_0402_5%
2

PR16
1M_0603_0.5%
2
1

22K_0603_1%

VS

B+

ACIN: Titan
B

PD5
PR17

PJP6
@ JUMP_43X118
1 1
2 2

+3VALWP

PJP8
@ JUMP_43X118
1 1
2 2

+1.8VP

+1.05VSP

+0.9VSP

PJP10
@ JUMP_43X118
1 1
2 2
PJP12
@ JUMP_43X118
1 1
2 2
PJP14
@ JUMP_43X118
1 1
2 2

+5VALW

+3VALW

+1.5VSP

PJP7
@ JUMP_43X118
1 1
2 2

+1.2VSP

PJP9
@ JUMP_43X118
1 1
2 2

+1.8V
+VGA_COREP

+VCCP

+1.5VS

1
2

2 N13
G

PC12
1000P_0402_50V7K

+1.8VS

PR21
200K_0603_1%
2

N11

PR24
10K_0402_5%
2
1

PJP15
@ JUMP_43X118
1 1
2 2

+
+1.2VS

N10

PR23
47K_0402_5%
1 PACIN

ACIN: Altima
Precharge detector
12.384 12.000 11.624
10.927 10.600 10.223
BATT

S
PQ2
2N7002_SOT23

+5VALWP
2

Precharge detector
7.558 7.333 7.112
6.108 5.933 5.704

PQ3
DTC115EUA_SC70

Titan: PR21= 200K

Altima:PR21= 300K

+2.5VS

4.7U_0805_6.3V6K

PC152

PC151
220U_D2_4VM

+2.5VSP

+1.8VSP

+5VALWP

PU1B
LM393M_SO8

VL
+0.9VGA

PR22
1.5M_0603_1%

1
2
PJP4
@ JUMP_43X39

N12

+0.9VGAP

PJP5
@ JUMP_43X118
1 1
2 2

N9

RB751V_SOD323

<50,56> MAINPWON

1U_0805_50V4Z

PC11
4.7U_0805_6.3V6K

PD6
PC10

1
PR256
47K_0603_1%

N8

IN
GND

PC14
1000P_0402_50V7K

OUT

3.3V

N7 1

Precharge detector
14.724 14.333 13.945
13.280 12.933 12.531

PR18
280K_0603_1%

RB751V_SOD323

<49> ACON

200_0603_5%

PC13
0.1U_0603_25V7K

PU2
G920AT24U_SOT89

CHGRTC

PR20
@ 510_0603_5%

PR19
@ 510_0603_5%

RTCVREF

PJP11
@ JUMP_43X118
1 1
2 2

+VGA_CORE

PJP13
@ JUMP_43X118
1 1
2 2

Compal Secret Data

Security Classification
Issued Date

2005/03/22

2006/03/22

Deciphered Date

Title

DCIN / Precharge

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+0.9VS

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

48

of

60

<46,48> V_Bat

PD32
EC31QS04
2

Charger

B+

B++

OUTC2

24

GND

23
22

3887CS

-INE2 VCC(o)

21

3887VCC

FB2

OUT

20

3887OUT

VH

19

PC23
3887VH 1
2

1
2N171
23887FB17
PR38
1K_0603_1%
PC25
1500P_0402_50V7K
3887-INE1 8

FB1

VCC

18

1
2

-INE3

3887-INE3

15

3887FB3

PL2
15U_PLFC1045P-150A_3.7A_20%
1
2
2

OUTC1

FB3

PC27
1500P_0402_50V7K

CTL

14

ACON

+INC1

13

3887+INC1

OUTD
-INC1

1
47K_0603_1%

2N181

PD10
EC31QS04

BATT+

PR40
0.02_2512_1%
PD11
EC31QS04

PC31
0.1U_0402_16V7K

<44>

MB3887_SSOP24

4.2V

PR45
49.9K_0603_0.1%

PC30
4.7U_1206_25V6K
2
1

3887RT 1
2
68K_0603_5%

16

PC29
4.7U_1206_25V6K
2
1

17

PC28
4.7U_1206_25V6K
2
1

+INE1

3887OUTC1
10

Battery OVP voltage :

4S2P : 18V--> BATT_OVP= 2.0V
(BAT_OVP=0.1112*VMB)

ACOFF

PQ7
DTC115EUA_SC70

PC26 0.1U_0603_25V7K
1
2

RT

-INE1

3887+INE19
2
1
PR41
10K_0603_1%

PR42

100K_0603_1%
2

PC20
0.1U_0603_25V7K

N19

PR44

PQ6
AO4407_SO8

PR39

12

IREF=1.096*Icharge
IREF=0.438~3.069V

ACOFF#

VREF

CS

+INE2

23887FB25
PR35
6.8K_0402_1%
3887VREF 6

VIN

3
2
1

5
6
7
8

3887-INE2

PR31
10K_0603_5%
PC19 2200P_0402_50V7K
1
2

174K_0603_1%

1
1

3887+INE2

3887OUTD11
1 PR43

IREF

PR30
2.2_0603_5%

+INC2

0.1U_0603_25V7K

65W PR34=31.6K
90W PR34=20.0K
<44>

2
-INC2

ACON

PR29

2
G

PQ5
AO4407_SO8

PR37
3K_0603_5%

1
PACIN 1

PACIN

PC21
2200P_0402_25V7K
1
2 N16 1

5.0V
2

<48>

1
PR32
10K_0402_1%

PC24
0.1U_0402_16V7K

2
1
PR36
10K_0402_1%

PD9
1SS355_SOD323

PC22
0.1U_0402_16V7K
2
1

PR34
31.6K_0603_1%

1
1

N15

ACOFF#

PQ8
2N7002_SOT23

PQ52
2N7002_SOT23

PR33
150K_0402_1%

8
7
6
5

47K_0603_5%

N14

65W==>1.202V
90W==>1.667V

3
1

ADP_I

2
G

1
2
3

PU3
<44>

PQ53
DTC115EUA_SC70

PC18
2200P_0402_50V7K

2
2

PR28
200K_0402_5%

65W:1.40V(-1 level); 1.30V (+1 level)

90W:2.05V(-1 levle); 1.83V (+1 level)

47K

PC206
0.1U_0603_25V7K
2
1

47K

0.02_2512_1%

3
1
2

PQ54
DTA144EUA_SC70
N64
2

N65 2

PC17
0.1U_0603_25V7K

DIS

PR248
47K_0402_5%

<48>

PR26

8
7
6
5

PC16
4.7U_1206_25V6K

1
2
3

PR27
15K_0603_5%
2
1

1
2
3

8
7
6
5

PL18
FBM-L18-453215-900LMA90T_1812

P3

VIN
D

PQ4
AO4407_SO8

PC15
4.7U_1206_25V6K

PQ49
AO4407_SO8

PC209
100U_25V_M

65W Iadp=0~3.0A
90W Iadp=0~4.2A

P2

PR46
150K_0603_0.1%
B

CC=0.4~2.8A
BATT_Charge Voltage Select
4S2P
CV=16.8V PR45 = 49.9K_0603_0.1%
3S2P/3S4P CV=12.6V PR45 = 150K_0603_0.1%

3S2P/3S4P : 13.5V--> BATT_OVP= 2.0V

(BAT_OVP=0.14753 *BATT+)
VS

PR46 =150K_0603_0.1%
PR46=300K_0603_0.1%

BATT++
AIR_ACIN

<44>

+3VALWP
1

N26

2
1

RTCVREF

N25 2

PQ10

2
G

2N7002_SOT23

VIN

PR52
(17V+-5%)
42.2K_0603_1%

1
2

1
2

PR53
10K_0603_5%

PC33
0.01U_0402_25V7Z

PR57
0_0603_5%

<44>

FSTCHG

2
PQ11
DTC115EUA_SC70

PR54
10.2K_0603_1%

Compal Secret Data

Security Classification

BATT_OVP Select
4S2P
PR57 = 0_0603_5%
3S2P/3S4P PR57 = 40.2K_0603_1%
5

47K_0603_5%
PR50
10K_0603_5%
1

N21

N23 2

1
PR56
22K_0402_5%

PR51
4.22K_0603_1%
2
1N247

N22

PR55
105K_0603_0.5%

PU4B
LM358A_SO8

PZD2
RLZ4.3B_LL34

PQ9
DTC115EUA_SC70

PR49
499K_0603_1%

3887CS
PR48

0.01U_0402_25V7Z

PC32

2
P
1

<44> BATT_OVP

PU4A
LM358A_SO8

3887CS

N20

PR47
340K_0603_1%

Issued Date

2005/03/22

2006/03/22

Deciphered Date

Title

Charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

49

of

60

+3.3VALWP/+5VALWP

B+

3
1

PQ42

2
2 1

1
2

LDO3P

LDO3

PR240
0_0805_5%

+3VALWP

2
+
2

PR252
@ 0_0805_5%

PR242
100K_0402_5%
1
1

N60

2
G

2
G
3

ACIN

2
G

EC_ON <42,44>

PQ47
RHU002N06_SOT323

PQ46
RHU002N06_SOT323

PC197
0.047U_0603_16V7K

Compal Secret Data

Security Classification
Issued Date

2005/03/22

2006/03/22

Deciphered Date

Title

+3V/+5V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PC194
150U_D2E_6.3VM_R18

LDO3P

PD26
@SKUL30-02AT_SMA

PR231
0_0402_5%
2

2
1999_PRO 1

PR230
@ 3.57K_0402_1%

+3VALWP

PR234
0_0402_5%
2
1

FB3

7
2

<48,56> MAINPWON

2
1
PR233
806K_0603_1%

1999_ON

VL

DL3

DH3

23
PC195
2
1

ACIN

REF

PL17
10U_LF919AS-100M-P3_4.5A_20%

PR232
0_0402_5%

ACIN

2VREF_1999

PR228
10K_0402_5%
PC193 <44,48>
@ 1U_1206_25V7K

12

PR223
0_0402_5%

1999_SKIP
2REF_1999

LX3

PRO#

2
0_0402_5%

LDO3

1
PR257

6
4
3

AO4912_SO8

BST3A

28
26
24
27
22

10

@ 0_0402_5%
2

25

PR258
2REF_1999
1

PR227
47K_0402_5%
2
1

1999_SHDN

0.22U_0603_16V7K

1999_V+

8
7
6
5

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

ILIM5

PC187
2200P_0402_50V7K
2
1

2
11

1
2
3
4

DH3A

PR225
PR222
499K_0402_1% 200K_0402_1%
1

ILIM3
1

2
2 1

LX5
PU5
DL5
ILIM5
OUT5 MAX8734EEI_QSOP28
FB5
BST3
N.C.
DH3
DL3
SHDN#
LX3
ON5
OUT3
ON3
FB3
SKIP#
PGOOD

VCC

15
19
21
9
1

ILIM3

PR224
PR221
499K_0402_1% 118K_0402_1%

2
1

PC189
1U_0603_10V6K

1999_VCC

17

13

DH5

V+

2VREF_1999

PC186
4.7U_1206_25V6K
2
1

PC184
0.1U_0402_16V7K

PC185
4.7U_1206_25V6K
2
1

1
2

2
1

PR218
47_0402_5%

1
PR219
10_1206_5%
1PC191
0.1U_0603_25V7K

BST5

16

PC196
4.7U_0805_6.3V6K

FB5

PR226
@ 10.2K_0402_1%

1
2
1

PR229
0_0402_5%

PD25
@SKUL30-02AT_SMA

PC192
150U_D2E_6.3VM_R18

14

LD05

BST5A

+5VALWP

20

18

DL5

B+++

PR220
0_0402_5%

1999_V+

+5VALWP

PC190
4.7U_0805_6.3V6K
2
1

1
PL16
10U_LF919AS-100M-P3_4.5A_20%

VL

VL

LX5

PD24
DAP202U_SOT323

1999_V++

PC188
4.7U_1206_25V6K
2
1

PR241
0_0805_5%

AO4912_SO8

PR255
@ 0_0805_5%
1
2

PR217
0_0402_5%

PR239
10_1206_5%
2
1

DH5

1
PR251
0_0805_5%
2
1

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

8
7
6
5

1
2
3
4

PC183
2200P_0402_50V7K
2
1

PC182
4.7U_1206_25V6K
2
1

PC181
4.7U_1206_25V6K
2
1

LDO5
PR216
0_0402_5%
DH5A 1
2

P2
PR254
0_0805_5%
1
2

VS

B+++

PQ41

PC180
0.1U_0603_25V7K
2
1

BST3B
2

BST5B

TON

PC179
0.1U_0603_25V7K
2
1

GND

@ JUMP_43X118

PQ48
RHU002N06_SOT323

PJP25

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

50

of

60

+1.8VP/+1.5VALWP/+2.5VS

IS6227A_B+

+5VALWP

LG1.5

PGND1

PGND2

26

VOUT2
VSEN2
EN2
PG2/REFA

20
19
21
16

OCSET2

18

OCSET1

4.7U_0805_6.3V6K

1
2

PC73

D
D
D
D

PC72
220U_D2_4VM

4
3
2
1
5
6
7
8

VOUT1.5
VSEN1.5
EN1.5
OC1.5

ISL6227BCA-T_SSOP28

PR101
73.2K_0603_1%

PR102
73.2K_0603_1%
2

SUSP#

PR96
0_0402_5%

<34,44,45,47,52,54>

PC79
@ 0.1U_0402_16V7K

PR100
10K_0402_1%
2
1

11

PR94
2.43K_0603_1%
1
2

VOUT1
VSEN1
EN1
PG1A

PR99
0_0402_5%
1

9
10
8
15

1
PQ59
SI4810DY-T1-E3_SO8

PR92
6.81K_0402_1%
2
1

27

PR88
0_0402_5%
2 UG1.5A

+1.5VSP

PL5
3.3UH_PLC1045P-3R3A_6.1A_30%
1
2

PC77
0.01U_0402_25V7Z
2
1

LGATE2

PQ58
SI4800BDY_SO8

PR91
@ 0_0402_5%
2
1

LGATE1

B+

5
6
7
8
D
D
D
D
ISEN1.5

G
S
S
S

25

PHASE1.5

PC71
0.1U_0603_25V7K
2
1

G
S
S
S

VCC

UG1.5

4
3
2
1

28

14
VIN

24

22

ISEN1

1
1
PC78
@ 0.1U_0402_16V7K

UGATE2

ISEN2

EN1.8

2
PR95
0_0402_5%

23

PHASE2

PHASE1

BOOT2

PR86
0_0402_5%
BOOT1.5
1
2

OC1.8

PR98
@ 0_0402_5%

PR97
10K_0402_1%
2
1

VOUT1.8
VSEN1.8

UGATE1

SOFT1.52

LG1.8

BOOT1

17

SOFT2

S
S
S
G

PR93
2.43K_0603_1%
1
2 ISEN1.8

PC69
0.01U_0402_25V7Z

SOFT1

DDR

D
D
D
D

UG1.8A

PHASE1.8

<34,44,47> SYSON

ISL6227A_VIN

PC66
0.1U_0603_25V7K
2
1

PR87
0_0402_5%
1
2 UG1.8

1
2
3
4

PR90
0_0402_5%

PQ17
SI4800BDY_SO8

PR85
0_0402_5%
1
2BO0T1.86

PC76
0.01U_0402_25V7Z
2
1

PR89
10.5K_0402_1%
2
1

PC74
220U_D2_4VM_R25

1
2

PC75
4.7U_0805_6.3V6K

PU6
1SOFT1.8 12

13

PC68
0.01U_0402_25V7Z

GND

PC70
0.1U_0603_25V7K
2
1

8
7
6
5

1
2
3
4

PL4
4.7UH_PLC1045P-4R7A_5.5A_30%

PD17
DAP202U_SOT323

S
S
S
G

+1.8VP
C

2
BOOT1.8A

BOOT1.5A

D
D
D
D

PQ16
SI4800BDY_SO8

PR84
2.2_0603_5%
PC67
2.2U_0805_10V6K
1
2

ISL6227A_VCC

8
7
6
5

PC65
4.7U_0805_6.3V6K
2
1

51_1206_5%

PC63
4.7U_1206_25V6K
2
1

PC62
4.7U_1206_25V6K
2
1

PR83

PC64
2200P_0402_50V7K
2
1

PC61
2200P_0402_50V7K
2
1

PC60
4.7U_1206_25V6K
2
1

PC59
4.7U_1206_25V6K
2
1

PJP18
@ JUMP_43X118

(400mA,40mils ,Via NO.= 1)

APL5508_SOT89
PJP19
@JUMP_43X39

6
5
2
1

OUT
GND

PR103
@ 47K_0603_5%
SUSP#
1
2

N32

PC83
@ 0.1U_0603_25V7K

IN

PC82
10U_1206_25VAK

@ SI3456DV-T1_TSOP6

VIN2.5

PC81
4.7U_0805_6.3V6K

1
PQ18

PC80
1U_0603_10V6K

+3VS

+2.5VSP

PU7

Compal Secret Data

Security Classification
Issued Date

2005/03/22

2006/03/22

Deciphered Date

Title

1.8V/1.5V/2.5V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

51

of

60

PL6
FBM-L18-453215-900LMA90T_1812

PQ19

2DL1.05A

PR111
4.7_0402_5%

PD18
1SS355_SOD323

PR112
750_0603_1%

PC93
0.1U_0402_10V6K

PJP20
@ JUMP_43X118

+1.8VP

PC92
0.047U_0603_25V7M
1

+1.8V

N33

PC89
0.1U_0603_25V7K

1
2

4
3
2
1

PC201
4.7U_0805_6.3V6K

MAX8578EUB_10UMAX

BST1.05

PR109
30_0402_5%

BST

GND

DL1.05

DL

VCC

LX1.05

PL7
3.3UH_PLC1045P-3R3A_6.1A_30%
1
2

PC85
0.1U_0603_25V7K

+1.05VSP
DH1.05A

PR108
7.15K_0402_1%

LX

PR106
0_0402_5%
2

5
6
7
8

FB

D
D
D
D

DH1.05

G
S
S
S

1
2

PR110
866_0402_1%

+1.05V_VCCPP/+0.9VSP

B+

4
3
2
1

PR107
0_0402_5%

MAX8578_VCC 3
PC91
4.7U_0805_6.3V6K
2
1

+5VS

DH

PQ20
SI4810BDY_SO8

FB1.05 1
1

IN

SS

OCSET

SI4800BDY_SO8
G
D 5
S
D 6
S
D 7
S
D 8

2
MAX8575_OCSET

PC87
@ 0.1U_0603_16V7K

PU8
PC88
10
3300P_0402_50V7K
2
1 MAX8575_SS 2

<34,44,45,47,51,54>
2

SUSP#

PC84
10U_1206_25V6M

PR105
0_0402_5%
MAX8575_IN 1
2

1
2

PR104
6.81K_0402_1%

PC86
0.01U_0402_25V7Z
2
1

MAX8575_B+

PC90
330U_D2_2.5VM

PU9
VCNTL

GND

NC

VREF

NC

VOUT

NC

TP

+3VALW
2

VIN

PR113
1K_0402_1%

PC95
1U_0603_16V6K

PC94
10U_1206_6.3V7K

VIN0.9

VREF0.9
1

PC96
0.1U_0402_16V7K

1
3

PR115
1K_0402_1%

+0.9VSP

PC98
10U_1206_6.3V7K

PQ21
2N7002_SOT23

2
G
@ PC97
0.1U_0402_16V7K
2
1

SUSP

PR253
510K_0402_5%
2
1

<47,55>

APL5331KAC-TR_SO8
PR114
510K_0402_5%
1
2

Compal Secret Data

Security Classification
Issued Date

2005/03/22

Deciphered Date

2006/03/22

Title

1.05V/0.9V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size
Date:

Document Number
Thursday, December 15, 2005

Rev
1.0
Sheet
1

52

of

60

CPU CORE

PL8
FBM-L18-453215-900LMA90T_1812
1
2
B+

PC103
10U_1206_25VAK
2
1

+CPU_B+

PC102
4.7U_1206_25V6K
2
1

PC101
2200P_0402_50V7K
2
1

PC100
0.1U_0603_25V7K
2
1

+CPU_B+

1
+
2

PC99
100U_25V_M

CPU_PHASE1

CLK_EN#

ISL6260_VRON

35

VR_ON

ISL6260_VSEN

12

VSEN

2
4

21

ISL6260_ISEN3

OCSET

2
1

2
PC113
4.7U_1206_25V6K
2
1

PC112
2200P_0402_50V7K
2
1

PC111
0.1U_0603_25V7K
2
1

PC114
10U_1206_25VAK
2
1

+CPU_CORE

PR140
10K_0402_1%
1
2

PC118
0.22U_0603_10V7K
2
1

PR136
10_0402_1%

PR143
5.11K_0603_1%

2 PR144 1

@ NC
VSUM

VO

6208B_LG

+5VS

ISL6260_OCSET

17

VSUM

PR152
2
1
11.5K_0402_1%

VO

PR166
6.19K_0603_1%
2
1

PR167
1K_0402_1%
2
1

1
2

PC136
1

PR158
3K_0402_1%

VSUM

VW

N35

COMP

PR164
6.98K_0402_1%

LGATE

GND

0.36UH_MPC1040LR36_24A_20%
CPU_PHASE2

6208B_UGA

PR138
4.7_1206_5%

40

PC208
@ 1U_0603_10V6K
2
1

ISL6260_PGOOD
ISEN3

PH2

1
PC133
1000P_0402_50V7K

PR147
0_0402_5%
2
1

220P_0402_25V8K
B

PQ25
SI4684DY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

PWM PHASE

BOOT

PR165
@ 1K_0402_1%

ISL6260_PWM3

N 57 2

PC128
PR160
0.022U_0402_16V7K 68.1K_0402_1%

25

10KB_0603_5%_ERTJ1VR103J

1
PC132
1
2

PWM3

VO

1 PR157 2
1.2K_0402_1%

VO

PL10

ISL6260_FCCM

FB

DFB

PR155
180_0603_1%

PR156
0_0402_5%
2
1

N 34

@ NC
VSUM

PR151
0_0402_5%

15

PC126
1800P_0402_50V7K
N 45 1
2

24

ISL6260_DFB

FCCM

VDIFF

DROOP

10

2 PR123 1

RTN

ISL6260_DROOP 14

PR154
@ 10_0402_1%

PC121
1000P_0402_50V7K

ISEN2

16

11

1
2

FCCM UGATE

ISL6208CRZ-T_QFN8

22

ISL6260_RTN 13

PR122
5.11K_0603_1%

38

PC107
0.22U_0603_10V7K
2
1

PGD_IN

ISL6260_CLK

PC199
0.082U_0603_25V7K

PR153
0_0402_5%
2
1

<5> VSSSENSE

VCC

PR237
0_0603_5%
6208B_UG 2
1

PSI#

ISL6260_ISEN2

1N 38

ISL6260_PGD

PC120
1000P_0402_50V7K
2
1

+CPU_CORE2
1
PR150
@ 10_0402_1%

18

DPRSLPVR

ISL6260_PSI

ISL6260_PWM2

PC129
1000P_0402_50V7K

1
0_0402_5%

DPRSTP#

36

2
PR149

37

ISL6260_DPRSLPVR

2 PR145 1
0_0402_5%
2 PR148 1
0_0402_5%

<44> VR_ON

ISL6260_DPRSTP

499_0402_1%

2 PR146 1
0_0402_5%

<15> CLK_ENABLE#
<5> VCCSENSE

PWM2

26

<44> PGD_IN

VID0
VID1
VID2
VID3
VID4
VID5
VID6

PR129
PC117
2.2_0603_5%
0.22U_0603_10V7K
2
1N 39 1
2

PU12

0.1U_0402_16V7K

2 PR142 1
0_0402_5%

H_PSI#

28
29
30
31
32
33
34

PC134
2
1

2 PR141 1

ISL6260_VID0
ISL6260_VID1
ISL6260_VID2
ISL6260_VID3
ISL6260_VID4
ISL6260_VID5
ISL6260_VID6

ISL6260_VCIFF
ISL6260_FB
ISL6260_COMP
ISL6260_VW

<5>

23

PC130
0.22U_0603_16V7K
1
2

2 PR139 1
0_0402_5%

<7,29> DPRSLPVR
D

ISEN1

ISL6260_ISEN1

PU11
PR1301
2
0_0402_5%
2 PR132 1
0_0402_5%
2 PR134 1
0_0402_5%
2 PR137 1
0_0402_5%

2 PR131 1
0_0402_5%
2 PR133 1
0_0402_5%
2 PR135 1
0_0402_5%

<4,28> H_DPRSTP#

ISL6260_PWM1

PR159
4.53K_0402_1%
2
1

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

27

N43 1

0.022U_0402_16V7K
<5>
<5>
<5>
<5>
<5>
<5>
<5>

VIN

SOFT

PR120
10K_0402_1%
1
2

+CPU_B+

PQ26
SI4856ADY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

+CPU_CORE
PR118
10_0402_1%

+5VS

ISL6260CRZ-T_QFN40

PWM1

6208A_LG

PC115
1U_0603_16V6K
2
1

NTC

<29,44>

PC119
680P_0603_50V8J

1
RBIAS

39

ISL6260_VIN
VR_TT#

3V3

19
4

VGATE

PGOOD

ISL6260_VRTT
2 PR126 1
0_0402_5%
ISL6260_RBIAS
PH1
2 PR127 1
150K_0402_5% 470KB_0402_5%_ERTJ1VR103J
N
56
ISL6260_NTC
PR128
2
1
2
1
4.22K_0402_1% PC116
ISL6260_SOFT
2
1

<4> H_PROCHOT#

VDD

VSS

20

N 59

PC110
0.01U_0402_25V7Z
ISL6260_NTC
2
1

PR236
@ 0_0402_5%
2
1

ISL6260_VDD

PR125
0_0402_5%

PR124
1.91K_0603_1%

PQ45
SI4684DY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

PC109
PR121
1U_0603_10V6K
10_0603_5%
2
1
1
2

ISL6208CRZ-T_QFN8

LGATE

PL9
0.36UH_MPC1040LR36_24A_20%

GND

6208A_UGA

PR119
4.7_1206_5%

PWM PHASE

N42 1

BOOT

FCCM UGATE

PC108
680P_0603_50V8J

VCC

PQ24
SI4856ADY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

+3VS

PR235
0_0603_5%
6208A_UG 2
1

PQ43
SI4684DY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

PC105
0.22U_0603_10V7K
1N 37 1
2

1N 36

PQ27
SI4856ADY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

+5VS

PR117
2.2_0603_5%
2
PU10

PQ23
SI4856ADY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

0.01U_0402_25V7K
PC106
2
1

PR116
10_0603_5%

PQ22
SI4684DY-T1-E3_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

PC104
1U_0603_16V6K
2
1

+5VS

PC200
0.1U_0402_16V7K

330P_0402_50V7K

Compal Secret Data

Security Classification
2005/03/22

Issued Date

Deciphered Date

2006/03/22

Title

CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
8

Compal Electronics, Inc.

Size
C
Date:
2

Document Number
Thursday, December 15, 2005

Rev
1.0
Sheet

53
1

of

60

+VGA_COREP/+1.8VSP

IS6227B_B+

+5VALWP

25

PHASE_V1.8

ISEN1

ISEN2

22

PR182
1.33K_0603_1%
ISEN_V1.81
2

LGATE1

LGATE2

27

LG_V1.8

PGND1

PGND2

26

9
10
8
15

VOUT1
VSEN1
EN1
PG1B

VOUT2
VSEN2
EN2
PG2/REFB

20
19
21
16

OCSET2

18

PR190
68K_0603_1%

OC_V1.8

PR250
@ 0_0402_5%

SUSP#

PR183
@ 0_0402_5%
1
2

EN_VGA

+3VALWP

PR185
100K_0402_5%

PR191
68K_0603_1%

PR180
10.2K_0402_1%
2
1

PR179
0_0402_5%
1
2

VOUT_V1.8
VSEN_V1.8
1

ISL6227BCA-T_SSOP28

+1.8VS

<34,44,45,47,51,52>

PR189
10K_0402_1%
2
1

OCSET1

1
1

EN_VGA# <55>
D

2
G

+3VALWP

PR249
100K_0402_5%

2
G

SUSP#

<34,44,45,47,51,52>

PR193
0_0402_5%

PC159
@ 0.1U_0402_16V7K

PQ55
RHU002N06_SOT323

PR192
0_0402_5%

PQ56
RHU002N06_SOT323

PC158
@ 0.1U_0402_16V7K

ISL6227B_VCC

PHASE2

OC_VGA 11

EN_VGACORE

28

PHASE1

PR176
0_0402_5%
2UG_V1.8A

EN_VGA 1

UG_V1.8 1

PL13
3.3UH_PLFC0745-3R3_4.8A_30%
1
2

EN_VGA

24

UGATE2

PC150
0.1U_0603_25V7K
2
1

PR187
0_0402_5%

PR184
@ 0_0402_5%

PR186
10K_0402_1%
2
1

SUSP#

UGATE1

PR174
0_0402_5%
2

PC157
0.01U_0402_25V7Z
2
1

LG_VGA

N50 1

+1.8VSP

PR188
@ 0_0402_5%
2
1

PHASE_VGA
PR181
1.33K_0603_1%
1
2 ISEN_VGA

23

1
2
3
4
C

BOOT2

VCC

PR175
0_0402_5%
2 UG_VGA

14

S
S
S
G
D
D
D
D
S
S
S
G

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A

PC148
0.01U_0402_25V7Z
SOFT2

DDR

BOOT1

8
7
6
5

SOFT_V1.82

13

B+

PQ31
AO4912_SO8
PC146
2.2U_0805_10V6K
1
2

17

VIN

PR173
0_0402_5%
2N49

VOUT_VGA
VSEN_VGA

ISL6227B_VIN

PC145
0.1U_0603_25V7K
2
1

PD22
DAP202U_SOT323

PC144
4.7U_0805_6.3V6K
2
1

8
7
6
5
D
D
D
D

SOFT1

8
7
6
5

UG_VGAA

1
2
3
4

PQ34
SI4810DY-T1-E3_SO8

8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4

12

PC149
0.1U_0603_25V7K
2
1

3
PQ33
SI4810DY-T1-E3_SO8

PR178
@ 0_0402_5%

PC156
0.01U_0402_25V7Z
2
1

1
PR177
2.26K_0402_1%
2
1

PC154
@330U_D2_2.5VM

1
2

PC153
330U_D2_2.5VM

PC155
4.7U_0805_6.3V6K

PU14
1SOFT_VGA

GND

PL12
1.4UH_SSF-13056-1R4_15.5A_+-20%

PC147
0.01U_0402_25V7Z

PR172
2.2_0603_5%

BOOT_V1.8

BOOT_VGA

+VGA_COREP

1
2
3
4

PQ32
SI4800DY-T1-E3_SO8

51_1206_5%

PC143
2200P_0402_50V7K
2
1

PR171

PC142
4.7U_1206_25V6K
2
1

PC141
4.7U_1206_25V6K
2
1

PC140
2200P_0402_50V7K
2
1

PC139
4.7U_1206_25V6K
2
1

PC138
4.7U_1206_25V6K
2
1

PJP21
@ JUMP_43X118

Compal Secret Data

Security Classification
Issued Date

2005/03/22

2006/03/22

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title
Size Document Number
Custom LA-2841
Date:

Rev
1.0

Thursday, December 15, 2005

Sheet
1

54

of

60

+1.2VSP/+0.9VSP

6
5
2
1

PQ36
@ SI3445DV_TSOP6

2
3

FB_V1.2

REF_V1.2

1
2

PC166
10U_1206_6.3V7K

PC202
@ 470P_0402_50V8J

1
2

PC165
220U_D2_4VM

2VREF_1999

PR247
499K_0402_1%

1
2

PC210
22P_0402_50V8J

PR246
330K_0402_1%
1
2

2
G

N46

PR196
0_0402_5%
2

EN_VGA# <54>

PU15B
LM393M_SO8
7 O

PC205
4700P_0402_25V7K

VS

PU15A
LM393M_SO8

O
G

N62

2
B

PQ51
2SA1036K_SOT23
C

1
2

N61

PD30
@ EC31QS04

PD29
EC31QS04
1

VS

2
B

PC204
0.1U_0603_25V7K

PR245
1K_0603_5%

PR244
10K_0402_5%

PQ50
HMBT2222A_SOT23
2
1

PC203
2200P_0402_50V7K

PQ57
SI3445DV_TSOP6

2
1N63 1

PD28
RB751V_SOD323

PC162
22U_1206_6.3V6M

PC161
22U_1206_6.3V6M

PHASE_V1.2

6
5
2
1

PR243
191K_0402_1%

VIN_V1.2

+1.2VSP
PL14
5UH_SPC-06704-5R0A GP_2.9A_30%
1
2

PJP22
@ JUMP_43X39

+5VALW

SN7002N_SOT23
PQ37

+1.8VS

PJP24
@ JUMP_43X118

NC

VREF

NC

VOUT

NC

TP

+3VALW

GND

1
PC169

PR201
@ 1K_0402_1%

@ 10U_1206_6.3V7K

PC170
@ 1U_0603_16V6K

PU16
@ APL5331KAC-TR_SO8
1 VIN
VCNTL 6

VIN_V0.9

1
2

+0.9VGAP

PC173
@ 10U_1206_6.3V7K

1
2

PC171
@ 0.1U_0402_16V7K

1
2

PR203
@ 1K_0402_1%

PQ39
@ 2N7002_SOT23

N48 2
G

PC172
@ 0.1U_0402_16V7K

SUSP

<47,52>

VREF_V0.9
PR202
@ 0_0402_5%
SUSP 1
2

Compal Secret Data

Security Classification
2005/03/2

Issued Date

Deciphered Date

2006/03/22

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

VGA1.2V/VGA0.9V

Size Document Number

Custom
Date:

Thursday, December 15, 2005

Rev
1.0
Sheet
1

55

of

60

Battery Connect/OTP

BATT+

BATT+

BATT++

PC174
1000P_0402_50V7K

PL15
FBM-L18-453215-900LMA90T_1812

PC175
0.01U_0402_25V7Z

PCN2

BATT+

SMD

SMD

SMC

SMC

Res

Temp

GND

PR204
100_0402_5%
1
2
1

EC_SMD_1 <44,45>

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

EC_SMC_1 <44,45>

PR205
100_0402_5%
TS

2 BATT_TEMP

BATT_TEMP <44>

PR206
1K_0402_5%

SUYIN_200045MR006G110ZR

+3VALWP

PR207
6.49K_0402_1%
VL

VL

1
PR209
470K_0402_1%

PU17A

OTPREF

1
2
PR212
470K_0402_1%

N55

PQ40
2N7002_SOT23

2
G

LM393M_SO8

1
PC178
1000P_0402_50V7K

VS

PR214
470K_0402_1%

PR213
20K_0603_1%

PC177
0.22U_0603_16V7K

VL

PR211
215K_0603_1%
N54
1
2

N52

PR210
0_0402_5%

PR208
470K_0402_1%
1
2

N53

CPU

<48,50>

PH3
100K_0603_1%_TH11-4H104FT

SMART
Batte ry:
1.BATT+
2.SMBD
3.SM BC
4.R es
5. Temp
6.GND

MAINPWON

PJPB1 battery connector

PC176
0.1U_0603_25V7K

VS

PU17B

LM393M_SO8

Compal Secret Data

Security Classification
Issued Date

2005/03/01

2006/03/01

Deciphered Date

Title

BATTERY CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number

Custom LA-2841
Date:

Rev
1.0
Sheet

Thursday, December 15, 2005

1

56

of

60

Version change list (P.I.R. List)

Item

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

50
51
52
53

Modify list

Reason for change

Rev.

PG#

Page 1 of 1

Modify by

Add R579 and R580 for EC PA/PR detec

EC team request

Rev0.2

P44

BOM del C591 220U_D2 for +VCCP bypass capacitance

Cost down

Rev0.2

P6

6/6 '05

U44 pin5 change from +5VAMP to +5V

Design modify

Rev0.2

P40

6/6 '05

U44 pin3 change from GNDA to GND

Design modify

Rev0.2

P40

6/6 '05

JP21 50pin contact to U31 F25pin

support system memory throttling

Rev0.2

P13

6/6 '05

JP24 50pin contact to U31 H26pin

support system memory throttling

Rev0.2

P14

6/6 '05

Add D26

Add RTC Battery life

Rev0.2

P28

6/6 '05

BOM del R51

Change NB strap pin CFG9 to Normal Operation

Rev0.2

P11

6/6 '05

Change R562 from 649K_0402 to 649_0402_1%

BOM error fix LAN can't link

Rev0.2

P35

6/6 '05

Change R558 from3.3K_0402 to 200_0402_5%

BOM error fix LAN can't link

Rev0.2

P35

6/6 '05

U24 contact to CPUSB#

Reserve new card detect input

Rev0.2

P44

6/6 '05

BOM del R307

no need EC control new card reset

Rev0.2

P44

6/6 '05

Add R582 @0_0402

Reserve

Rev0.2

P35

6/6 '05

Cancel U12 pin3 contact to +3VLAN

Design modify for LAN function fix LAN can't link Rev0.2

P35

6/6 '05

IFPAB_PLLVDD PLLVDD VID_PLLVDD change from 3.3V to 2 .5V

G72 G73 power modify

Rev0.2

P20

6/6 '05

PEX_CFG 0~2

Overridden CFG modify

Rev0.2

P26

6/6 '05

ME update

Rev0.2

P37

6/6 '05

6/6 '05

change from 100 to 001

Add JP34 for mini-PCIE card

Del BOM R359,R349,R361,D9,D10,Q23

For TI 7412 modify request

Rev0.2

P32

6/7 '05

Change MSBS_SDCMD_SMWE_FIXED# to MSBS_SDCMD_SMWE#

For TI 7412 modify request

Rev0.2

P32

6/7 '05

Change SDCLK_SMRE_FIXED# to SDCLK_SMRE#

For TI 7412 modify request

Rev0.2

P32

6/7 '05

Change SDWP#_SMCE_FIXED# to SDWP#_SMCE#

For TI 7412 modify request

Rev0.2

P32

6/7 '05

Change SM_RB_FIXED# to SM_RB#

For TI 7412 modify request

Rev0.2

P32

6/7 '05

Change R554,R556,R557,R559 from 10K to 2.2K

For TI 7412 modify request

Rev0.2

P32

6/7 '05

Del R369,Q20,Q9,C446,JP29,JOPEN1,JOPEN2

Cancel TV tuner function

Rev0.2

P41

6/7 '05

Change LINK_LED100# contact to U41 pin27

Customer request for LAN link LED state

Rev0.2

P35

6/8 '05

Add R583,R584 75 ohm contact to JP19 and RJ45_GND

LAN modify

Rev0.2

P35

6/8 '05

Swap DQSA0~7/DQSA#0~7 and DQSC0~7/DQSC#0~7

Schematic error modify

Rev0.2

P19

6/8 '05

Add R585 LID_SW# 10K pull-high reserve

LID_SW# floating

Rev0.2

P44

6/13 '05

U6 pin D23 SLP_S4# contact to U24 pin35

EC need detect SLP_S4# for S4 state

Rev0.2

P44

6/13 '05

BOM update add R388

DOCK_MICR need pull-high to +CODEC_REFC

Rev0.2

P38

6/13 '05

Change WL_PRIORITY contact to JP18 pin3 and BT_PRIORITY contact

to JP18 pin5.

pin define swap

Rev0.2

P37

6/14 '05

BOM add R587,R588,R589,R590 0 ohm

for NV72 CLK swap pin rework

Rev0.2

P19

6/14 '05

JP17 footprint update

DB1 footprint error, fix can't TV-out

Rev0.2

P17

6/14 '05
6/17 '05

Del R587,R588,R589,R590 0 ohm

for NV72 chipset modify

Rev0.3

P19

Add R586,R587

UMA or Discrrte PCBA detect

Rev0.3

P44

6/27 '05

Change R145,R146 from 88.7K to 88.7 ohm

BOM error

Rev0.3

P18

6/28 '05

Change C419,C421 form 33P to 22P_0402

improve TV out quility.

Rev0.3

P15

6/28 '05

Add R588

TI recommend(It can avoid the small noise

form this SPKROUT pin)

Rev0.3

P32

6/30 '05
6/30 '05

JP26 footprint update

ME change new USB connector

Rev0.3

P41

JP3 footprint update

ME change new CRT connector

Rev0.3

P17

Add R589

Dual layout for 9LP306 and SLG8LP462.

Rev0.3

P15

BOM add C591 220U_D2 for +VCCP bypass capacitance

change 220U location with C595

Rev0.3

P06

7/06 '05

BOM del C595 220U_D2 for +VCCP bypass capacitance

For cost down

Rev0.3

P11

7/06 '05

7/05 '05

U24(EC) pin91 add ACZ_RST# input

fix into xp codec out popo noise

Rev0.3

P44

7/06 '05

Add C790,C791,C792,C793,C794,C795,C796 100P_0402

For EMI

Rev0.3

P42

7/06 '05

Add R590,Q46

Switch PCBEEP path

Rev0.3

P29,40 7/07 '05

Add C797 reserve

For EMI

Rev0.3

P37

7/07 '05

Change R94,R141 to @ and change R96,R142 form @ to 128@

For NVDIA change request

Rev0.3

P19

7/08 '05

Change R139,Q6 to @ and change R145 form 87_0402 to 124_0402,

R84 from 130_0402 change to 124_0402

For NVDIA change request

Rev0.3

P18

7/08 '05

Add screw hold H23, H24

ME drawing modify

Rev0.3

P47

7/08 '05

Change LAN LED state, Amber LED indicates activity, Rev0.3

Green LED indicates the link is present

P35

7/09 '05

R36 pin1 change contact to ACTLED#,R43 pin1 change contact to

LINK_LED100#

Add R591 10K_0402 and Q47

fix mute LED power on turn on

Rev0.3

P38

7/11 '05

BOM del R383 4.7K pull-high

EC program this pin as push-pull output

Rev0.3

P42

7/13 '05

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

Title

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

Size

Document Number

Rev
1.0

LA-2841
Date:

Sheet

Thursday, December 15, 2005

5

57

of

60

Version change list (P.I.R. List)

Item

Modify list

Reason for change

Rev.

PG#

54
55
56
57
58

BOM del R101,C161,R467,R88

nvdia recommend

Rev0.3

P18

BOM del R78,R468,R111,R117,R63,R475,R477

nvdia recommend

Rev0.3

P26

7/13 '05

BOM del R108,add R112

nvdia recommend(change to PEX_CFG[2..0]=0x010b)

Rev0.3

P26

7/18 '05

BOM add C599

add 220U cap for 1.8V power decoupling

Rev0.4

P11

8/18 '05

BOM add R455

add 51_0402 resister for intel Yonah B0 sightings Rev0.4

update

P04

8/18 '05

59
60
61
62
63
64
65
66
67

Add Q48,Q49,Q50,R593,R594

modify WLED control circuit for OTS:0164892 issue Rev0.4

P37

8/22 '05

Del D3

modify WLED control circuit for OTS:0164892 issue Rev0.4

P41

8/22 '05

Del R440,R432,Q30

modify WLED control circuit for OTS:0164892 issue Rev0.4

P16

8/22 '05

Add R592

add R592 150 ohm for WLED# current limit

Rev0.4

P37

8/22 '05

JP9 Pin 14 contact to +5VS

change SPDIF LED power from +5V to +5VS

Rev0.4

P42

8/22 '05

Add Q51

Prevent TPS2231 pin2 +3VALW leakage to +3VS

Rev0.4

P34

8/29 '05

switch board need +3VALW provide lie switch power Rev0.4

P42

8/23 '05

TI 7412 pull-high recommend

Rev0.4

P32

8/23 '05

JP3 change new part

change CRT conn from top side to bottom side for

DFX request

Rev0.4

P17

8/24 '05

68
69
70
71

Del C764,R552,R553, Add D28,change U40 to G993 fan control

Fan control circuit change to G993

Rev0.4

P04

8/24 '05

BOM del R47

Intel WW31 document update

Rev0.4

P11

8/29 '05

Add R595/R596/R597/R598/R599

SD card signal add 33 ohm damping resister

Rev0.4

P32

8/30 '05

Add R81/R77 10K_0402

NV72 A1 chip recommend JTAG_TCK pull-high and

JTAG_N pull-down

Rev0.4

P18

8/29 '05

72
73
74
75
76
77
78
79
80
81

Del clock generators difference clock 49.9ohm termination

ICS9LP306 clock generators update

Rev0.4

P15

8/29 '05

Change clock generators difference clock 33ohm damping to 10ohm

ICS9LP306 clock generators update

Rev0.4

P15

8/29 '05

Change R266 from 475 ohm to 2.4K ohm

ICS9LP306 clock generators update

Rev0.4

P15

8/29 '05

Add D29/D30/D31/D32/D33/D34/D35/D36

SD card signal add diode for Voltage clamp

Rev0.4

P32

8/30 '05

Move C8/C11/C10/C3/C4/C5/C2/C13/C14/C34/C35/C1 for layout

ME update limit area for CPU

Rev0.4

P06

8/30 '05

Change R591 from 10K ohm to 100 ohm

Fix OTS:163350 calgary's mute LED can't display

Rev0.4

P38

8/30 '05

JP34 pin50 change contact from PM_EXTTS#1 to PM_EXTTS#0

Intel WW31 document update

Rev0.4

P14

8/30 '05

U31 pinH6 change contact from PM_EXTTS#1 to DPRSLPVR

Intel WW31 document update

Rev0.4

P07

8/30 '05

D26 pin2 change contact from +3VALW to LDO3

Add RTC battery life

Rev0.4

P28

8/30 '05

BOM change R562 from 649 ohm to 619 ohm and change U12 to new
part

LAN performance modify

Rev0.4

P35

8/30 '05
8/30 '05

Add R600 100 ohm and DEL C608 @

HP recommend

Rev0.4

P37

Add R601 100 ohm

HP recommend

Rev0.4

P41

8/30 '05

Reserve C810~C821 0.1u cap

For EMI

Rev0.4

P42

8/30 '05

Add L32 and C822 on SPDIF signal

For EMI

Rev0.4

P42

8/30 '05

Add C802 /C803 /C804 /C805 1000P for

CLKREQA#/CLKREQB#/CLKREQC#/CLKREQD#

For EMI

Rev0.4

P15

8/30 '05

87

U40 pin5,6,7,8 contact to GND

schematic update for SI2 fan can't full trun on

issue

Rev0.5

P04

10/26 '05

88
89
90
91

change C599 from 220U to 330U

Steady the 1.8V

Rev0.5

P11

10/26 '05

nvdia recommend

Rev0.5

P21

10/28 '05

change R510,R75,R533,R168 from 120ohm to 499ohm for NV73 only

nvdia recommend

Rev0.5

P22~25

10/26 '05

straps table PEX_CFG[2:0] from 010 to 001 and PCI_DEVID[3:0]

NV73M from 1010 to 1011

nvdia recommend

Rev0.5

P26

10/26 '05

Add C825 15P_0402 for MSCLK_SDCLK_SMELWP# signal

For EMI

Rev0.5

P32

10/26 '05

Add C823 1000P_0402 for +VCC_SD

For EMI

Rev0.5

P32

10/26 '05

Add C824 1000P_0402 for +VCC_SM_XD

For EMI

Rev0.5

P32

10/26 '05

Add C826 1000P_0402 for JP32 pin4

For EMI

Rev0.5

P32

10/26 '05

change PCM_SPK pull down R588 from 43K to 10K

TI recommend

Rev0.5

P32

10/26 '05

D29,D30,D31,D32 pin1 contact to +VCC_MS

schematic update for SI2 MS card can't work issue Rev0.5

P32

10/26 '05

Add R607 22ohm and @ C827 10P

Reserve

Rev0.5

P32

10/26 '05

U18 pinG6 contact to +3VS

TI recommend

Rev0.5

P33

10/26 '05

Add @ R606 110ohm

Reserve

Rev0.5

P35

10/26 '05

Change Q46 to U45 analog switch

design change

Rev0.5

P40

10/26 '05

Change U38 pin3,4 form +5VALW to +5V

design change

Rev0.5

P41

10/26 '05

Rev0.5

P41

10/26 '05

Add D38~D45 for KB ESD solution

For ESD request

Rev0.5

P42

10/26 '05

AIR_ACIN change contact to U24 pin81 and add R605 for BID
define, add D37.

design change

Rev0.5

P44

10/26 '05

Compal Secret Data

Security Classification
Issued Date

Add R103 40.2ohm

Change Q2 from AO3413 to AO3419

Page 2 of 3

7/13 '05

JP5 Pin 25 contact to +3VALW

92
93
94
95
96
97
98
99
100
101
102
103
104
105

Modify by

BOM change R554/R557/R556 to 100K, change R559 to 22K

82
83
84
85
86
3

2005/03/10

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

Title

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

Size

Document Number

Rev
1.0

LA-2841
Date:

Sheet

Thursday, December 15, 2005

5

58

of

60

Version change list (P.I.R. List)

Item

106
107
108
109
110
111
112

Modify list

Reason for change

Rev.

PG#

Add D46

ESD

Rev1.0

P17

12/08 '05

RESERVE Q52 / C828 / R608

CONTROL RTC RESET

Rev1.0

P28

12/08 '05

ADD R612

CIR OUTPUT IS OPEN-DRAIN

Rev1.0

P42

12/08 '05

CANCEL C811 / C812 AND ADD D47

ESD

Rev1.0

P42

12/08 '05

CANCEL Q45 AND ADD U48 / C830

FIX ODD CAUSE BOOT LATE ISSUE

Rev1.0

P43

12/08 '05

CANCEL D37 AND RESERVE U47 / C51 / R611

IMPROVE EC RESET SIGNAL

Rev1.0

P44

12/08 '05

RESERVE U46 / C829 / R609 / Q53 / R610

CONTROL WRITE SIGNAL OF FLASH ROM

Rev1.0

P45

12/08 '05

Page 3 of 3

Modify by

Compal Secret Data

Security Classification
Issued Date

2005/03/10

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1

Title

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

Size

Document Number

Rev
1.0

LA-2841
Date:

Sheet

Thursday, December 15, 2005

5

59

of

60

Version change list (P.I.R. List)

Item

Reason for change

Power section
PG#

Page 1 of 1

Modify List

Date

B.Ver#

Solve the oscillate of +3VALWP when plug adapter.

48

Change PC11 from 10U_0805_10V to 0.1U_0603_25V.

2005.06.01

Adjust VGA power rail sequence.

54

Add PQ55, PQ56 and PR249

2005.06.21

To protect PQ21, because SUSP change to 18.5V from 5V.

52

Add PR253 and change PR114 to 510K_0402_5%.

2005.08.10

To save S5 power consumption.

50,48

Add PR254, PR13, PR14, PQ1 and PC8.

Reserve PR255.

2005.08.15

To solve EMI issue.

53,49

Add PR117,PR129,PR119,PR138,PC108 and PC119.

Change PJP16 to PL18 and PR30 from 0_0402 to 2.2_0603.

2005.08.15

To speed up CP mode response.

49

Change PR32 to 10K; PR35 to 6.8K and PC21 to 2200P.

2005.08.23

Reserve capacitor to reduce noise.

49

Reserve PC209.

2005.08.27

To speed up C4 return to C0. follow Intel recommend.

53

Change PR141 from 0_0402_5% to 499_0402_1%.

2005.08.29

To pull up +1.8V power plan to 1.846V.

51

Change PR89 from 10.2K to 10.5K.

2005.10.01

10

To filter high frequency from AirCard.

55

Add PC210 22P_0402_50V.

2005.11.25

Compal Secret Data

Security Classification
Issued Date

2005/03/22

Deciphered Date

2006/03/22

Title

Power PIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number

Custom LA-2841
Date:

Thursday, December 15, 2005

Rev
1.0
Sheet
1

60

of

60

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