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Open the Microwind Editor window.

Select the Foundry file from File menu. Select cmos025.rul file.

Draw the layout of 2 input NAND gate based on the stick diagram in Figure 3.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2

Change to white background

Make sure that your layout obeys all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker

Simulate the Nand gate layout by selecting:


>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.

TIMING DIAGRAM

Part B : Simulating the layout of a Boolean equation.


1. Simulate the Boolean equation layout. Get the the timing diagram of the circuit.
2. Determine the propagation delay of the output. Rise time :8ns Fall time :16ns..
3. Specify the size of your designed circuit : _________ x _________ Area = ____________ 2

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