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Select the Foundry file from File menu. Select cmos025.rul file.
Draw the layout of 2 input NAND gate based on the stick diagram in Figure 3.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
Make sure that your layout obeys all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker
TIMING DIAGRAM