JADAVPUR UNIVERSITY

MICROELECTRONICS TECHNOLOGY
AND VLSI DESIGN
A SUMMER PROGRAMME

ELECTRONIC DESIGN
AUTOMATION LABORATORY
A Lab-Report by Group: B1.

Electronic Design Automation

Analog EDA laboratory

Acknowledgements

We are grateful to the entire team at the JU IC Centre for their Short Term
Training course on "Microelectronics Technology & VLSI Design". This training
programme and project would not have been possible without the kind
support and help of the entire distinguished faculty at the IC Centre who
conducted the training.

We are also highly indebted to our coordinator Mr Ashok Mondal for his
guidance and constant supervision, as well as for providing necessary
information regarding the project.

Contents
Title

Page number

NMOS

PMOS

RESISTIVE LOAD INVERTER

DIODE MODE INVERTER

11

CMOS INVERTER

13

NMOS CURRENT MIRROR

15

DIFFERENTIAL AMPLIFIER

18

OPERATIONAL AMPLIFIER

20

DIGITAL TO ANALOG CONVERTER

22

NMOS
Date: 26.6.2015
Schematic:

Netlist:
MNMOS_1 Vdd Vg GndGnd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p
PD=6.8u $ $x=5200 $y=3500 $w=400 $h=600
Vdd Vdd Gnd DC 5 $ $x=6600 $y=3600 $w=400 $h=600 $m
Vg Vg Gnd DC 5 $ $x=4300 $y=3500 $w=400 $h=600
.dc Vdd 0 5 0.001 Vg 0 5 1
.include "C:\Users\user\Desktop\ml1_typ.md"
.print I(MNMOS_1)
.end

Id vs Vds graph:

PMOS
Date: 26. 6.2015
Schematic:

Netlist:
MPMOS_1 Vdd Vg GndGnd PMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p
PD=6.8u $ $x=4300 $y=3500 $w=400 $h=600
Vg Vg Gnd

DC -5 $ $x=3300 $y=3200 $w=400 $h=600

Vdd Vdd Gnd

DC -5 $ $x=5200 $y=2700 $w=400 $h=600

.dc Vdd 0 -5 -0.001 Vg 0 -5 -1

.include "C:\Users\user\Desktop\ml1_typ.md"
.print I(MPMOS_1)
.end

Id vs. Vds graph:

Resistive Load Inverter

Date: 26.6.2015
Schematic:

Netlist:
Res1 Vdd Vd R=100 $ $x=4314 $y=4200 $w=149 $h=600
MNMOS_1 Vd Vg Gnd Gnd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p
PD=6.8u $ $x=4100 $y=3400 $w=400 $h=600
Vg Vg Gnd DC 5 $ $x=3100 $y=3100 $w=400 $h=600
Vdd Vdd Gnd DC 5 $ $x=6200 $y=4300 $w=400 $h=600
.dc Vg 0 5 0.001
.include "C:\Users\user\Desktop\ml1_typ.md"
.print V(Vd)
.end

Output waveforms:

Vout vs Vin for R=100ohms

Vout vs. Vin for R=100k ohms

Diode Mode Inverter

Date:26.6.2015

Schematic:

Netlist:
MNMOS_1 Vd Vg GndGnd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p
PD=6.8u $ $x=4100 $y=3400 $w=400 $h=600
MNMOS_2 Vdd Vdd Vd Vd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p
PD=6.8u $ $x=3100 $y=4200 $w=400 $h=600
Vg Vg Gnd DC 5 $ $x=3100 $y=3100 $w=400 $h=600
Vdd Vdd Gnd DC 5 $ $x=6200 $y=4300 $w=400 $h=600
.dc Vg 0 5 .001
.include "C:\Users\user\Desktop\ml1_typ.md"
.print V(Vd)
.end

Output waveforms:
Vout vs. Vin for w=22u

Vout vs. Vin for w=2u

CMOS inverter
Date: 27.6.2015
Schematic::

Netlist:
MNMOS_1 Vout Vin Gnd Gnd NMOS W=450n L=150n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u $ $x=4400 $y=3000 $w=400 $h=600
MPMOS_1 Vout Vin Vdd Vdd PMOS W=1.59u L=150n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u $ $x=4400 $y=3900 $w=400 $h=600
Vin Vin Gnd DC 1 $ $x=3400 $y=3300 $w=400 $h=600
Vdd Vdd Gnd DC 1 $ $x=5900 $y=4000 $w=400 $h=600 $m
.dc Vin 0 1 0.001
.include "C:\Users\user\Desktop\dual.md"
.print V(Vout) V(Vin)
.end

Output waveform:
Vout vs. Vin for k=1.4044

NMOS Current Mirror

Date: 27.6.2015
Netlist:
When Wref = W2:
RResistor_1 Vdd Id

R=10k $ $x=6914 $y=4600 $w=149 $h=600

MNMOS_1 VG VG Gnd Gnd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p

PD=6.8u $ $x=5000 $y=3700 $w=400 $h=600 $m
MNMOS_2 Id VG Gnd Gnd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p
PD=6.8u $ $x=6700 $y=3700 $w=400 $h=600
VVoltageSource_1 Vdd Gnd

DC 5 $ $x=3500 $y=5600 $w=400 $h=600

ICurrentSource_1 Vdd VG

DC 30u $ $x=4800 $y=4600 $w=400 $h=600

.tran 1n 40n
.include "C:\Users\am_ju\Desktop\ml1_typ.md"
.print I(MNMOS_1) I(MNMOS_2)
.end

When Iref= ID2:

RResistor_1 Vdd Id R=10k $ $x=6914 $y=4600 $w=149 $h=600

MNMOS_1 VG VG Gnd Gnd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=5000
$y=3700 $w=400 $h=600 $m
MNMOS_2 Id VG Gnd Gnd NMOS W=20.5992u L=2u AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=6700
$y=3700 $w=400 $h=600
VVoltageSource_1 Vdd Gnd DC 5 $ $x=3500 $y=5600 $w=400 $h=600
ICurrentSource_1 Vdd VG DC 30u $ $x=4800 $y=4600 $w=400 $h=600
.tran 1n 40n
.include "C:\Users\am_ju\Desktop\ml1_typ.md"
.print I(MNMOS_1) I(MNMOS_2)
.end

When ID2 = Iref/2:

RResistor_1 Vdd Id

R=10k $ $x=6914 $y=4600 $w=149 $h=600

MNMOS_1 VG VG Gnd Gnd NMOS W=22u L=2u AS=2.25p PS=6.8u AD=2.25p

PD=6.8u $ $x=5000 $y=3700 $w=400 $h=600 $m
MNMOS_2 Id VG Gnd Gnd NMOS W=10.2996u L=2u AS=2.25p PS=6.8u AD=2.25p
PD=6.8u $ $x=6700 $y=3700 $w=400 $h=600
VVoltageSource_1 Vdd Gnd

DC 5 $ $x=3500 $y=5600 $w=400 $h=600

ICurrentSource_1 Vdd VG

DC 30u $ $x=4800 $y=4600 $w=400 $h=600

.tran 1n 40n
.include "C:\Users\am_ju\Desktop\ml1_typ.md"
.print I(MNMOS_1) I(MNMOS_2)
.end

Output waveforms:
When Wref = W2:

When Iref= ID2:

When ID2 = Iref/2:

Calculation:
For calculation of common mode gain, peak voltage of input sine wave is taken 1V.
=0.006
For calculation of differential mode gain, peak voltage of input wave is 1mV.
=787.8
CMRR=131300

Differential Amplifier
Date: 27.6.2015
Netlist:
MPMOS_1 Vd Vd Vdd Vdd PMOS w=4.5u l=2u
MPMOS_2 Vout Vd Vdd Vdd PMOS w=4.5u l=2u
MNMOS_1 Vd Vin1 Vc Vc NMOS w=22u l=2u
MNMOS_2 Vout Vin2 Vc Vc NMOS w=22u l=2u
MNMOS_3 Iref Iref Vss Vss NMOS w=10u l=2u
MNMOS_4 Vc Iref Vss Vss NMOS w=10u l=2u
Vdd Vdd Gnd DC 2.5
Vss Vss Gnd DC -2.5
Iref Vdd Iref DC 30u
Vin1 Vin1Gnd SIN (0 1m 1k 0 0 0)
Vin2 Vin2Gnd SIN (0 -1m 1k 0 0 0)
.tran 1n 1m
.include "C:\Users\user\Desktop\ml1_typ.md"
.print V(Vin1) V(Vin2) V(Vout)
.end

Waveform:
Common Mode:

Differential Mode:

Calculation:

Voc=0.006
Ac=0.006
Vod=1.5756
Ad=Voc/2Vb=787.8
CMRR=131300

Operational Amplifier
Date:29.6.2015
Netlist:
.subckt diffamp Vin1 Vin2 Vdd Vss Iref Vout
MPMOS_1 Vd Vd Vdd Vdd PMOS w=15u l=2u
MPMOS_2 Vout Vd Vdd Vdd PMOS w=15u l=2u
MNMOS_1 Vd Vin1 Vc Vc NMOS w=3u l=2u
MNMOS_2 Vout Vin2 Vc Vc NMOS w=3u l=2u
MNMOS_3 Iref Iref Vss Vss NMOS w=4.5u l=2u
MNMOS_4 Vc Iref Vss Vss NMOS w=4.5u l=2u
.ends

.subckt ca Vin Vb Vdd Vss Vout

MPMOS_1 Vout Vin Vdd Vdd PMOS w=50u l=2u
MNMOS_1 Vout Vb Vss Vss NMOS w=10u l=2u
.ends

Vin1 Vin1 Gnd SIN(0 .03m 1k 0 0 0)

Vin2 Vin2 Gnd SIN(0 -.03m

1k 0 0 0)

Vdd Vdd Gnd Dc 2.5

Vss Vss Gnd DC -2.5
Iref Vdd Iref DC 30u

Xdiffamp_1 Vin1 Vin2 Vdd Vss Iref Vx diffamp

Xca_1 Vx Iref Vdd Vss Vout ca

.tran 1n 1m

.include "C:\Users\user\Desktop\ml1_typ.md"
.print V(Vin1) V(Vin2) V(Vout)
.end

Waveform:

Calculation:
For calculation of common mode gain, peak voltage of input sine wave is taken 0.7V-0.75V.
=0.07
For calculation of differential mode gain, peak voltage of input wave is 0.03mV.
=89.05
CMRR=44525

Digital to Analog Converter

Date:29.6.2015

Netlist:
.subckt diffamp Vin1 Vin2 Vdd Vss Iref Vout
MPMOS_1 Vd Vd Vdd Vdd PMOS w=15u l=2u
MPMOS_2 Vout Vd Vdd Vdd PMOS w=15u l=2u
MNMOS_1 Vd Vin1 Vc Vc NMOS w=3u l=2u
MNMOS_2 Vout Vin2 Vc Vc NMOS w=3u l=2u
MNMOS_3 Iref Iref Vss

Vss NMOS w=4.5u l=2u

MNMOS_4 Vc Iref Vss Vss NMOS w=4.5u l=2u

.ends
.subckt ca Vin Vb Vdd Vss Vout
MPMOS_1 Vout Vin Vdd Vdd PMOS w=50u l=2u
MNMOS_1 Vout Vb Vss Vss NMOS w=10u l=2u
.ends
R10 V0 Gnd R=1k
R11 V1 V0

R=1k

R12 V2 V1 R=1k
R13 V3 V2 R=1k
R20 D0 V0 R=2k
R21 D1 V1

R=2k

R22 D2 V2

R=2k

R23 D3 V3 R=2k
Vdd Vdd Gnd Dc 2.5
Vss Vss Gnd DC -2.5

Iref Vdd Iref DC 30u

VD0 D0 Gnd PULSE (0 2.5 0 0.01n 0.01n 100n 200n)
VD1 D1 Gnd PULSE (0 2.5 0 0.01n 0.01n 200n 400n)
VD2 D2 Gnd PULSE (0 2.5 0 0.01n 0.01n 400n 800n)
VD3 D3 Gnd PULSE (0 2.5 0 0.01n 0.01n 800n 1600n)
Xdiffamp_1 Vin V3 Vdd Vss Iref Vx diffamp
Xca_1 Vx Iref Vdd Vss Vin ca
.tran 1n 1600n
.include "C:\Users\user\Desktop\ml1_typ.md"
.print V(Vin) V(D0) V(D1) V(D2) V(D3)
.end

Output Waveform:

Electronic Design Automation

Project Report: Digital EDA

Acknowledgements

We are grateful to the entire team at the JU IC Centre for their Short Term
Training course on "Microelectronics Technology & VLSI Design". This training
programme and project would not have been possible without the kind
support and help of the entire distinguished faculty at the IC Centre who
conducted the training.

We are also highly indebted to our coordinator Mr Ashok Mondal for his
guidance and constant supervision, as well as for providing necessary
information regarding the project.

Contents
CMOS............................................................................................................................................................. 29
NAND GATE ................................................................................................................................................... 31
XOR ............................................................................................................................................................... 33
AND GATE USING TRANSMISSION GATE ........................................................................................................ 35
OR GATE USING TRANSMISSION GATE........................................................................................................... 39
PMOS LAYOUT ............................................................................................................................................... 43
NMOS LAYOUT .............................................................................................................................................. 44
CMOS LAYOUT ............................................................................................................................................... 45

CMOS
Date: 30.6.2015
Schematic:

Netlist:
MNMOS_1 Opt A Gnd Gnd NMOS W=450n L=150n AS=405f PS=2.7u AD=405f
PD=2.7u $ $x=4400 $y=4200 $w=400 $h=600
MPMOS_1 Opt A Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=4400 $y=5000 $w=400 $h=600
Va A Gnd DC 1 $ $x=3700 $y=4100 $w=400 $h=600
Vdd Vdd Gnd

DC 1 $ $x=6000 $y=4500 $w=400 $h=600

.tran 0.1n 400n

.include "C:\Users\Dell\Documents\Tanner EDA\dual.md"
.print V(a) V(opt)
.power vdd 0.1n 400n
.measure tran delaytime trig V(Vout) val=1 fall=1 targ V(Vin) val=1
rise=1
.end

Output Waveform:

Output Results:
Average Power consumed=

Delay time= 74.01ps

Power delay profile= 5.92

NAND gate
Date:30.6.2015
Schematic

Netlist
MNMOS_1 out A n1 Gnd NMOS W=450n L=150n AS=405f PS=2.7u AD=405f
PD=2.7u $ $x=4500 $y=3400 $w=400 $h=600
MNMOS_2 n1 B Gnd Gnd NMOS W=450n L=150n AS=405f PS=2.7u AD=405f
PD=2.7u $ $x=4500 $y=2600 $w=400 $h=600
MPMOS_1 out A Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=3800 $y=4400 $w=400 $h=600
MPMOS_2 out B Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=5500 $y=4400 $w=400 $h=600 $m
Vdd Vdd Gnd

DC 1 $ $x=7800 $y=4500 $w=400 $h=600

Va a gnd BIT ({0011} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n

ft=0.1n)
Vb b gnd BIT ({0101} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n
ft=0.1n)
.tran 0.1n 800n
.include "C:\Users\user\Desktop\dual.md"

.print V(a) V(b) V(out)

.measure tran delay trig V(a) val=1 fall=1 targ V(out) val=1 rise=1
.power Vdd 0.1n 400n
.end

Waveform

Results
Average power consumed=
Delay time=
Power delay profile=

s
J

XOR
Date:30.6.2015
Schematic

Netlist
MNMOS_1 Abar A GndGnd NMOS W=450n L=150n
MNMOS_3 outpoutbarGndGnd NMOS W=450n L=150n
MNMOS_4 Bbar B GndGnd NMOS W=450n L=150n
MNMOS_5 outbar A n2 Gnd NMOS W=450n L=150n
MNMOS_6 n2 BbarGndGnd NMOS W=450n L=150n
MNMOS_7 outbarAbar n3 Gnd NMOS W=450n L=150n
MNMOS_8 n3 b GndGnd NMOS W=450n L=150n
MPMOS_1 n1 A VddVdd PMOS W=900n L=150n
MPMOS_2 outbarAbar n1 Vdd PMOS W=900n L=150n
MPMOS_3 n1 BbarVddVdd PMOS W=900n L=150n
MPMOS_4 outbar B n1 Vdd PMOS W=900n L=150n
MPMOS_5 Abar A VddVdd PMOS W=900n L=150n

MPMOS_6 Bbar B VddVdd PMOS W=900n L=150n

MPMOS_8 outpoutbarVddVdd PMOS W=900n L=150n
VddVddGnd

DC 1 $ $x=1900 $y=5400 $w=400 $h=600

va a gnd BIT ({0011} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n

ft=0.1n)
vb b gnd BIT ({0101} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n
ft=0.1n)
.include "C:\Users\user\Desktop\dual.md"
.tran 0.1n 800n
.print v(a) v(b) v(outp)
.measure trandelaytime trig V(outp) val=1 fall=1 targ v(b) val=1
rise=2
.power vdd 0.1n 400n
.end

Waveform

Output results
Average power=

Delay time=199.93 ns
PDP=5.51

And gate using Transmission Gate

Date:1.7.2015
Inverter
Schematic:

Symbol:

Transmission gate(Tg)
Schematic:

Symbol:

Top level schematic:

Netlist:
.subcktInvAAbarGndVdd
Mm1 Abar A GndGnd NMOS W=450n L=150n AS=405f PS=2.7u AD=405f PD=2.7u $ $x=4600 $y=2700
$w=400 $h=600
Mm2 Abar A VddVdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f PD=3.6u $ $x=4600 $y=3500
$w=400 $h=600
.ends
.subcktTgIn Out S SbarGndVdd
Mm1 Out S InGnd NMOS W=450n L=150n AS=405f PS=2.7u AD=405f PD=2.7u $ $x=5300 $y=1900
$w=600 $h=400 $r=270 $m
Mm2 Out Sbar InVdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f PD=3.6u $ $x=5200 $y=3300
$w=600 $h=400 $r=90 $m
.ends
XInv1 A AbarGndVddInv $ $x=3940 $y=3000 $w=2680 $h=1800
XTg1 Gnd Y Abar A GndVddTg $ $x=4700 $y=4500 $w=1400 $h=1200
XTg2 B Y A AbarGndVddTg $ $x=4700 $y=2900 $w=1400 $h=1200
VddVddGnd DC 1 $ $x=7000 $y=4900 $w=400 $h=600

VaAGnd BIT ({0011} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n ft=0.1n)
Vb B Gnd BIT ({0101} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n ft=0.1n)
.tran 0.1n 400n
.include "C:\Users\user\Desktop\dual.md"
.print V(A) V(B) V(Y)
.power Vdd 0.1n 400n
.measure trandelaytime trig v(b) val=1 rise=2 targ v(y) val=1 rise=1
.end

Waveform:

Results:
Average power=5.74
Delay time=110.80ps
PDP=6.36

OR gate using Transmission Gate

Date:1.7.2015
Inverter
Schematic:

Symbol:

Transmission gate(Tg)
Schematic:

Symbol:

Top level schematic:

Netlist:
.subcktInvAAbarGndVdd
Mm1 Abar A GndGnd NMOS W=450n L=150n AS=405f PS=2.7u AD=405f PD=2.7u $ $x=4600 $y=2700
$w=400 $h=600
Mm2 Abar A VddVdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f PD=3.6u $ $x=4600 $y=3500
$w=400 $h=600
.ends
.subcktTgIn Out S SbarGndVdd
Mm1 Out S InGnd NMOS W=450n L=150n AS=405f PS=2.7u AD=405f PD=2.7u $ $x=5300 $y=1900
$w=600 $h=400 $r=270 $m
Mm2 Out Sbar InVdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f PD=3.6u $ $x=5200 $y=3300
$w=600 $h=400 $r=90 $m
.ends
XInv1 A AbarGndVddInv $ $x=3940 $y=3000 $w=2680 $h=1800
XTg1 Gnd Y Abar A GndVddTg $ $x=4700 $y=4500 $w=1400 $h=1200
XTg2 B Y A AbarGndVddTg $ $x=4700 $y=2900 $w=1400 $h=1200
VddVddGnd DC 1 $ $x=7000 $y=4900 $w=400 $h=600

VaAGnd BIT ({0011} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n ft=0.1n)
Vb B Gnd BIT ({0101} pw=100n lt=100n ht=100n on=1 off=0 rt=0.1n ft=0.1n)
.tran 0.1n 400n
.include "C:\Users\user\Desktop\dual.md"
.print V(A) V(B) V(Y)
.power Vdd 0.1n 400n
.measure trandelaytime trig v(b) val=1 rise=2 targ v(y) val=1 rise=1
.end

Waveform:

Results:
Average power=9.47
Delay time=111.39ps
PDP=1.054

PMOS layout
Date:2.7.2015
Layout:

Netlist:
D1 VddVddD_lateral A=3e-015 P=6.002e-006 $ (11 10.499 14 10.5)
M1 Gnd_ In VddVdd PMOS l=3e-006 w=3e-006 ad=9e-012 as=7.5e-012 pd=1.2e-005 ps=1.1e-005 $
(11 13 14 16)

Area:

NMOS layout
Date:2.7.2015
Layout:

Netlist:
D1 Gnd_ Gnd_ D_lateral A=3e-015 P=6.002e-006 $ (7 12 10 12.001)
M1 vdd In Gnd_ Gnd_ NMOS l=3e-006 w=3e-006 ad=9e-012 as=9e-012 pd=1.2e-005 ps=1.2e-005 $
(7 15 10 18)

Area:

CMOS layout
Date:2.7.2015
Layout:

Netlist:
D1 VddVddD_lateral A=3e-015 P=6.002e-006 $ (-9.001 27.5 -9 30.5)
D2 Gnd_ Gnd_ D_lateral A=3e-015 P=6.002e-006 $ (6.5 11.5 9.5 11.501)
M1 out in Gnd_ Gnd_ NMOS l=3e-006 w=3e-006 ad=9e-012 as=7.5e-012 pd=1.2e-005 ps=1.1e-005 $
(6.5 14 9.5 17)
M2 out in VddVdd PMOS l=3e-006 w=3e-006 ad=9e-012 as=7.5e-012 pd=1.2e-005 ps=1.1e-005 $ (6.5 27.5 -3.5 30.5)

Area:
8.28