Вы находитесь на странице: 1из 1

MARTHANDAM COLLEGE OF ENGINEERING AND

TECHNOLOGY
MODEL EXAM I -2016

Semester VI
ELECTRONICS & COMMUNICATION ENGINEERING
CS6303 COMPUTER ARCHITECTURE
Time: 3 Hrs
Maximum Marks : 100
Staff: D. Navis Nayagam
_________________________________________________
Part A (10x2=20)
Answer All Questions
1.
2.
3.
4.
5.

What is the need for Speculation?


What is an Exception?
What is Multithreading?
Differentiate Programmed I/O and Interrupt I/O
What is the purpose of Dirty/Modified bit in Cache
Memory?
6. What is a branch prediction buffer?
7. Differentiate between Strong scaling and weak scaling.
8. Compare UMA and NUMA multiprocessors
9. What is the need to implement memory as a hierarchy?
10. Point out how DMA can improve I/O speed
Part B (5 X 16 = 80)
11. a)What is Hazard? Explain i t s t y p e s with
suitable examples.
(16)
(Or)
(b) Explain i n detail how exceptions are handled
in MIPS architecture?
(16)
12. a) Explain Instruction level Parallel Processing. State
the challenges of parallel Processing. (16)
(Or)
b) Explain in detail about Multi-core Processor. (16)

13. a) Discuss a b o u t SISD, MIMD, SIMD, SPMD and


VECTOR systems .
(16)
(Or)
b) What is Hardware Multithreading? Compare and
contrast Fine grained Multi-Threading
and coarse
grained Multi-Threading. (16)
14. a) Elaborate on the various memory technologies
and its relevance (16)
(Or)
b) What is virtual memory? Explain the s t e p s
involved in virtual memory address translation. (16)
15. (a) (i) Explain mapping functions in cache memory
to determine how memory blocks are placed in Cache.
(8)
(ii) Explain in detail about the Bus Arbitration
techniques in DMA.
(8)
(Or)
(b) (i) Draw different. memory address layouts
and brief about the technique used to increase
the average rate of fetching words from the main
memory.
(8)
(ii) Explain in detail
about
any two
Standard Input and
Output
Interfaces
required to connect the I/O device to the Bus.
(8)