Practice Homework-1

Digital Logic Design

1. Find the unsigned binary (radix-2) representation of the following numbers (assume 8 bit representation)
a. (128)10
b. (18)10
c. (87)10
d. (193)10
e. (0.984)10
f. (0.123)10
2. Find the signed 2s complement binary representation of the following numbers (assume 8 bit
representation)
a. (127)10
b. (-127)10
c. (-87)10
d. (94)10
e. (103)10
f. (-118)10
3. Perform the following operations, and show your steps (assume 8 bit representation). (As discussed in
class, we first take the 2s complement of N, and the simply do M +N, and so on )
a. M - N, where M = 1110001 and N = 1011101, and both M, N are (positive) unsigned binary
numbers
b. M - N, where M = 1101 and N = 101101, and both M, N are (positive) unsigned binary numbers
4. Perform the following operations, and show your steps (First convert the radix-10 number to signed 2s
complement binary number assuming 8 bit representation)
a. M + N, where M = (-113)10, and N = (93)10, and both M, N are represented as signed 2s
complement
b. M + N, where M = (113)10, and N = (-63)10, and both M, N are represented as signed 2s
complement
c. M - N, where M = (93)10, and N = (11)10, and both M, N are represented as signed 2s complement
d. M - N, where M = (113)10, and N = (-93)10, and both M, N are represented as signed 2s
complement
e. M - N, where M = (-63)10, and N = (-11)10, and both M, N are represented as signed 2s
complement
5. Convert from one number system to another (assume all positive numbers). If necessary, you may
convert to radix-10 first, and then to any other given system.
a. (1100100)2 = (?)5
b. (11011001100100)2 = (?)16
c. (1FBC7)16 = (?)10
d. (1ABD7)16 = (?)5
e. (19FC2)16 = (?)2
f. (0.43321)5 = (?)8
6. Perform the following operation (in the given number system, without converting), and show the steps
a. M + N, where M = (34)5 and N = (44)5
7. Given is a number (24)5
a. Find its 4s complement
1

b. Find its 5s complement

8. Draw the gate-level schematic of the Boolean expression (Do not reduce the expression; Just
implement in the format given, using only AND, OR, INV gates):

'

a. F xy xz (v ' w)

'
'
b. F xyz xz y ' w yz

9. For the Boolean function F AB ' A' B CD C ' D '

a.
b.
c.
d.

Draw the gate-level schematic in the format given (using AND, OR, Ex-OR, INV gates)
Find the truth-table of this Boolean function
Draw the gate-level schematic using only Ex-OR, INV gates
Draw the gate-level schematic using only Ex-NOR, INV gates