axi_gpio_0

S_AXI
s_axi_aclk

leds_4bits

GPIO

s_axi_aresetn

AXI GPIO
axi_mem_intercon
axi_dma_0

processing_system7_0
M_AXI_SG

DDR
FIXED_IO

S00_AXI
DDR

S01_AXI

S_AXI_LITE
M_AXI_MM2S

FIXED_IO

S02_AXI

S_AXIS_S2MM
M_AXI_S2MM

SDIO_0

s_axi_lite_aclk

ACLK

S_AXI_HP0_FIFO_CTRL
M_AXIS_MM2S

USBIND_0

m_axi_sg_aclk

ARESETN[0:0]

S_AXI_HP0
mm2s_prmry_reset_out_n

M_AXI_GP0

m_axi_mm2s_aclk

S00_ACLK

M_AXI_GP0_ACLK
s2mm_prmry_reset_out_n

m_axi_s2mm_aclk

TTC0_WAVE0_OUT

S00_ARESETN[0:0]

TTC0_WAVE1_OUT

M00_ACLK

TTC0_WAVE2_OUT

M00_ARESETN[0:0]

M00_AXI

S_AXI_HP0_ACLK
mm2s_introut

axi_resetn

IRQ_F2P[1:0]
s2mm_introut

FCLK_CLK0

AXI Direct Memory Access

S01_ACLK

FCLK_RESET0_N

S01_ARESETN[0:0]
S02_ACLK

ZYNQ7 Processing System

S02_ARESETN[0:0]

AXI Interconnect

xlconcat_0

rst_processing_system7_0_100M
processing_system7_0_axi_periph

In0[0:0]

slowest_sync_clk

mb_reset

dout[1:0]
In1[0:0]

Concat

ext_reset_in

bus_struct_reset[0:0]

aux_reset_in

peripheral_reset[0:0]

mb_debug_sys_rst
dcm_locked

interconnect_aresetn[0:0]
peripheral_aresetn[0:0]

S00_AXI
ACLK
ARESETN[0:0]
S00_ACLK
M00_AXI
S00_ARESETN[0:0]

Processor System Reset

M01_AXI
M00_ACLK
M00_ARESETN[0:0]
M01_ACLK
M01_ARESETN[0:0]

AXI Interconnect