EC6302 - Digital Electronics

LESSON PLAN
Sub. Code:
Sub.Title:
Dept.:
EC6302
Date:
10/06/2015
III
Page 1 of 6
DIGITAL ELECTRONICS
ECE
Year:
II
Sem:
UNIT - I MINIMIZATION TECHNIQUES AND LOGIC GATES

9
Objective: To introduce basic postulates of Boolean algebra and show the correlation
between Boolean expressions. To introduce the methods for simplifying Boolean expressions.
Session
No./Date
1.
2.
3.
4.
5.
6.
7.
8.
9.
Topics to be covered
Introduction to Digital Electronics, Boolean
postulates and laws, De-Morgans Theorem.
Principle of duality, Minimization of expressions
using Boolean laws.
Minterm, Maxterm, Sum of Products (SOP),
Product of Sums (POS).
Minimization of expressions using Karnaugh
map-3&4 variable K-map.
5-variable K-map, K-map with dont care
conditions.
Quine-McCluskey method of minimization.
Truth table, symbol and expressions of AND, OR,
NOT, NAND, NOR, ExOR and ExNOR.
Implementation of logic function using Universal
gates
Multi level-output gate implementations.
No.
Hrs
Ref.Book
with
Pg.No.
Teaching
Method
T1(35)
BB
T1(39)
BB
T1(46)
BB
T1(67)
BB
T1(79)
BB
T1(112)
BB
T1(56)
BB
T1(87)
BB
T1(95)
BB
T1(498)
BB
10.
Characteristics of TTL and CMOS Logic, Tristate

gates.
11.
TUTORIAL
BB
12.
Review
PPT
13.
University Question Paper Discussion
BB
14.
Test
Total No. of Hours
16
Remark:........................................................................................................................................
......................................................................................................................................................
LESSON PLAN
Sub. Code:
Sub.Title:
Dept.:
EC6302
Date:
10/06/2015
III
Page 2 of 6
DIGITAL ELECTRONICS
ECE
Year:
II
Sem:
UNIT - II COMBINATIONAL CIRCUITS

Objective: To outline the procedures for the analysis and design of combinational circuits.
Session
No./Date.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Design of half adder and full adder.
Design of half subtractor, full subtractor and
parallel binary adder/subtractor.
Disadvantages of parallel adder, carry look ahead
adder.
Design of serial adder/subtractor and BCD adder.
Binary multiplier and binary divider.
Design and implementation of Multiplexer and
Demultiplexer.
Encoder and decoder.
Odd, Even: Parity generators and checker.
Code converters.
2-bit, 4-bit Magnitude comparator.
No.
Hrs
Ref.Book
with
Pg.No.
Teaching
Method
T1(143)
BB
T1(50)
BB
T1(149)
BB
T1(156)
BB
T1(158)
BB
T1(168)
BB
T1(162,
166)
BB
T1(160)
BB
T1(160)
BB
T1(160)
BB
11.
TUTORIAL
BB
12.
Review
PPT
13.
BB
14.
Test
Total No. of Hours
14
Remark:........................................................................................................................................
......................................................................................................................................................
LESSON PLAN
Sub. Code:
Sub.Title:
Dept.:
EC6302
Date:
10/06/2015
III
Page 3 of 6
DIGITAL ELECTRONICS
ECE
Year:
II
Sem:
UNIT - III SEQUENTIAL CIRCUITS

9
Objective: To outline the formal procedures for the analysis and design of sequential circuits.
Session
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Latches, Characteristic table and equation of SR,
JK, D and T flip flop.
Level triggering and edge triggering of flip flop.
Conversion of one flip flop to other flip flops
Realizations of one flip flop using other flip flops,
Master-Slave flip flop.
Asynchronous: ripple counter, Up/Down counter.
Synchronous: Up/Down counters, Programmable
counters.
State diagram, minimization and State assignment.
Excitation table and maps.
Design of Modulo-n counter.
Shift registers, SISO, SIPO, PISO, PIPO ,Universal
shift registers
Shift register counters ,ring counter and shift
counter.
Design of sequence generators.
No.
Hrs
Ref.Book
with
Pg.No.
Teaching
Method
T1(199)
BB
T1(204)
BB
T1(207)
BB
T1(268)
BB
T1(282)
BB
T1(233)
BB
T1(288)
BB
T1(255)
BB
T1(255)
BB
T1(245)
BB
11.
TUTORIAL
12.
Review
PPT
13.
14.
Test
Total No. of Hours
17
Remark:........................................................................................................................................
......................................................................................................................................................
LESSON PLAN
Sub. Code:
Sub.Title:
Dept.:
EC6302
Date:
10/06/2015
III
Page 4 of 6
DIGITAL ELECTRONICS
ECE
Year:
II
Sem:
UNIT - IV MEMORY DEVICES

Objective: To introduce the concept of memories and programmable logic devices.
Session
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Classification of memories- ROM, RAM
ROM Organisation - PROM, EPROM,
EEPROM,EAPROM
RAM organization, - Write and Read operation,
Memory cycle and Timing wave forms.
Memory decoding and memory expansion.
Static RAM Cell, Bipolar RAM cell ,
Dynamic RAM Cell and MOSFET RAM cell.
Introduction to Programmable Logic Devices
Implementation of combinational logic circuits
using PLA.
using ROM, PLA, PAL
using ROM, PLA, PAL
using PAL. Field Programmable Gate Arrays
(FPGA).
No.
Hrs
Ref.Book
with
Pg.No.
Teaching
Method
T1(308)
BB
T1(308)
BB
T1(310)
BB
T1(314)
BB
T1(308)
BB
T1(328)
BB
T1(328)
BB
T1(332)
BB
T1(332)
BB
T1(332)
BB
11.
TUTORIAL
BB
12.
Review
PPT
13.
14.
Test
Total No. of Hours
14
Remark:........................................................................................................................................
......................................................................................................................................................
LESSON PLAN
Sub. Code:
Sub.Title:
Dept.:
EC6302
Date:
10/06/2015
III
Page 5 of 6
DIGITAL ELECTRONICS
ECE
Year:
II
Sem:
UNIT - V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS

9
Objective: To introduce the concept of synchronous and asynchronous sequential circuits
and to design Combinational and Sequential circuits using VERILOG.
Session
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
General sequential Model Classification and
design of synchronous sequential circuit.
Analysis of Synchronous Sequential circuit.
Algorithmic State Machine.
Design of fundamental mode Incompletely
specified State Machines
Design of Pulse mode - Incompletely specified
State Machines
Problems in Asynchronous Circuits - Hazards and
types of hazards.
Design of Hazard free Switching circuits.
Design of Combinational and Sequential circuits
using Verilog.
Design of Combinational and Sequential circuits
using Verilog.
No.
Hrs
Ref.Book
with
Pg.No.
Teaching
Method
T1(210)
BB
T1(210)
BB
T1(210)
BB
T1(436)
BB
T1(436)
BB
T1(469)
BB
T1(469)
BB
T1(174)
BB
T1(174)
BB
10.
TUTORIAL
11.
Review
12.
13.
Test
Total No. of Hours
13
Remark:........................................................................................................................................
......................................................................................................................................................
LESSON PLAN
Sub. Code:
Sub.Title:
Dept.:
EC6302
Date:
10/06/2015
III
Page 6 of 6
DIGITAL ELECTRONICS
ECE
Year:
II
Sem:
CONTENT BEYOND SYLLABUS:

1. K-map Simplification Different methods
INDUSTRY INSTITUTE LACKING:

1. Advanced Processors and their specifications
TEXT BOOKS
1. M. MORRIS MANO, DIGITAL DESIGN, 4TH EDITION, PRENTICE
HALL OF
INDIA PVT. LTD., 2008
/ PEARSON EDUCATION
(SINGAPORE) PVT. LTD., NEW DELHI, 2003.
REFERENCES
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2008
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning,
2006.
3. Charles H.Roth. Fundamentals of Logic Design, 6th Edition, Thomson Learning,
2013
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th
Edition, TMH, 2006
5. Thomas L. Floyd, Digital Fundamentals, 10th Edition, Pearson Education Inc,
2011
6. Donald D.Givone, Digital Principles and Design, TMH, 2003.
Prepared by
Approved by
Name
Mr. C.MOHAMED HASHIM
Dr. G.Suresh
Designation
Assistant Professors/ ECE
Prof. & HOD/ECE
Date
10 /06/2015
10 /06/2015
Signature

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LESSON PLAN

UNIT - I MINIMIZATION TECHNIQUES AND LOGIC GATES

Characteristics of TTL and CMOS Logic, Tristate

University Question Paper Discussion

Total No. of Hours

UNIT - II COMBINATIONAL CIRCUITS

University Question Paper Discussion

Total No. of Hours

UNIT - III SEQUENTIAL CIRCUITS

University Question Paper Discussion

Total No. of Hours

UNIT - IV MEMORY DEVICES

University Question Paper Discussion

Total No. of Hours

UNIT - V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS

University Question Paper Discussion

Total No. of Hours

CONTENT BEYOND SYLLABUS:

INDUSTRY INSTITUTE LACKING:

Mr. C.MOHAMED HASHIM

Assistant Professors/ ECE

Prof. & HOD/ECE

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