Unified Patents Inc. v. Advanced Silicon Technologies, LLC, IPR2016-01026, Paper 1 (May 11, 2016)

IPR2016-01026 Petition
Patent 6,546,439
DOCKET NO.: 2211726-00124
Filed on behalf of Unified Patents Inc.
By: David L. Cavanaugh, Reg. No. 36,476
Daniel V. Williams 45,221
Wilmer Cutler Pickering Hale and Dorr LLP
1875 Pennsylvania Ave., NW
Washington, DC 20006
Tel: (202) 663-6000
Email: David.Cavanaugh@wilmerhale.com
Jonathan Stroud, Reg. No. 72,518
Unified Patents Inc.
1875 Connecticut Ave. NW, Floor 10
Washington, DC, 20009
Tel: (202) 805-8931
Email: jonathan@unifiedpatents.com
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________________________________
BEFORE THE PATENT TRIAL AND APPEAL BOARD

____________________________________________
UNIFIED PATENTS INC.

Petitioner
v.
ADVANCED SILICON TECHNOLOGIES, LLC
Patent Owner
IPR2016-01026
Patent 6,546,439
PETITION FOR INTER PARTES REVIEW OF
US PATENT NO. 6,546,439
CHALLENGING CLAIMS 1, 4, 7, 10, 11, 14, 15, 17, 20, 23, 26, 27, 30, AND
31
UNDER 35 U.S.C. 312 AND 37 C.F.R. 42.104
Patent 6,546,439
TABLE OF CONTENTS
Page
I.
MANDATORY NOTICES ............................................................................. 1

A.
B.
C.
D.
Real Party-in-Interest ............................................................................ 1

Related Matters...................................................................................... 1
Counsel .................................................................................................. 2
Service Information, Email, Hand Delivery and Postal ........................ 2
II.
CERTIFICATION OF GROUNDS FOR STANDING .................................. 2
III.
OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 2

A.
Prior Art Patents and Printed Publications ............................................ 3

1.
2.
3.
4.
B.
US Patent 5,784,582 (filed on October 28, 1996,

published on July 21, 1998) (Hughes (EX1002)),
which is prior art under 35 U.S.C. 102(a)................................ 3
US Patent 5,745,913 (filed on August 5, 1996,
published on April 28, 1998) (Pattin (EX1003)),
which is prior art under 35 U.S.C. 102(a)................................ 3
US Patent 5,155,854 (filed on February 3, 1989,
published on October 13, 1992) (Flynn (EX1004)),
which is prior art under 35 U.S.C. 102(b) ............................... 3
European Patent Application 0 380 844 (published on
August 8, 1990) (Gagliardo (EX1005)), which is
prior art under 35 U.S.C. 102(b) .............................................. 3
Grounds for Challenge .......................................................................... 3
IV.
TECHNOLOGY BACKGROUND................................................................. 4
V.
OVERVIEW OF THE 439 PATENT ............................................................ 5

A.
B.
C.
VI.
Summary of the Alleged Invention ....................................................... 5

Level of Ordinary Skill in the Art ......................................................... 7
Prosecution History ............................................................................... 8
CLAIM CONSTRUCTION ............................................................................ 9

A.
B.
source indication .............................................................................. 10

tag ..................................................................................................... 11
i
Patent 6,546,439
VII. SPECIFIC GROUNDS FOR PETITION ...................................................... 11
A.
Ground I: Claims 1, 4, 7, 10, 11, 14, 15, 17, 20, 23, 26, 27,
30, and 31 are rendered obvious by Hughes in view of Pattin ........... 12
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
B.
Overview of Hughes ................................................................. 12

Overview of Pattin .................................................................... 17
Motivation to Combine Hughes and Pattin .............................. 19
Claim 1 is obvious in view of Hughes and Pattin .................... 20
Claim 10 is obvious in view of Hughes and Pattin .................. 29
Ground II: Claims 1, 4, 10, 11, 15, 17, 20, 26, 27, and 31
are rendered obvious by Flynn in view of Gagliardo ......................... 35
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Overview of Flynn .................................................................... 35

Overview of Gagliardo ............................................................. 42
Motivation to combine Flynn and Gagliardo ........................... 48
Claim 1 is obvious in view of Flynn and Gagliardo ................ 49
Claim 4 is obvious in view of Flynn and Gagliardo ................ 55
Claim 10 is obvious in view of Flynn and Gagliardo .............. 57
VIII. CONCLUSION.............................................................................................. 62
ii
Patent 6,546,439
I.
MANDATORY NOTICES
A.
Real Party-in-Interest
Pursuant to 37 C.F.R. 42.8(b)(1), Unified Patents Inc. (Unified or

Petitioner) certifies that Unified is the real party-in-interest, and further certifies
that no other party exercised control or could exercise control over Unifieds
participation in this proceeding, the filing of this petition, or the conduct of any
ensuing trial. In this regard, Unified has submitted voluntary discovery. See
EX1013 (Petitioners Voluntary Interrogatory Responses).
B.
Related Matters
US Pat. No. 6,546,439 (439 patent (EX1001)) is owned by Advanced

Silicon Technologies, LLC (AST or Patent Owner). On December 21, 2015,
AST filed lawsuits in the US District Court for the District of Delaware against
multiple companies, claiming that these companies products and/or services
infringe the 439 patent. AST also filed a Section 337 Action in the International
Trade Commission on December 27, 2015 against multiple companies, seeking to
exclude from importation components and products incorporating computing and
graphics systems that allegedly infringe the 439 patent.
Patent 6,546,439
C.
Counsel
David L. Cavanaugh (Reg. No. 36,476) will act as lead counsel; Jonathan
Stroud (Reg. No. 72,518) and Daniel Williams (Reg. No. 45,221) will act as backup counsel.
D.
Service Information, Email, Hand Delivery and Postal
Unified consents to electronic service at david.cavanaugh@wilmerhale.com

and jonathan@unifiedpatents.com. Petitioner can be reached at Wilmer Cutler
Pickering Hale and Dorr, LLP, 1875 Pennsylvania Ave., NW, Washington, DC
20006, Tel: (202) 663-6000, Fax: (202) 663-6363, and Unified Patents Inc., 1875
Connecticut Ave. NW, Floor 10, Washington, DC 20009, (650) 999-0899.
II.
CERTIFICATION OF GROUNDS FOR STANDING

Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
review is sought is available for inter partes review and that Petitioner is not
barred or estopped from requesting an inter partes review challenging the patent
claims on the grounds identified in this Petition.
III.
OVERVIEW OF CHALLENGE AND RELIEF REQUESTED

Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)(2), Petitioner challenges
claims 1, 4, 7, 10, 11, 14, 15, 17, 20, 23, 26, 27, 30, and 31 of the 439 patent.
Patent 6,546,439
A.
Prior Art Patents and Printed Publications
The following references are pertinent to the grounds of unpatentability

explained below:1
1.
US Patent 5,784,582 (filed on October 28, 1996, published on

July 21, 1998) (Hughes (EX1002)), which is prior art under
35 U.S.C. 102(a)
2.
US Patent 5,745,913 (filed on August 5, 1996, published on

April 28, 1998) (Pattin (EX1003)), which is prior art under
35 U.S.C. 102(a)
3.
US Patent 5,155,854 (filed on February 3, 1989, published on

October 13, 1992) (Flynn (EX1004)), which is prior art under
35 U.S.C. 102(b)
4.
European Patent Application 0 380 844 (published on August 8,

1990) (Gagliardo (EX1005)), which is prior art under 35
U.S.C. 102(b)
B.
Grounds for Challenge
This Petition, supported by the declaration of Professor Sudhakar

Yalamanchili (Yalamanchili Declaration or Yalamanchili (EX1006)), requests
cancellation of challenged claims 1, 4, 7, 10, 11, 14, 15, 17, 20, 23, 26, 27, 30, and
31 as unpatentable under 35 U.S.C. 103. See 35 U.S.C. 314(a).
1
The 439 patent issued from a patent application filed prior to enactment of the
America Invents Act (AIA). Accordingly, pre-AIA statutory framework applies.
Patent 6,546,439
IV.
TECHNOLOGY BACKGROUND
At the time of filing the 439 patent, it was well known that the speed of
accessing memory was a major limiting factor on overall system speed.

(Yalamanchili 11 (EX1006)). Memory bottlenecks often existed because the
ability to fulfill memory access requests was slower than the speed at which
components of the system could generate and convey the requests. (Yalamanchili
11 (EX1006)).
Access to memory is commonly controlled by components called memory
controllers. (Yalamanchili 12 (EX1006)). Memory controllers may act as an
interface between components of the system and the memory. (Yalamanchili 12
(EX1006)).
The memory controller receives memory access requests from
components of the system, such as the central processing unit (CPU), graphics
accelerator, input/output units, etc. (Yalamanchili 12 (EX1006)). These requests
may be to read data stored in memory or to write data to memory. (Yalamanchili
12 (EX1006)).
Well before the application for the 439 patent was filed, it was well known
to arbitrate the order in which multiple requests would be granted access to
memory by using a memory controller. (Yalamanchili 13 (EX1006)). For
example, US Pat. 6,272,600, filed in February 1997, disclosed to reorder memory
requests based on currently available portions of memory. (Yalamanchili 13
Patent 6,546,439
(EX1006)).
Further, US Pat. 6,032,232, filed in May 29, 1997, disclosed a
memory arbitration system where high priority components were given first access
to memory. (Yalamanchili 13 (EX1006)). Even earlier, US Pat. 5,301,279,
published in 1994, disclosed an arbitration scheme that reprioritizes requests from
devices based on accesses to system memory. (Yalamanchili 13 (EX1006)).
Prioritizing memory requests based on assigning priority levels to requesting
devices necessarily requires that the source of the request, such as the particular
component making the request or its associated device is known. (Yalamanchili
13 (EX1006)).
V.
OVERVIEW OF THE 439 PATENT

A.
Summary of the Alleged Invention
Independent claims 1 and 17 were allowed based on the incorrect premise

that it was not known to consider source indication when making memory access
requests. (Yalamanchili 14 (EX1006)). The 439 patent acknowledges that it
was known to access memory from multiple different sources. (439 patent at 2:1
28 (EX1001); (Yalamanchili 14 (EX1006)).
The sources may include, for
example, CPU 114, AGP graphics controller 100, PCI I/O devices 150-154, and
their associated buses. (439 patent at 5:65-6:15 (EX1001)); (Yalamanchili 14
(EX1006)).
Patent 6,546,439
The 439 patent uses Figure 5 to describe how source information is created
by using queues 500, 502 and 504. (Yalamanchili 15 (EX1006)). Figure 5 is
reproduced below to show the queues. The 439 patent explains that memory
access requests that originate on CPU bus 115 are deposited in CPU bus queue
500, memory access requests originating on AGP interconnect 102 are deposited in
AGP interconnect queue 502, and memory access requests originating on PCI bus
118 are deposited in PCI bus queue 504. (439 patent at 9:6310:1 (EX1001));
(Yalamanchili 15 (EX1006)).
(439 patent at Figure 5 (EX1001) (annotations added). The memory controller

200 is able to determine the source of the memory access request by virtue of the
Patent 6,546,439
queue in which the memory access is stored.
(Id. at 10:113 (EX1001));
(Yalamanchili 15 (EX1006)). For example, if a memory access request is stored

in the PCI bus queue 504, the memory controller 200 knows that a source
associated with the 504 queue, such as an I/O device, made the memory access
request. (Yalamanchili 15 (EX1006). This information can be used to determine
an order in which the memory requests will be serviced. (439 patent at 10:46
(EX1001)); (Yalamanchili 15 (EX1006)). However, as discussed below in more
detail, using source information when managing memory access requests, was
well-known in the art before the filing date of the 439 patent. (Yalamanchili 15
(EX1006)).
Figure 6 of the 439 patent describes another embodiment where tags 302
are included in the queues.
The tags 302 are used to associate additional
information with the memory requests. This additional information may provide
an urgency or priority of a request, whether transactions need to be answered in a
particular order, and whether the memory access is speculative. (439 patent at
9:3944, 10:2733 (EX1001)); (Yalamanchili 16 (EX1006)).
B.
Level of Ordinary Skill in the Art
A person of ordinary skill in the art for the 439 patent would have been an
electrical engineer or computer engineer having the equivalent of a post-graduate
education, such as a masters degree or equivalent knowledge obtained through
Patent 6,546,439
work experience, and several years of experience in the design or performance
evaluation of memory systems. (Yalamanchili 19 (EX1006)).
C.
Prosecution History
The 439 patent issued from US Pat. Appl. No. 09/207,970, which was filed
on December 9, 1998 (File History, Application (12/09/98) (EX1007)).
Four
Office Actions on the merits were issued during prosecution of the 439 patent.
The first three Office Actions included a single reference rejection of claim 1.
After the third Office Action, Patent Owner canceled pending claims 132 and
added new claims 3364. (File History, Amendment at 2-6 (4/22/02) (EX1008)).
New independent claims 33 and 49 issued as independent claims 1 and 17,
respectively. In the fourth Office Action, the Examiner rejected claims 33 and 49
based on another single reference rejection by asserting that the claimed source
indication is inherently found in the prior art. (File History, Office Action at 3
(5/21/02) (EX1009)).
The Patent Owner argued that application claims 33 and 49 were not
anticipated because the prior art did not explicitly disclose the claimed source
indication and because the Examiner had not established a proper theory of
inherency. (File History, Request for Consideration at 2 (8/23/02) (a requested
memory operation buffer configured to provide a source indication for each
memory request is not inherent in the cited art.) (EX1010)); (Yalamanchili 18
Patent 6,546,439
(EX1006)). The Examiner then allowed all claims. (File History of 439 patent,
NOA (9/25/02) (Ex. 1011). However, as described in detail below, the source
indication limitation was well known before the 439 patent was filed and was
explicitly, not inherently, disclosed in many references.
(Yalamanchili 18
(EX1006)).
VI.
CLAIM CONSTRUCTION
Claim terms of an unexpired patent in inter partes review are given the
broadest reasonable construction in light of the specification.
37 C.F.R.
42.100(b); In re Cuozzo Speed Techs., LLC 778 F.3d 1271, 127981 (Fed. Cir.
2015). Any claim term that lacks a definition in the specification is therefore given
a broad interpretation.2 In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379
(Fed. Cir. 2007). Under the broadest reasonable interpretation standard, claim
terms are given their ordinary and customary meaning, as they would be
understood by one of ordinary skill in the art, in the context of the disclosure. In re
Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
Any special
definition for a claim term must be set forth in the specification with reasonable
2
Petitioner applies the broadest reasonable construction standard as required by
the governing regulations. 37 C.F.R. 42.100(b). Petitioner reserves the right to

pursue different constructions in a district court, where a different standard is
applicable.
Patent 6,546,439
clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed.
Cir. 1994).
The following proposes constructions and offers support for those
constructions.
Any claim terms not included should be given their broadest
reasonable interpretation in light of the specification, as commonly understood by

those of ordinary skill in the art. Should the Patent Owner, to avoid the prior art,
contend that a claim term has a construction different from its broadest reasonable
interpretation, the appropriate course is for the Patent Owner to seek to amend the
claim to expressly correspond to its contentions in this proceeding. See 77 Fed.
Reg. 48764 (Aug. 14, 2012).
A.
source indication
The term source indication should be interpreted to mean information

that can be used to determine the source of the request. (Yalamanchili 29
(EX1006)). This construction is consistent with the claims and the specification of
the 439 patent. (Yalamanchili 29 (EX1006)). For example, the 439 patent
discloses that due to association with the various buses 102, 115, 118, queues
600-604 convey information about the sources of the queue memory transactions.
(439 patent at 10:2023 (EX1001)); (Yalamanchili 29 (EX1006)). Further,
claim 14, for example, describes that said requested memory operation buffer
comprises a separate memory request queue for each of said plurality of sources
10
Patent 6,546,439
wherein said source indication corresponds to one of said memory request queues.
(439 patent at 13:1320 (EX1001)); (Yalamanchili 29 (EX1006)). Thus, one of
ordinary skill in the art would have understood a source indication to mean
information that can be used to determine the source of the request.
B.
tag
A term tag should be interpreted as a data structure that includes

information associated with a memory access request.
(Yalamanchili 30
(EX1006)). The 439 patent discloses that the requested memory operation buffer
336 may be further structured such that each memory operation within requested
memory operation buffer 336 may also have associated with that memory
operation a tag 302 which may contain one or more units indicative of one or
more parameters related to the transaction in question. (439 patent at 9:2531
(EX1001)); (Yalamanchili 30 (EX1006)). Thus, the proposed construction is
consistent with the specification of the 439 patent and with the ordinary use of the
term tag. (Yalamanchili 30 (EX1006)).
VII. SPECIFIC GROUNDS FOR PETITION
Pursuant to Rule 42.104(b)(4)(5), the following sections (as confirmed in
the Yalamanchili Declaration 31155 (EX1006)) detail the grounds of
11
Patent 6,546,439
unpatentability, the limitations of the challenged claims of the 439 patent, and
how these claims were therefore obvious in view of the prior art.
A.
Ground I: Claims 1, 4, 7, 10, 11, 14, 15, 17, 20, 23, 26, 27, 30, and
31 are rendered obvious by Hughes in view of Pattin
Hughes was not applied in a rejection during prosecution of the 439 patent.
Hughes was cited by the applicant during prosecution. Pattin is not of record in
the 439 patent.
1.
Overview of Hughes
Hughes discloses to use a memory controller to select a next request for

access to a shared memory, for the purpose of improving pipeline fullness.
(Hughes at 2:2430 (EX1002)); (Yalamanchili 31 (EX1006)). This is done by
looking at (1) characteristics of the current request, or requests currently being
executed, and (2) characteristics of pending requests.
(Hughes at 2:2430
(EX1002)); (Yalamanchili 31 (EX1006)). Thus, a next request can be selected

based on a priority which assigns a higher priority to accesses of the same type as
a request currently in the pipeline, which assigns a higher priority to a next request
which is an access to the same line of data in the SDRAM as in the current request
in the pipeline, and which give higher priority to a next request to a second bank in
the SDRAM. (Hughes at 2:4356 (EX1002)); (Yalamanchili 31 (EX1006)).
Figure 2 of Hughes, reproduced below with annotations, shows a system
including:
a shared memory, controller/arbiter that comprises a memory

12
Patent 6,546,439
controller, a buffer, and a plurality of sources that make memory requests.
(Hughes at 4:4448; 5:3542 (EX1002)); (Yalamanchili 32 (EX1006)). The
shared memory is also accessed by a refresh path source, not shown in Figure 2a.
Figure 3 of Hughes, also reproduced below with annotations, shows the

buffer and memory controller of Figure 2 and the sources that make memory
requests. (Hughes at 5:636:5 (EX1002)). In particular, the sources include an
internal bus and its path 101, a corebus and its path 102, and a processor and its
path 103. (Hughes at 5:3640 (EX1002)); (Yalamanchili 33 (EX1006)).
Requests from these sources include a starting address, a size and a direction
13
Patent 6,546,439
indicating whether the access is for read or write. (Hughes at 5:4042 (EX1002));
(Yalamanchili 33 (EX1006)). Hughes discloses that [e]ach request is stored in a
buffer represented by blocks 104 through 107 in the figure. (Hughes at 5:4345
(EX1002)).
14
Patent 6,546,439
The blocks 104107 of the buffer are coupled to a request selection
processor 108. (Id. at 5:4546 (EX1002)). When determining a next request to
process, Hughes makes clear that the source of the request is considered:
The request selection processor 108 is able to select a
request synchronously from each of the buffers 104
through 107 in order to manage the shared memory
pipeline according to the present invention. Thus, the
source of the data, the beginning address of the data, the
size of the access and the direction of the access are all
utilized in combination with information about current
requests pending in the shared memory pipeline, in order
to select a next optimum request according to the
parameters of the particular implementation.
(Id. at 5:636:5 (emphasis added); see also 7:5759 (By determining the
source of the request and determining, based on particular criteria, the order of the
access requests, controller 72 arbitrates access to the SDRAM.) (EX1002));
Figure 4 of Hughes is a flowchart which illustrates the request selection
process. (Hughes at 6:5859 (EX1002)); (Yalamanchili 35 (EX1006)).
15
Patent 6,546,439
The process begins when the controller receives multiple requests (block
150). (Hughes at 6:6061 (EX1002)). The controller then determines the priority
of the source of the plural requests in block 151. (Id. at 6:6163 (EX1002)).
Thus, the controller must be able to determine which source is making the request.
If multiple requests have the highest priority, then a process is executed to select
the optimum request. (Id. at 6:6365 (EX1002)); (Yalamanchili 36 (EX1006)).
If only one request has the highest priority, then the high priority request is
16
Patent 6,546,439
selected at block 152, the selected request is processed, and the algorithm returns
(block 153). (Id. at 6:6567 (EX1002)); (Yalamanchili 36 (EX1006)).
2.
Overview of Pattin
Pattin is directed to a system that includes multiple sources that access a

shared memory. Similar to Hughes and the 439 patent, Pattin discloses a memory
controller that re-orders requests from the different sources to handle the requests
in an efficient manner.
(Pattin at 1:5154 (EX1003)); (Yalamanchili 37
(EX1006)).
Figure 6 of Pattin is reproduced below with annotations to show (a) the
sources that make the memory requests, (b) a request queue 26, (c) a request
optimizer 22, and (d) a request processor 24. (Pattin at 6:5556, 7:5558, 8:1419
(EX1003)); (Yalamanchili 38 (EX1006)).
17
Patent 6,546,439
The request prioritizer 22 examines pending requests in the request queue 26
to determine which request should be processed next by request processor 24.
(Pattin at 8:1416 (EX1003)). Requests may be processed in an order different
than the requests are received, to maximize memory performance. (Id. at 8:1619
Figure 5 of Pattin is reproduced below to show a diagram of the fields for a
memory request in the request queue. (Pattin at 7:2628 (EX1003)). The fields
include, e.g., memory commands and, importantly, a source identifier field 36,
shown by annotation. (Id. at 7:2637 (EX1003)); (Yalamanchili 40 (EX1006)).
In particular, Pattin discloses that an identifier for the source of the request is
stored in source field 36. (Pattin at 7:2637 (EX1003)). The request prioritizer 22
uses the fields, including the source identifier field 36, to reorder the memory
requests.
(Pattin at 7:2628, 8:1416, 11:6412:5, 12:2730 (EX1003));
18
Patent 6,546,439
3.
Motivation to Combine Hughes and Pattin
Hughes and Pattin are each directed to systems that allow multiple sources
to access a shared memory and are in the same field of endeavor. (Yalamanchili
41 (EX1006)). The shared memory in both references is a form of DRAM.
Hughes and Pattin each disclose to increase pipeline efficiency by determining an
appropriate order to process memory requests. (Yalamanchili 41 (EX1006)).
Hughes and Pattin each disclose to consider attributes of the memory requests
when determining the order. (Yalamanchili 41 (EX1006)). Both references also
consider the source of the request attribute when determining the order.
Further, both Pattin and Hughes store their
attributes in a buffer, so that this information can be used by a memory controller

when determining the order. (Yalamanchili 41 (EX1006)).
Given the similarities in structure, objectives, and operation between Hughes
and Pattin, one would have been motivated to include the source identifier field, as
19
Patent 6,546,439
used in the buffer of Pattin, with the existing fields used in the buffer of Hughes.
This would provide an efficient way for the
memory controller of Hughes to identify the source.
(Yalamanchili 42
(EX1006)). While it may be argued that Hughes already has this feature because
of Hughess explicit need to identify the source of the memory requests, the
additional teachings in Pattin clarify how the source identification can be obtained.
(Yalamanchili 42 (EX1006)). Adding the source identification field to Hughes is
well within the abilities of one of ordinary skill in the art and would be
accomplished with a reasonable chance of success. (Yalamanchili 42 (EX1006)).
Doing so would require only minor hardware and/or software modifications to the
buffer and memory controller of Hughes. (Yalamanchili 42 (EX1006)).
4.
Claim 1 is obvious in view of Hughes and Pattin
a)
Preamble: A system comprising:
Hughes discloses a data processing system having shared memory. (Hughes

at 1:1113, Figure 2 (EX1002)). Pattin discloses [w]hat is desired is a DRAM
controller which is optimized for a multi-processor system. (Pattin at 1:5152,
Figure 1 (EX1003)). Thus, both Hughes and Pattin disclose a system as recited
in claim 1. (Yalamanchili 44 (EX1006)).
b)
a requested memory operation buffer configured to
receive memory requests from a plurality of sources
20
Patent 6,546,439
Hughes discloses a requested memory operation buffer. (Yalamanchili
46 (EX1006)). Specifically, Hughes discloses that each memory request is
stored in a buffer represented by blocks 104 through 107 in [Figure 3]. (Hughes
at 5:4345 (EX1002)); (Yalamanchili 46 (EX1006)). As Hughes indicates, there
are multiple sources that access the shared memory.
(Yalamanchili 46
(EX1006)). The sources include an internal bus and its path 101, a corebus and its
path 102, and a processor and its path 103. (Hughes at 5:3640 (EX1002));
(Yalamanchili 46 (EX1006)). As shown in Figure 3, the buffer receives memory
requests from the sources. (Yalamanchili 46 (EX1006)). Thus, Hughes teaches
limitation (b) of claim 1. (Yalamanchili 46 (EX1006)).
c)
wherein said requested memory operation buffer is
further configured to provide, for each memory request, a

source indication of the one of said plurality of sources from
which the memory request was received; and
The
combination of
Hughes
and
Pattin
teaches
this
limitation.
(Yalamanchili 48 (EX1006)). Hughes discloses that the buffer 104107 receives

memory requests from the sources. (Hughes at 5:4048 (EX1002) ([r]equests
from each of the paths, include a starting address, a size and a direction indicating
whether the access is for read or write.)); (Yalamanchili 48 (EX1006)). The
different portions 104107 of the buffer, shown in Figure 3, confirm that each
source making a memory request has a corresponding buffer portion or queue.
21
Patent 6,546,439
The buffer portions 104107 themselves
correspond to respective sources of the placed memory requests. (Yalamanchili

48 (EX1006)). Thus, Hughes teaches to make an association between the source
of the request and the buffer portion 104-107 that contains the request.
(Yalamanchili 48 (EX1006)). The 439 specification confirms this understanding
of source indication. (Yalamanchili 48 (EX1006)). The 439 specification
describes that due to the association between various buses and queues, the
queues convey information about the sources of the queued memory
transactions. (439 patent at 10:2023, 10:713 (EX1001)); (Yalamanchili 48
(EX1006)).
Figure 5 of Pattin shows a diagram of the fields for a memory request in
the request queue.
(Pattin at 2:5253 (EX1003)).
The fields include, e.g.,
memory commands and, importantly, a source identifier field 36, shown by

annotation.
(Id. at 7:2637 (EX1003)); (Yalamanchili 49 (EX1006)).
In
particular, Pattin discloses that an identifier for the source of the request is stored
in source field 36. (Pattin (EX1003)). Pattin further discloses the ability to
distinguish between multiple sources of the same type. (Id. at 11:5658, 11:66
67). The request prioritizer 22 uses the fields, including the source identifier field
36, to reorder the memory requests.
(Id. at 7:2628, 8:1416, 11:6412:5
(EX1003)); (Yalamanchili 49 (EX1006)). The request prioritizer 22 in Pattin is

22
Patent 6,546,439
similar to the request selection processor 108 of Hughes. (Yalamanchili 49
(EX1006)).
Turning back to Hughes, this reference further discloses that the priority, or
order of arbitration, is programmable to allow the most critical requester [i.e.,
source] to be service[d] before the lower priority requesters. (Hughes at 14:4143
(EX1002)). Hughes teaches that this priority order may be static or dynamic. (Id.
at 14:4346 (EX1002)); (Yalamanchili 50 (EX1006)).
It would have been obvious for the buffer portions 104107 of Hughes to
include a source field 36, as disclosed by Pattin. (Yalamanchili 51 (EX1006)).
The motivation for doing so is described above. Further, a person of ordinary skill
in the art would appreciate that this would allow for desired flexibility in providing
the dynamic assignment of priorities disclosed by Hughes. (Yalamanchili 51
(EX1006)).
In particular, if the systems needs changed, requiring different
priorities to be assigned to different sources, it would not matter which path 100
103 was used by the different sources. (Yalamanchili 51 (EX1006)). Instead, a
memory controller would merely need to know which source is granted the highest
priority and then look to the source identification that is explicitly provided by the
buffer. (Yalamanchili 51 (EX1006)). Further, Pattin also acknowledges the use
of dynamic priorities.
23
(Pattin at 11:5660
Patent 6,546,439
(EX1003)). Thus, the combination of Hughes and Pattin teaches limitation (c) of
claim 1. (Yalamanchili 51 (EX1006)).
d)
a memory controller configured to receive said
memory requests and said source indication from said

requested memory operation buffer,
Hughes discloses a memory controller, as described above in annotated
Figure 3, comprising at least elements 108111. (Yalamanchili 53 (EX1006)).
Similar to the claimed memory controller, Hughes teaches that its request
selection processor 108 acts as an arbiter for receiving memory requests and source
indications. (Hughes at 5:636:5 (EX1002)); (Yalamanchili 53 (EX1006)).
Specifically, Hughes teaches that the request selection processor 108 is able to
select a request synchronously from each of the buffers 104 through 107 in order to
manage the shared memory pipeline according to the present invention. (Hughes
at 5:6366 (EX1002)).
When Hughes buffer is modified to include [a]n identifier for the source of
the request [that] is stored in source field 36, as disclosed by Pattin, the request
selection processor 108 of Hughes teaches limitation (d) of claim 1.
(Yalamanchili 54 (EX1006)). The motivation to modify Hughes based on Pattin
is further underscored by Hughess need to identify the source of the memory
request:
24
Patent 6,546,439
The request selection processor 108 is able to select a
request synchronously from each of the buffers 104
through 107 in order to manage the shared memory
pipeline according to the present invention. Thus, the
source of the data, the beginning address of the data, the
size of the access and the direction of the access are all
utilized in combination with information about current
requests pending in the shared memory pipeline, in order
to select a next optimum request according to the
parameters of the particular implementation.
(Hughes at 5:636:5, see also 7:5759 (By determining the source of the
request and determining, based on particular criteria, the order of the access
requests, controller 72 arbitrates access to the SDRAM. (EX1002));
Hughes therefore teaches that (1) the memory request and (2) the source of
the data are used by the request selection processor 108. (Yalamanchili 55
(EX1006)). As noted above, it would have been obvious for the source of the
request to be stored in the buffer of Hughes, as taught by Pattin. (Yalamanchili
55 (EX1006)).
This modification would make clear that Hughess memory
controller is configured to receive the memory requests and the source indication
from its buffer. (Yalamanchili 55 (EX1006)). Thus, the combination of Hughes
and Pattin teaches limitation (d) of claim 1. (Yalamanchili 55 (EX1006)).
25
Patent 6,546,439
e)
wherein said memory controller is configured to
schedule accesses to a memory in response to said memory

requests.
The combination of Hughes and Pattin teaches this feature. (Yalamanchili
57 (EX1006)). For example, Figure 4 of Hughes discloses to schedule accesses
to memory in response to memory requests. (Yalamanchili 57 (EX1006)). The
process of Figure 4 begins when the controller receives multiple requests (block
150). (Hughes at 6:6061 (EX1002)). The controller then determines the priority
of the source of the plural requests in block 151. (Id. at 6:6163 (EX1002)).
Thus, the controller must be able to determine which source is making the request,
and when modified based on Pattin, the controller is explicitly provided with the
source of the request. (Yalamanchili 57 (EX1006)). If multiple requests have
the highest priority, then a process is executed to select the optimum request.
(Hughes at 6:6365 (EX1002)); (Yalamanchili 57 (EX1006)).
If only one
request has the highest priority, then the high priority request is selected at block
152, the selected request is processed, and the algorithm returns (block 153).
(Hughes at 6:6567 (EX1002)). Thus, the combination of Hughes and Pattin
teaches limitation (e) of claim 1. (Yalamanchili 57 (EX1006)).
26
Patent 6,546,439
5.
a)
The system as recited in claim 1, wherein said
requested memory operation buffer is further configured to

provide one or more parameters for each said memory request
in addition to said source indication to said memory controller
for use in scheduling the memory requests.
Hughes teaches that parameters are stored in the buffer components 104
107. (Hughes at Figure 3 (EX1002)); (Yalamanchili 59 (EX1006)). Hughes
further discloses that the memory controller includes logic responsive to
configuration parameters to control the priority of data paths sharing the memory.
(Id. at 2:31-34 (EX1002)). Hughes teaches that information sent in the paths from
the sources, such as command attributes indicative of read and write
operations, are parameters. (Id. at 5:4243 (EX1002)). Thus, Hughes teaches
this limitation. (Yalamanchili 59 (EX1006)).
Similarly, Pattin teaches fields that are stored with each memory request in
the request queue. For example, Pattin describes that Figure 5 is a diagram of the
fields for a memory request in the request queue. (Pattin at 7:2637 (EX1003));
Thus, Pattin also teaches this limitation.
6.
a)
The system as recited in claim 4, wherein the one or
more parameters for each memory request comprise an

27
Patent 6,546,439
indication of whether or not the memory request is
speculative.
For example, Pattin discloses that a speculative/demand bit is added to
each entry in request queue 26 to indicate if the request is speculative, before cache
look-up, or demand, after cache look-up. (Pattin at 10:4952 (EX1003)). Pattin
therefore teaches parameters that comprise an indication of whether or not the
memory request is speculative.
Pattin also
discloses that [a]ll speculative requests have a lower priority than other demand
requests. (Pattin at 10:25, 10:5911:2, 11:49 (EX1003)).
Hughes discloses that the priority, or order of arbitration, is programmable
to allow the most critical requester [i.e., source] to be service[d] before the lower
priority requesters. (Hughes at 14:4143 (EX1002)). It would have been obvious
to modify one of the data fields in Hughes to provide an indication of whether or
not the memory request is speculative for the same reason taught by Pattin, which
is, for example, to consider whether a request is speculative when making a
priority determination. (Yalamanchili 63 (EX1006)). Thus, the combination of
Hughes and Pattin teaches the limitations of claim 7.
(EX1006)).
28
(Yalamanchili 63
Patent 6,546,439
7.
a)
more parameters for each memory request are stored within a

tag associated with each memory request.
Hughes describes storing parameters in fields for each memory request. The
parameters are stored in the buffer components 104107. (Hughes at 5:4043,
Figure 3 (EX1002))); (Yalamanchili 65 (EX1006). A person of ordinary skill in
the art would have understood that the fields stored for each memory request, as
described by Hughes, teach or suggest the recited tag. (Yalamanchili 65
(EX1006)).
8.
a)
The system as recited in claim 1, wherein said plurality
of sources comprises a central processing unit interface.

The combination of Hughes and Pattin teaches or suggests claim 11. For
example, Hughes and Pattin each teaches or suggests the recited central processing
unit (CPU) interface. (Yalamanchili 67 (EX1006)).
Hughes teaches receiving requests from a plurality of units including a
central processing node. (Hughes at 2:6264 (EX1002)). One of ordinary skill
in the art would understand that a central processing node comprises a central
processing unit. (Yalamanchili 68 (EX1006)). Figure 3 of Hughes shows the
central processing node communicating with the buffer 107 through an interface
29
Patent 6,546,439
call an internal processor complex path 103. (Hughes at 5:3940 (EX1002)));
(Yalamanchili 68 (EX1006). Hughes further describes that a processor complex
interface 53 is used. (Id. at 4:4748 (EX1002)). It would have been obvious to a
person of ordinary skill in the art that the internal processor complex path 103 and
the processor complex interface 53 respectively teach CPU interfaces for the
central processing node. (Yalamanchili 68 (EX1006)).
Pattin teaches receiving requests from CPU cores. (Pattin at 7:5558
(EX1003)). The CPUs send memory requests using a [b]us 54. (Id. at 6:6466
(EX1003)). One of ordinary skill in the art would understand that the bus 54
provides the claimed CPU interface.
Thus,
Hughes and Pattin each teaches or suggests this limitation. (Yalamanchili 69

(EX1006)).
9.
a)
requested memory operation buffer comprises a separate

memory request queue for each of said plurality of sources,
Hughes teaches that its buffer comprises multiple portions 104107.
(Hughes at 5:4346, Figure 3 (EX1002))); (Yalamanchili 71 (EX1006). One of
ordinary skill in the art would find obvious that the respective portions 104107
provide separate memory request queues.
Hughes teaches to provide these queues for the plurality of sources, including the
30
Patent 6,546,439
coresbus, the internal bus and the processor.
(Hughes at 5:4344, 14:3437,
Figure 3 (EX1002)); (Yalamanchili 71 (EX1006)).
Thus, Hughes teaches
limitation (a) of claim 14. (Yalamanchili 71 (EX1006)).
b)
further comprised to provide each memory request to said

memory controller from one of said memory request queues,
wherein said source indication corresponds to one of said
memory request queues.
Hughes teaches to provide each memory request to the memory controller,
shown above in annotated Figure 3, from the respective memory request queues.
(Yalamanchili 73 (EX1006)). For example, these memory requests are provided
through the connections shown in Figure 3 between (1) the queues 104107 and
(3) the request selection processor 108 that forms part of the memory controller.
(Hughes at 5:4546, Figure 3 (EX1002)); (Yalamanchili 73 (EX1006).
One of ordinary skill in the art would have found it obvious to modify
Hughes in view of Pattin, as discussed above, such that the queues 104107 send
an indication of the source, in addition to the other parameters disclosed as being in
the queues 104107. (Yalamanchili 74 (EX1006)). These source indications, for
example, would therefore respectively correspond to the queues 104107.
(Yalamanchili 74 (EX1006)). The combination of Hughes and Pattin therefore
teaches limitation (b) of claim 14. (Yalamanchili 74 (EX1006)).
31
Patent 6,546,439
10.
a)
The system as recited in claim 1, wherein said source
indication comprises an identity of a request initiator for the

memory request.
Pattin teaches or suggests the claimed identity of a request initiator. Pattin
discloses a source field that identifies the source of each memory request. (Pattin
at 7:3637 (EX1003))); (Yalamanchili 76 (EX1006). As described with respect
to claim 1, it would have been obvious to modify Hughes to include the source
field of Pattin. (Yalamanchili 76 (EX1006)). A person of ordinary skill in the
art would have understood that this source field teaches an identity of a request
initiator for the memory request. (Yalamanchili 76 (EX1006)). Thus, the
combination of Hughes and Pattin teaches or suggests this limitation.
11.
a)
A method, comprising: receiving memory requests
from a plurality of sources;

As noted above in Section VII.A.4, the combination of Hughes and Pattin
teaches A method, comprising: receiving memory requests from a plurality of
sources.
32
Patent 6,546,439
b)
associating a source indication for each memory
request of the one of said plurality of sources from which the

memory request was received; and
teaches associating a source indication for each memory request of the one of said
plurality of sources from which the memory request was received.
c)
scheduling execution of said memory requests based
on said source indication.

teaches scheduling execution of said memory requests based on said source
indication.
12.
a)
The method as recited in claim 17, further comprising
associating one or more parameters with each said memory

request in addition to said source indication for use in said
scheduling.
teaches associating one or more parameters with each said memory request in
addition to said source indication for use in said scheduling.
13.
a)
The method as recited in claim 20, wherein the one or
more parameters for each memory request comprise an
33
Patent 6,546,439
indication of whether or not the memory request is
speculative.
teaches wherein the one or more parameters for each memory request comprise an
indication of whether or not the memory request is speculative.
14.
a)

teaches wherein the one or more parameters for each memory request are stored
within a tag associated with each memory request.
15.
a)
The method as recited in claim 17, wherein said
plurality of sources comprises a central processing unit

interface.
teaches wherein said plurality of sources comprises a central processing unit
interface.
16.
a)
associating a source indication for each memory request
34
Patent 6,546,439
comprises placing each memory requests in a separate
memory request queue for each of said plurality of sources.
teaches wherein said associating a source indication for each memory request
comprises placing each memory requests in a separate memory request queue for
each of said plurality of sources.
17.
a)
source indication comprises an identity of a request initiator

for the memory request.
teaches wherein said source indication comprises an identity of a request initiator
B.
Ground II: Claims 1, 4, 10, 11, 15, 17, 20, 26, 27, and 31 are
rendered obvious by Flynn in view of Gagliardo
Flynn was not applied in a rejection during prosecution of the 439 patent.
Flynn was cited by the applicant during prosecution. Gagliardo is not of record in
the 439 patent.
1.
Overview of Flynn
Flynn is directed to a system that includes multiple sources that make

memory requests. (Yalamanchili 95 (EX1006)). In particular, Flynn discloses
multi-processor computer systems in which a system control unit (SCU) is used for
35
Patent 6,546,439
operating a plurality of central processor units (sources) and input/output units
(additional sources) in a parallel fashion.
(Flynn at 2:3741 (EX1004));
Memory requests are arbitrated based on the
source of the request to provide system efficiency and fairness to the different
sources. (Flynn at 2:4145; 3:414) (EX1004)); (Yalamanchili 95 (EX1006)).
Figure 1 of Flynn is reproduced below with annotations to show the plurality
of sources that make requests to a common memory 16.
(Flynn at 6:1117
(EX1004)); (Yalamanchili 96 (EX1006)). The SCU 14 receives the memory

requests from the CPUs 12 and the input/output (I/O) units 20A. (Flynn at 6:5661
36
Patent 6,546,439
Communications between the SCU 14 and the memory 16 are handled
through a dedicated interface means 30.
(Flynn at 6:3036 (EX1004));
(Yalamanchili 97 (EX1006)). With respect to details about the interface means

30, Flynn refers to and incorporates by reference U.S. patent application Ser. No.
07/306,326 (the 326 application). (Flynn at 6:3648 (EX1004)). Gagliardos
disclosure of the interface means 30 is discussed further below in more detail.
An objective of Flynn is to arbitrate memory requests in order to achieve
the dual requirements of system efficiency and unit fairness. (Id. at 7:510
(EX1004)); (Yalamanchili 98 (EX1006)). Flynn discloses that conventional
arbitration schemes, based, for instance, on the round-robin approach or the
instantaneous execution approach are unsatisfactory for use in multi-processing
systems because they fail to provide efficient utilization of system resources in
combination with a reasonable response period in the arbitration of communication
requests. (Flynn at 7:1623 (EX1004)).
37
Patent 6,546,439
Figure 3 of Flynn, shown here, includes a block diagram illustrating an

arrangement for implementing the arbitration scheme for the system in FIG. 1. (Id.
at 10:6410:68 (EX1004)). The CPUs and I/O units send memory request
indications 112 that are stored within a prioritizer 113.
(Id. at 10:6811:4
(EX1004)); (Yalamanchili 99 (EX1006)). Commands 114 associated with the

incoming requests are stored in a command buffer 115. (Flynn at 10:6811:4
(EX1004)); (Yalamanchili 99 (EX1006)). The commands indicate, for example,
whether a request is for a memory read or write operation. (Flynn at 17:2329
(EX1004)); (Yalamanchili 99 (EX1006)). The memory commands also require
38
Patent 6,546,439
target addresses of the memory being accessed. (Flynn at 17:5566 (EX1004));
In operation, the prioritizer 113 issues a priority index signal 116 that
indicates which source should have its request prioritized. (Flynn at 11:417
(EX1004)); (Yalamanchili 100 (EX1006)). The commands 114 and the priority
index signal 116 are sent to a multiplexer 117. (Flynn at 11:49 (EX1004)). The
multiplexer 117 then selects the command corresponding to the source that should
be given priority. (Id. at 11:49 (EX1004)); (Yalamanchili 100 (EX1006)).
Figure 4 of Flynn is reproduced below with annotations to show the
prioritizer 113 in more detail. The prioritizer includes latches 07. (Flynn at
11:6812:3, Figure 4 (EX1004)).
The command buffer of Figure 3 and its
associated latches 07, shown in Figure 4, work together as a team to provide the
information sent to the multiplexer 117. (Id. at 11:49 (EX1004)); (Yalamanchili
101 (EX1006)). A latch is provided for each CPU and I/O unit that makes a
memory request.
(Flynn at 11:6612:3 (EX1004)); (Yalamanchili 101
(EX1006)). For example, Latch 0 corresponds to the CPU connected to port 0.

(Flynn at 11:5512:3 (EX1004)); (Yalamanchili 101 (EX1006)). The requests
REQ 00REQ 07, from the different sources, are fed to a priority select network
162, also shown in Figure 4, which constitutes a logic arrangement for picking a
particular request on the basis of a predefined hierarchy of prioritizing levels.
39
Patent 6,546,439
(Flynn at 12:4044 (EX1004)); (Yalamanchili 101 (EX1006)).
As one of
ordinary skill in the art would appreciate, the requests would contain at least one
bit of information to constitute the signal. (Yalamanchili 101 (EX1006)).
40
Patent 6,546,439
The prioritizer 113 implements a hierarchical prioritizing scheme for
selection of requests for arbitration.
(Flynn at 5:5557 (EX1004)).
The
hierarchical scheme is based on (1) selecting the request which is most outstanding
in terms of time of arrival at the SCU port when multiple requests arrive at a given
port, and (2) selecting, from such outstanding requests a single request based on a
pre-defined hierarchy of request-originating sources. (Id. at 11:1017 (EX1004));
(Yalamanchili 102 (EX1006))); (Yalamanchili 102 (EX1006). Flynn describes
that the hierarchy for assigning priorities is keyed to the particular system unit
originating a communication request:
[T]he highest priority is preferably awarded to requests
originating from memory, while requests from I/O units
are awarded a relatively lower priority, and finally,
requests originating from CPUs are awarded the lowest
priority.
(Flynn at 11:1724 (emphasis added) (EX1004)).
Flynn therefore discloses to provide an indication of the source by virtue of
sending the REQ XX signal. (Yalamanchili 103 (EX1006)). The memory
requests, including an indication of the source, are then sent to a memory controller
through the interface 30, the details of which are discussed below with reference to
Gagliardo (Flynn at 6:3048 (EX1004)); (Yalamanchili 103 (EX1006)).
41
Patent 6,546,439
2.
Overview of Gagliardo
Gagliardo is intended to be used as the interface means 30 of Flynn, as

discussed further below in section VII(B)(3). (Yalamanchili 104 (EX1006)). A
comparison of Figure 1 in Gagliardo and Figure 1 in Flynn shows the relationship
between these two references.
Figure 1 of Gagliardo
Figure 1 of Flynn
42
Patent 6,546,439
The interface means 30 described in Gagliardo comprises an array control
unit (ACU). (Gagliardo at p. 5, line 57p. 6, line 5; Figures 2 and 3 (EX1005)).
Figure 3 of Gagliardo is reproduced below to show how the ACU 34 interfaces
between the system control unit (SCU) 14 and the main memory unit (MMU) 36.
The MMU 36 functions as the storage section of the main memory 16. (Gagliardo
at p. 6, lines 23) (EX1005)).
The ACU is a memory controller. (Yalamanchili 106 (EX1006)). For

example, Gagliardo describes that all communication between the SCU and the
main memory takes place through the ACU. (Gagliardo at p. 4, lines 2022
43
Gagliardo further discloses that
Patent 6,546,439
control for the memory modules [is] provided by the ACU. (Id. at p. 4, lines 38
40 (EX1005)); (Yalamanchili 106 (EX1006)).
As shown in Figure 3, the ACU has subcomponents, including a main
memory control (MMC) 70, memory control DRAM controller (MCD) 72 and
memory data path (MDP) modules 74 and 76. (Gagliardo at p. 8, lines 58p. 9,
lines 1620 (EX1005)).
The MMC module 70 in combination with the MCD module 72 provides
control for the data path and the memory modules. (Id. at p. 8, line 58p. 9, lines
12 (EX1005)). The MMC 70 and MCD 72 are linked to each other for exchange
of command signals, and are linked to the MMU 36 through control/status lines.
(Id. at p. 9, lines 24 (EX1005)). The MMC 70 is in direct communication with
SCU 14 by virtue of control/status lines. (Id. at p. 9, lines 34 (EX1005)).
The data path section of the ACU 34 is divided between the two MDP's 74
and 76. (Id. at p. 9, lines 1617 (EX1005)). The MDP modules are linked to the
MMC 70 for accepting and acknowledging command signals, and linked to both
the SCU 14 and the MMU 36 through data lines for transfer of data between the
SCU and memory. (Id. at p. 9, lines 1719 (EX1005)).
In operation, if the addressed memory segment is found to be busy, due to a
variety of reasons including a cycle delay in loading and unloading DRAM or due
to the need for the memory to be periodically refreshed on a per segment basis, the
44
Patent 6,546,439
ACU 34 continues monitoring the memory segment and reports back to the SCU
when the address segment becomes available, so that a desired memory operation
can proceed. (Id. at p. 7, lines 47 (EX1005)); (Yalamanchili 110 (EX1006)). In
the meantime, the ACU 34, through suitable buffering, continues the processing,
on a sequential basis, of other memory access commands which are logged with
the SCU and require access to a memory segment which is available at the time.
(Gagliardo at p. 7, lines 810 (EX1005)); (Yalamanchili 110 (EX1006)). Thus,
the ACU 34 schedules access to memory based, e.g., on the availability of the
memory segments corresponding to the received memory requests. (Yalamanchili
110 (EX1006)).
The SCU 14 sends memory commands to the MMC 70, located within the
ACU 34. (Gagliardo at p. 10, lines 1518, p. 11, lines 1415 (EX1005)). This
action is performed using segment command buffers (180 and 181 in FIG. 10)
which are located within each MMC and which correspond to the memory
segments controlled by the MMC. (Id. at p. 10, lines 1820 (EX1005)). These
memory commands correspond to the memory commands received by the SCU
from the devices seeking access to memory, e.g., CPUs and I/O units. (Id. at
p. 10, lines 1518 (EX1005)); (Yalamanchili 111 (EX1006)).
Gagliardo further discloses that an identification of the source making a
memory request is sent to the ACU 34, along with the memory command.
45
Patent 6,546,439
(Gagliardo at p. 7, lines 4344 (EX1005)); (Yalamanchili 112 (EX1006)).
Gagliardo envisions that the ACU 34 may use this identification to facilitate
prioritizing of memory commands and help routing of accessed data appropriately
through the ACU and SCU to the system unit originating the command.
Figure 15 of Gagliardo is reproduced below to show additional aspects
involved in executing memory operations using the ACU. (Gagliardo at p. 5, lines
2324 (EX1005)).
Gagliardo describes the following steps with respect to Figure 15:
46
Patent 6,546,439
The interfacing action is initiated at step 261 by the
transmission of a signal from the ACU to the SCU
indicating that a command buffer is available for
accepting memory commands.
At step 262, a memory command prioritized for
execution by the SCU is transferred to the ACU along
with the corresponding index field.
The received memory command is checked at step
263 to determine whether the command was initiated by
a system CPU or I/O unit so that the appropriate protocol
of restrictions applicable to either a CPU or I/O memory
operation may be followed.
(Id. at p. 20, lines 4048 (emphasis added) (EX1005)).
Gagliardo discloses that if the requesting unit is found to be a CPU, step
264 is initiated and the memory system follows the CPU restriction protocol which
preferably includes the restriction of write transfers to eight quad-words at a time
and the specification of a single mask bit for every long-word of transferred data.
(Id. at p. 20, lines 4548 (EX1005)). Similarly, [i]f the requesting unit is found to
be an I/O unit, step 265 is undertaken wherein the I/O protocol of restrictions is
followed wherein write transfers are preferably permitted for any one of 1, 2, 4, 6,
or 8 quad-words. (Id. at p. 20, lines 4952 (EX1005)). The memory controller of
Gagliardo, the ACU, therefore receives the source indication, e.g., indication of
47
Patent 6,546,439
whether the requesting unit is a CPU or I/O unit, and takes this information into
consideration to schedule access to memory. (Yalamanchili 115 (EX1006)).
3.
Motivation to combine Flynn and Gagliardo
Flynn and Gagliardo are each directed to systems that allow multiple
sources to access a shared memory and are in the same field of endeavor.
(Yalamanchili 116 (EX1006)). Flynn discloses that communications between the
SCU 14 and the memory 16 are handled through a dedicated interface means 30.
(Flynn at 6:3036 (EX1004)). (Yalamanchili 116 (EX1006)). Both Flynn and
Gagliardo were owned by a common assignee at the time that Flynn was filed.
(Flynn at 6:4048 (EX1004)). With respect to details about the interface means
30, Flynn refers to and incorporates by reference U.S. patent application Ser. No.
07/306,326 (the 326 application).
(Id. at 6:3048 (EX1004)); (Yalamanchili
116 (EX1006)).
The 326 application was abandoned before issuing as a patent. However,
Gagliardo claims priority to the 326 application and embodies the 326 application
specification.
(Gagliardo at p. 1 (EX1005)).
The relied upon teachings of
Gagliardo are found in the 326 application. (Yalamanchili 117 (EX1006)). A

copy of the 326 application is included as Exhibit 1012. Thus, instead of referring
to the 326 application, Petitioner makes reference to Gagliardo to remove any
doubt about when the disclosure was first made publicly available. Flynn therefore
48
Patent 6,546,439
provides explicit motivation to use the interface means of the 326 application and
its corresponding EP counterpart to Gagliardo. (Yalamanchili 117 (EX1006)).
Adding Gagliardos interface to Flynn is well within the abilities of one of
ordinary skill in the art and would be accomplished with a reasonable chance of
success. (Yalamanchili 117 (EX1006)).
4.
Claim 1 is obvious in view of Flynn and Gagliardo
a)
Preamble: A system, comprising:
Flynn discloses a multi-processing system 10 which uses a plurality of

central processing units (CPUs) 12 and is adapted to permit simultaneous, i.e.,
parallel, operation of the system CPUs by allowing them to share a common
memory 16 for the system. (Flynn at 6:1317, Figure 1 shows the multiprocessor
system (EX1004)). Gagliardo also discloses a multi-processing computer system
including a plurality of central processing units (CPUs) and input/output (I/O)
units.
(Gagliardo at p. 1, Abstract (EX1005)).
Thus, both Flynn and
Gagliardo disclose a system as recited in claim 1.
(Yalamanchili 119
(EX1006)).
b)
a requested memory operation buffer configured to
receive memory requests from a plurality of sources

Flynn
teaches
the
recited
requested
memory
operation
buffer.
(Yalamanchili 121 (EX1006)). For example, Flynn discloses a series of latches,

shown in Flynns Figure 4 above, that receive memory requests from a plurality of
49
Patent 6,546,439
sources. (Flynn at 11:5965 (EX1004) (The arrangement 160 includes a series of
latches 161 for accepting incoming requests from eight SCU ports comprising four
CPU ports two I/O ports, and two memory ports .)); (Yalamanchili 121
(EX1006)). Flynn also discloses a command buffer 115, shown in Flynns Figure
3 above, which receives corresponding memory request information from a
plurality of sources. (Flynn at 11:14 (EX1004) (commands 114 associated with
incoming requests are accepted and initially stored in a separate command buffer
115)); (Yalamanchili 121 (EX1006)). The command buffer 115 of Figure 3 and
its associated latches 07 shown in Figure 4 work together as a team to provide the
information sent to the multiplexer 117.
(Flynn at 10:6811:4 (EX1004));
As one of ordinary skill in the art would
appreciate, the combination of the command buffer 115 and its associated latches
0-7 act in a cooperative manner to temporarily store the memory requests, so as to
teach the claimed requested memory operation buffer.
(Yalamanchili 121
(EX1006)). Even the 439 patent acknowledges that those skilled in the art will
recognize that such location is somewhat arbitrary, and that such buffers could be
distributed to other components throughout a system so long as the appropriate
functionalities were preserved.
(439 patent at 11:2732 (EX1001));
50
Patent 6,546,439
Flynn discloses that sources of the requests include multiple CPU units and
I/O units. (Flynn at 11:4654 (EX1004) (Preferably the SCU is adapted to have
up to three requests outstanding at every CPU port in the SCU and up to two
requests for each I/O unit and each memory unit port in the SCU . . . Similarly, up
to 20 corresponding incoming commands need to be stored and the command
buffer 115 is accordingly provided with the capacity to accomplish this.)). Thus,
Flynn teaches limitation (b) of claim 1. (Yalamanchili 122 (EX1006)).
c)
further configured to provide, for each memory request, a

source indication of the one of said plurality of sources from
which the memory request was received; and
Flynns latches, which are considered to be part of Flynns overall buffer
configuration, teach this limitation. (Yalamanchili 124 (EX1006)). As described
above with respect to FIG. 4 and limitation (a) of claim 1, Flynn discloses that the
latches provide an indication of the source by virtue of sending the REQ XX
signals. (Yalamanchili 124 (EX1006)). The signals REQ 00REQ 07, which are
shown in Figure 4 as being provided by the latches, represent the different sources.
(Yalamanchili 124 (EX1006)). For example, the signal REQ 00 indicates that the
device at CPU port 0 made a memory request. (Flynn at 11:6812:3 (EX1004));
(Yalamanchili 124 (EX1006)). Similarly, the signal REQ 04 indicates that the
device at I/O port 1 made a memory request. (Flynn at 12:1825 (EX1004));
51
Patent 6,546,439
(Yalamanchili 124 (EX1006)). These signals are provided for each memory
request that is made. (Yalamanchili 124 (EX1006)). The priority selector 162,
shown in Figure 4, knows which device or source sent the memory request based
on the individual signals REQ 00-07 that it receives.
(Flynn at 12:4044
(EX1004)); (Yalamanchili 124 (EX1006)). Thus, Flynn teaches limitation (c) of

d)
a memory controller configured to receive said
memory requests and said source indication from said

requested memory operation buffer,
Gagliardo discloses this limitation. (Yalamanchili 126 (EX1006)). As
noted above, Gagliardo provides the interface means 30 of Flynn. The interface
means includes the ACU 34, which is a memory controller. (Yalamanchili 126
(EX1006)). For example, Gagliardo describes that all communication between
the SCU and the main memory takes place through the ACU. (Gagliardo at p. 4,
lines 2022 (EX1005)). Gagliardo further discloses that control for the memory
modules [is] provided by the ACU. (Id. at p. 4, lines 3840 (EX1005)).
The ACU of Gagliardo is intended to be used with the SCU 14 of Flynn, to
receive the memory requests and the source indication that are provided by the
buffer configuration of Flynn, i.e., the command buffer 115 and the latches 07.
(Yalamanchili 127 (EX1006)). In particular, Gagliardo discloses that the SCU
14 sends memory commands to the MMC 70, located within the ACU 34.
52
Patent 6,546,439
(Gagliardo at p. 10, lines 1518, p. 11, lines 1415, p. 20, lines 4043 (EX1005));
This action is performed using segment
command buffers (180 and 181 in FIG. 10) which are located within each MMC
and which correspond to the memory segments controlled by the MMC.
These memory commands correspond to the memory commands received by the
SCU from the devices seeking access to memory, e.g., CPUs and I/O units. (Id. at
p. 10, lines 1518, p. 11, lines 1415, p. 20, lines 4043 (EX1005)); (Yalamanchili
127 (EX1006)). Gagliardo further discloses that an identification of the source
making a memory request is sent to the ACU 34, along with the memory
command.
(Gagliardo at p. 7, lines 4344, p. 20, lines 4348 (EX1005));
(Yalamanchili 127 (EX1006)). Thus, the combination of Flynn and Gagliardo

teaches limitation (d) of claim 1. (Yalamanchili 127 (EX1006)).
e)
wherein said memory controller is configured to
schedule accesses to a memory in response to said memory

requests.
Gagliardos ACU 34 in combination with Flynns SCU 14 teaches this
limitation.
Gagliardo discloses that if an
addressed memory segment is found to be busy, due to a variety of reasons

including a cycle delay in loading and unloading DRAM or due to the need for the
memory to be periodically refreshed on a per segment basis, the ACU 34 continues
53
Patent 6,546,439
monitoring the memory segment and reports back to the SCU 14 when the address
segment becomes available, so that a desired memory operation can proceed.
(Gagliardo at p. 7, lines 47 (EX1005)); (Yalamanchili 129 (EX1006)). In the
meantime, the ACU 34, through suitable buffering, continues processing, on a
sequential basis, of other memory access commands which are logged with the
SCU 14 and require access to a memory segment which is available at the time.
(Gagliardo at p. 7, lines 810 (EX1005)); (Yalamanchili 129 (EX1006)). Thus,
the ACU 34 schedules access to memory based, e.g., on the availability of the
memory segments corresponding to the received memory requests. (Yalamanchili
129 (EX1006)).
Further, Gagliardo describes that if the requesting unit is found to be a
CPU, step 264 is initiated and the memory system follows the CPU restriction
protocol which preferably includes the restriction of write transfers to eight quadwords at a time and the specification of a single mask bit for every long-word of
transferred data. (Gagliardo at p. 20, lines 4548 (EX1005)). Similarly, [i]f the
requesting unit is found to be an I/O unit, step 265 is undertaken wherein the I/O
protocol of restrictions is followed wherein write transfers are preferably permitted
for any one of 1, 2, 4, 6, or 8 quad-words. (Id. at p. 20, lines 4952 (EX1005)).
The memory controller of Gagliardo, the ACU, therefore receives the source
indication, e.g., indication of whether the requesting unit is a CPU or I/O unit, and
54
Patent 6,546,439
takes this information into consideration to schedule access to memory.
(Yalamanchili 130 (EX1006)). Further, Gagliardo envisions that the ACU 34
may use this identification to facilitate prioritizing of memory commands and
help routing of accessed data appropriately through the ACU and SCU to the
system unit originating the command. (Gagliardo at p. 7, lines 4446 (EX1005));
(Yalamanchili 130 (EX1006)). Thus, Flynn in combination with Gagliardo
teaches limitation (e) of claim 1. (Yalamanchili 130 (EX1006)).
5.
a)
requested memory operation buffer is further configured to

provide one or more parameters for each said memory request
in addition to said source indication to said memory controller
for use in scheduling the memory requests.
Flynn discloses that commands 114 are stored within the command
buffer and discloses the manner in which these commands are implemented
(Yalamanchili 132 (EX1006)); (Flynn at 6:3648, 11:24, Figure 3 (EX1004)).
The specific embodiment provided in Gagliardo, at page 10, lines 21-30 and Table
A, discloses the use of parameters associated with a command. (Yalamanchili
132 (EX1006)). These commands 114 are provided by the command buffer 115
and are ultimately received by the memory controller in Gagliardo. (Yalamanchili
132 (EX1006)); (Flynn at 11:49, Figure 3 (EX1004)). Thus, Flynn teaches the
55
Patent 6,546,439
claimed one or more parameters.
The
commands 114 are stored in addition to said source indication. For example, as
described above, the latches 07 store and provide the source indication.
(Yalamanchili 132 (EX1006)); (Flynn at 12:4041, Figure 4. (EX1004)).
Gagliardo teaches that its memory controller, i.e. the ACU, uses (1) the
command parameters provided by the command buffer 114 and (2) the source
indications, e.g., RE 00REQ 08, provided by the latches 0-7 that are associated
with the command buffer 114, for scheduling the memory requests. (Yalamanchili
133 (EX1006)). For example, Gagliardo teaches to schedule memory requests
by managing the timing of processing the requests based on availability of system
resources.
(Gagliardo at p.7, lines 47 (EX1005))); (Yalamanchili 133
(EX1006)).
Further, Gagliardo discloses that the ACU schedules different protocols
based on whether the requesting unit is found to be a CPU or found to be an I/O
unit. (Gagliardo at p. 20, lines 45952 (EX1005)). The ACU of Gagliardo
therefore receives the source indication, e.g., indication of whether the requesting
unit is a CPU or I/O unit, and takes this information into consideration when
scheduling the memory requests, as required by claim 4. (Yalamanchili 134
(EX1006)). Thus, Flynn in combination with Gagliardo teaches the limitations of
56
Patent 6,546,439
6.
a)

Flynn discloses that commands 114 (i.e., parameters) are stored within the
command buffer for each memory request.
(Flynn at 11:24, Figure 3
(EX1004))); (Yalamanchili 136 (EX1006). A person of ordinary skill in the art

would have understood that the commands are stored in a data structure.
(Yalamanchili 136 (EX1006)). In particular, the commands are stored in a data
structure that includes information associated with a memory request.
(Yalamanchili 136 (EX1006)). Flynn therefore teaches or suggests the recited
tag. (Yalamanchili 136 (EX1006)).
7.
a)
The system as recited in claim 1, wherein said plurality
of sources comprises a central processing unit interface.

The combination of Flynn and Gagliardo teaches or suggests claim 11. For
example, Flynn and Gagliardo each teaches or suggests the recited central
processing unit (CPU) interface. (Yalamanchili 138 (EX1006)). Flynn teaches
receiving requests from a plurality of central processing units (CPUs) 12. (Flynn
at 6:1314 (EX1004)).
Figure 1 of Flynn shows connections between the CPUs
and the SCU. (Id. at Figure 1 (EX1004)).
57
Flynn further describes that at least
Patent 6,546,439
eight ports are provided on the SCU for accepting requests and associated
commands from corresponding system units. (Id. at 11:3033 (EX1004)). It
would have been obvious to a person of ordinary skill in the art that these
connections and ports teach the recited CPU interface.
(Yalamanchili 138
(EX1006)).
Gagliardo teaches receiving requests from a plurality of central processing
units (CPUs) 12. (Gagliardo at p. 5:31 (EX1005)).
Figure 1 of Gagliardo,
similar to Figure 1 of Flynn, shows connections between the CPUs and the SCU.
(Id. at Figure 1 (EX1005)). Gagliardo further describes that at least eight ports
are provided on the SCU for accepting requests and associated commands from
corresponding system units.
(Id. at 11:3033 (EX1005)).
Gagliardo each teaches or suggests this limitation.
Thus, Flynn and
(Yalamanchili 139
(EX1006)).
8.
a)
The system as recited in claim 1, wherein said source
indication comprises an identity of a request initiator for the

memory request.
Flynn teaches or suggests the claimed identity of a request initiator. As
described above with respect to FIG. 4 and limitation (a) of claim 1, Flynn
discloses that the latches provide an indication of the source by virtue of sending
the REQ XX signals. (Yalamanchili 141 (EX1006)). The signals REQ 00
58
Patent 6,546,439
REQ 07, which are shown in Figure 4 as being provided by the latches, represent
the different sources and are therefore source indications. (Yalamanchili 141
(EX1006)). For example, the signal REQ 00 indicates that the device at CPU port
0 made a memory request. (Flynn at 11:68-12:3 (EX1004))); (Yalamanchili 141
(EX1006). A person of ordinary skill in the art would have understood that these
source indications each provide an identity of a request initiator for the memory
request, by indicating, for example, that the CPU at port 0 made the request.
9.
a)
A method, comprising: receiving memory requests
from a plurality of sources;

As noted above in Section VII.B.4, the combination of Flynn and Gagliardo
teaches A method comprising: receiving memory requests from a plurality of
sources.
b)
associating a source indication for each memory
request of the one of said plurality of sources from which the

memory request was received; and
teaches associating a source indication for each memory request of the one of said
plurality of sources from which the memory request was received.
59
Patent 6,546,439
c)
scheduling execution of said memory requests based
on said source indication.

teaches scheduling execution of said memory requests based on said source
indication.
10.
a)
The method as recited in claim 17, further comprising
associating one or more parameters with each said memory

request in addition to said source indication for use in said
scheduling.
teaches associating one or more parameters with each said memory request in
addition to said source indication for use in said scheduling.
11.
a)


teaches wherein the one or more parameters for each memory request are stored
within a tag associated with each memory request.
12.
60
Patent 6,546,439
a)
27. The method as recited in claim 17, wherein said
plurality of sources comprises a central processing unit

interface.
teaches wherein said plurality of sources comprises a central processing unit
interface.
13.
a)
source indication comprises an identity of a request initiator

teaches wherein said source indication comprises an identity of a request initiator
61
Patent 6,546,439
VIII. CONCLUSION
Based on the foregoing, the challenged claims of the 439 patent recite
subject matter that is unpatentable. The Petitioner requests institution of an inter
partes review to cancel these claims.
Respectfully Submitted,
/David L. Cavanaugh/
David L. Cavanaugh
Registration No. 36,476
Jonathan Stroud
Daniel V. Williams
62
Patent 6,546,439
Exhibit
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
Description
US Patent 6,546,439
US Patent 5,784,582 (Hughes) (filed on October 28, 1996,
published on July 21, 1998)
US Patent 5,745,913 (Pattin) (filed on August 5, 1996,
published on April 28, 1998)
US Patent 5,155,854 (Flynn) (filed on February 3, 1989,
published on October 13, 1992)
European Patent Application 0 380 844 (Gagliardo)
(published on August 8, 1990)
Declaration of Professor Sudhakar Yalamanchili
File History, Application (12/09/98)
File History, Amendment (4/22/02)
File History, Office Action (5/21/02)
File History, Request for Consideration (8/23/02)
File History, Notice of Allowability (9/25/02)
U.S. Application No. 07/306, 326 (326 application), filed
February 3, 1989.
Petitioners Voluntary Interrogatory Responses
Patent 6,546,439
CERTIFICATE UNDER 37 CFR 42.24(d)
Under the provisions of 37 CFR 42.24(d), the undersigned hereby certifies
that the word count for the foregoing Petition for Inter Partes Review totals
11,494, which is less than the 14,000 words allowed under 37 CFR 42.24(a)(i).
Respectfully submitted,
Dated: May 11, 2016
/Daniel V. Williams/
Daniel V. Williams
Reg. No. 45,221
Wilmer Cutler Pickering Hale and Dorr LLP
1875 Pennsylvania Ave., NW
Washington, DC 20006
Tel: (202) 663-6000
Patent 6,546,439
CERTIFICATE OF SERVICE
I hereby certify that on May 11, 2016, I caused a true and correct copy of the
foregoing materials:
Petition for Inter Partes Review of U.S. Patent No. 6,546,439 Under 35
U.S.C. 312 and 37 C.F.R. 42.104
Exhibit List
Exhibits for Petition for Inter Partes Review of U.S. Patent No. 6,546,439
(EX10011013)
Power of Attorney
Fee Authorization
Word Count Certification Under 37 CFR 42.24(d)
to be served via Express Mail on the following correspondent of record as listed on
PAIR:
MEYERTONS, HOOD, KIVLIN, KOWERT & GOETZEL (AMD)
P.O. BOX 398
AUSTIN TX 78767-0398
/Daniel V. Williams/
Daniel V. Williams
ii

Unified Patents Inc. v. Advanced Silicon Technologies, LLC, IPR2016-01026, Paper 1 (May 11, 2016)

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IPR2016-01026 Petition

BEFORE THE PATENT TRIAL AND APPEAL BOARD

UNIFIED PATENTS INC.

MANDATORY NOTICES ............................................................................. 1

Real Party-in-Interest ............................................................................ 1

CERTIFICATION OF GROUNDS FOR STANDING .................................. 2

OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 2

Prior Art Patents and Printed Publications ............................................ 3

US Patent 5,784,582 (filed on October 28, 1996,

Grounds for Challenge .......................................................................... 3

OVERVIEW OF THE 439 PATENT ............................................................ 5

Summary of the Alleged Invention ....................................................... 5

CLAIM CONSTRUCTION ............................................................................ 9

source indication .............................................................................. 10

Overview of Hughes ................................................................. 12

Overview of Flynn .................................................................... 35

Pursuant to 37 C.F.R. 42.8(b)(1), Unified Patents Inc. (Unified or

US Pat. No. 6,546,439 (439 patent (EX1001)) is owned by Advanced

Service Information, Email, Hand Delivery and Postal

Unified consents to electronic service at david.cavanaugh@wilmerhale.com

CERTIFICATION OF GROUNDS FOR STANDING

OVERVIEW OF CHALLENGE AND RELIEF REQUESTED

Prior Art Patents and Printed Publications

The following references are pertinent to the grounds of unpatentability

US Patent 5,784,582 (filed on October 28, 1996, published on

US Patent 5,745,913 (filed on August 5, 1996, published on

US Patent 5,155,854 (filed on February 3, 1989, published on

European Patent Application 0 380 844 (published on August 8,

Grounds for Challenge

This Petition, supported by the declaration of Professor Sudhakar

America Invents Act (AIA). Accordingly, pre-AIA statutory framework applies.

accessing memory was a major limiting factor on overall system speed.

The memory controller receives memory access requests from

Further, US Pat. 6,032,232, filed in May 29, 1997, disclosed a

OVERVIEW OF THE 439 PATENT

Summary of the Alleged Invention

Independent claims 1 and 17 were allowed based on the incorrect premise

The sources may include, for

(439 patent at Figure 5 (EX1001) (annotations added). The memory controller

(Id. at 10:113 (EX1001));

(Yalamanchili 15 (EX1006)). For example, if a memory access request is stored

The tags 302 are used to associate additional

Level of Ordinary Skill in the Art

broadest reasonable construction in light of the specification.

Petitioner applies the broadest reasonable construction standard as required by

the governing regulations. 37 C.F.R. 42.100(b). Petitioner reserves the right to

Any claim terms not included should be given their broadest

reasonable interpretation in light of the specification, as commonly understood by

The term source indication should be interpreted to mean information

A term tag should be interpreted as a data structure that includes

Hughes discloses to use a memory controller to select a next request for

(EX1002)); (Yalamanchili 31 (EX1006)). Thus, a next request can be selected

a shared memory, controller/arbiter that comprises a memory

Figure 3 of Hughes, also reproduced below with annotations, shows the

Pattin is directed to a system that includes multiple sources that access a

(Pattin at 1:5154 (EX1003)); (Yalamanchili 37

(Pattin at 7:2628, 8:1416, 11:6412:5, 12:2730 (EX1003));

Motivation to Combine Hughes and Pattin

Further, both Pattin and Hughes store their

attributes in a buffer, so that this information can be used by a memory controller

This would provide an efficient way for the

memory controller of Hughes to identify the source.

Claim 1 is obvious in view of Hughes and Pattin

Preamble: A system comprising: