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XILINX PROJECT NAVIGATOR TOOL TUTORIAL

1. Double click on Project Navigator on your desktop.
2. Select File -> New Project. The New Project dialog box will appear.
3. In the Project line, type in a name for your project. Then select a directory
for the project files. You may type in the path, or you may click the browse
button to find a directory to place the files.
4. Select the Top-Level Module Type value box. For VHDL, Verilog, or ABEL
designs, select HDL. Click Next.
5. The dialog changes to allow you to select device and design flow method.
Selection of device:
Product Category

All

Family

Spartan 3

Device

XC3S400

Package

TQ144

Speed

-5

XC3S400

->

XC Xilinx Corporation
3S Spartan 3 families
400 Gate Capacity
TQ Thin Quad Package

6. After you click Next from the Device and Design Flow dialog box, the New
Source dialog box will appear.
7. Create a source file. Click New Source. The New source type dialog box
appears. Select the type of source file you wish to create. Select VHDL
Module as the type of our main design source. Next, enter the name and
location for the new source design.
8. Click Next >. The Define VHDL Source dialog will appear.
9. Type the desired module name into the Entity Name text box. For VHDL
designs, you can also change the Architecture Name.
10. Type the name of each port of your source module into the Port Name
column. Specify whether each port is an input or output by clicking in the
Direction column and pulling down the selection list.
11. Click the Next button and the New Source Information dialog box will
appear.
12. Examine the information, then click Finish. The Create a New Source
dialog box will appear with your new source file listed.
13. Click Next. Click Next, Click Finish. The first new module is
automatically added to the project as the top-level module of the project.
You will now use the HDL Editor window to define the contents of your
design. When complete, Save your design source. You can repeat the above
procedure to create additional design sources in your project hierarchy.
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14. With the module name (my_mod) selected in the Sources window,
double-click Check Syntax (found under Synthesize) to check the VHDL
syntax. The transcript on the Project Navigator will let you know if the
syntax is correct and places a green check next to Check Syntax. If the
syntax check fails, a red x will appear.
15. Select pins 45 to pin 63 as output pins except pins 49, 59, 60.
16. Select pins 65 to pin 84 as input pins except pins 73, 74,76,77,78.
17. Enable input pins from switches on CPLD board, observe the output
LEDs glowing.
18. Close the xilinx pace window
19. Double click on Generate Programming File then it will show completed
process Generate Programming File in console window
20. Connect the Xilinx JTAG Parallel Download Cable to your PC. Then
connect the cable to your target device JTAG pins as specified in the device
data sheet (and turn on the power to your target device).
21. After you have successfully implemented your design, double-click
Configure Device [IMPACT] in the Processes window under Generate
Programming File. This will generate a JEDEC file and bring up the iMPACT
interface. A dialog will appear. Select Boundary-Scan Mode and click Next.
Note: For CPLD designs, you can also highlight the Configure Device
[iMPACT] process in the Project Navigator window and select Process -> Run.
22. The Boundary Scan selection mode dialog box will then ask if you want
to automatically connect, or just enter a boundary-scan chain (manually). If
you have a demo board, select the automatic mode, otherwise manually
create a boundary-scan chain using Enter a Boundary-Scan Chain.
23. Click Finish. The program automatically detects the chain. When it
finds a device, it brings up a file dialog and the program queries you for a
JED, BSDL or BIT file for the device. Locate the *.jed file for your design and
click OK. The part displays as shown below.
24. Start the iMPACT programming operation by highlighting the device
(click on it once) and selecting Operations -> Program:
You will see the following screen:
25. Select Erase Before Programming and Verify, then click OK.
When programming is complete an message will appear and inform you of
the results.
To Assign Package Pins
1. Select the design module in the Sources in Project window for which you
want to assign a pin package.
2. Double-click the Assign Package Pins process in the Processes for Source
window.

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EXPERIMENT 1: REALIZATION OF LOGIC GATES

AIM:

a) Write VHDL / Verilog code to realize AND gate.

b) Write VHDL / Verilog code to realize all logic gates

THEORY: The gate is a digital circuit with one or more input voltages but
only one output voltage. By connecting the different gates in different ways,
we can build circuits that perform arithmetic and other functions.
Logic gates are the basic elements that make up a digital system. The
Electronic gate is a circuit that is able to operate on a number of binary
inputs in order to perform a particular logic function. The types of gates
available are the NOT, AND, OR, NAND, NOR, EXCLUSIVE-OR, and
EXCLUSIVE-NOR.

TRUTH TABLE FOR ALL GATES:

Inputs

Outputs

C(0) AND

C(1)
OR

C(2)
XOR

C(3)
NOT
(A)

C(4)
NOT
(B)

C(5)
NAND

C(6)
NOR

C(7)
XNOR

0
0
1
1

0
1
0
1

0
0
0
1

0
1
1
1

0
1
1
0

1
1
0
0

1
0
1
0

1
1
1
0

1
0
0
0

1
0
0
1

--VHDL code to realize AND gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port (a.b : in std_logic;
y: out std_logic);
end and2;
architecture Behavioral of and2 is
begin
y<=a and b;
end Behavioral ;
-----------------------------------------------------------------------------------------------Verilog code to realize AND gate
module and3(a,b,c);
input a;
input b;
output c;
assign c=a & b;
endmodule
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--VHDL code to realize all the logic gates (Data flow description)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logicgates is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic_vector(7 downto 0));
end logicgates;
architecture Behavioral of logicgates is
begin
c(0)<=
c(1)<=
c(2)<=
c(3)<=
c(4)<=
c(5)<=
c(6)<=
c(7)<=

a and b;
a or b;
a xor b;
not a;
not b;
a nand b;
a nor b;
a xnor b;

end Behavioral;
___________________________________________________________________________
--VHDL code to realize all the logic gates using case statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logicgates is
Port ( a : in std_logic;
b : in std_logic;
s : in std_logic_vector(2 downto 0);
c : out std_logic);
end logicgates;
architecture Behavioral of logicgates is
begin
process (a,b,s)
begin
case s is
when "000"=> c<=(a and b);
when "001"=> c<=(a or b);
when "010"=> c<=(a xor b);
when "011"=> c<=(not a);
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when "100"=> c<=(not b);

when "101"=> c<=(a nand b);
when "110"=> c<=(a nor b);
when others=> c<=(a xnor b);
end case;
end process;
end Behavioral;
__________________________________________________________________________
--Verilog code to realize all the logic gates (Data flow description)
module basicgates(a,b,c);
input a;
input b;
output [6:0]c;
assign c[0]=a & b;
assign c[1]=a | b;
assign c[2]=a ^ b;
assign c[3]=~(a ^ b);
assign c[4]= ~ a;
assign c[5]=~(a & b);
assign c[6]=~(a | b);
endmodule
RESULTS:

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EXPERIMENT 2: REALIZATION OF COMBINATIONAL LOGIC DESIGN

i) 2 to 4 DECODER
AIM:

Write VHDL /Verilog code for 2 to 4 DECODER.

THEORY:
A decoder is a combinational circuit that converts binary information from n
input lines to a maximum of 2n unique output lines. A binary code of n bits
is capable of representing up to 2n distinct elements of the coded
information.
A 2-to-4-line decoder, the two inputs are decoded into four outputs, each
output representing one of the minterms of the 2-input variables. A 2-to-4
decoder can be used for decoding any 2 bit code to provide 4-outputs, one
for each element of the code.
BLOCK DIAGRAM:

Y(0)

I(0)

I(1)

Y(1)

2:4
DECODER

Y(2)
Y(3)

Enb
TRUTH TABLE:
Inputs
Enb
I1
0
X
1
0
1
0
1
1
1
1

I0
X
0
1
0
1

Y(3)
0
0
0
0
1

Outputs
Y(2) Y(1)
0
0
0
0
0
1
1
0
0
0

Y(0)
0
1
0
0
0

--VHDL code for 2 to 4 DECODER (using case statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder2_4 is
Port ( i : in std_logic_vector(1 downto 0);
enb : in std_logic;
y : out std_logic_vector(3 downto 0));
end decoder2_4;
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architecture Behavioral of decoder2_4 is

begin
y<=0000;
process(i,enb)
begin
if(enb='1')then
case (i) is
when "00"=>y<="0001";
when "01"=>y<="0010";
when "10"=>y<="0100";
when "11"=>y<="1000";
when others=>null;
end case;
else y<="0000";
end if;
end process;
end Behavioral;
___________________________________________________________________________
--Verilog code for 2 to 4 DECODER (using case statement)
module decoder2_4(i,en,y);
input [1:0]i;
input en;
output [3:0]y;
reg [3:0]y;
always @(i,en)
begin
if (en==1)
case (i)
2'b00:y=4'b0001;
2'b01:y=4'b0010;
2'b10:y=4'b0100;
default:y=4'b1000;
endcase
else
y=4'b0000;
end
endmodule
___________________________________________________________________________
--VHDL code for 2 to 4 DECODER (using if else statement)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder2_4 is
Port ( i : in std_logic_vector(1 downto 0);
en : in std_logic;
y : out std_logic_vector(3 downto 0):=0000);
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end decoder2_4;
architecture Behavioral of decoder2_4 is
begin
process(i,en)
begin
if(en='1') then
if(i="00") then y<="0001";
elsif(i="01") then y<="0010";
elsif(i="10") then y<="0100";
else y<="1000";
end if;
end if;
end process;
end Behavioral;
___________________________________________________________________________
--Verilog code for 2 to 4 DECODER (using else if statement)
module decoder2_4(i,en,y);
input [1:0]i;
input en;
output [3:0]y;
reg [3:0]y;
always @(en,i)
begin
if(en==1)
begin
if (i==2'b00)
y=4'b0001;
else if(i==2'b01)
y=4'b0010;
else if(i==2'b10)
y=4'b0100;
else
y=4'b1000;
end
else
y=4'bzzzz;
end
endmodule
--VHDL code for 2 to 4 DECODER (Structural Description)
--TOP LEVEL MODULE-library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder2_4 is
Port(i0,i1,en : in std_logic;
y0,y1,y2,y3: out std_logic);
end decoder2_4;
architecture structural of decoder2_4 is
component notgate
port(a:in std_logic;
b:out std_logic);
end component;
component andgate
port(c,d,e:in std_logic;
f:out std_logic);
end component;
signal s1,s2:std_logic;
begin
u0:notgate port map(i0,s1);
u1:notgate port map(i1,s2);
u2:andgate port map(s1,s2,en,y0);
u3:andgate port map(s1,i1,en,y1);
u4:andgate port map(i0,s2,en,y2);
u5:andgate port map(i0,i1,en,y3);
end structural;
___________________________________________________________________________
--LOW LEVEL MODULE-library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity andgate is
port(c,d,e:in std_logic;
f:out std_logic);
end andgate;
architecture Behavioral of andgate is
begin
f<= c and d and e;
end Behavioral;
-----------------------------------------------------------------------------------------------LOW LEVEL MODULE-library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity notgate is
port(a:in std_logic;
b:out std_logic);
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end notgate;
architecture Behavioral of notgate is
begin
b<= not a;
end Behavioral;
---------------------------------------------------------------------------------------------RESULTS:

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ii) 8 to 3 ENCODER
AIM: Write VHDL code for 8 to 3 ENCODER with priority and without
priority.
THEORY: An encoder is a digital function that produces a reverse operation
from that of decoder. An encoder has 2n (or less) input lines and n output
lines. The output lines generate the binary code for 2n input variables. The
encoder assumes that only one input line can be equal to 1 at any time.
Otherwise the circuit has no meaning. If the encoder has 8 inputs and could
have 28 = 256 possible input combinations.
Priority Encoder: These encoders establish an input priority to ensure that
only the highest priority line is encoded. For example 8-to-3-line priority
encoder the inputs are I(0) ,I(1) ,.I(7).If the priority is given to an input
with higher subscript number over one with a lower subscript number , then
if both I(2) and I(5) are logic-1 simultaneously , the output will be 101
because I(5) has higher priority over I(2).
BLOCK DIAGRAM:
I (0)
I (1)

Y(0)

I (2)

Y(1)

I (3)
I (4)

Y(2)

8:3
ENCODER

I (5)
I (6)
I (7)

TRUTH TABLE:
8:3 Encoder with Priority
Enb I(0)
0
X
1
1
1
X
1
X
1
X
1
X
1
X
1
X
1
X

I(1)
X
0
1
X
X
X
X
X
X

ACIT, BANGALORE

I(2)
X
0
0
1
X
X
X
X
X

Enb

Inputs
I(3)
I(4)
X
X
0
0
0
0
0
0
1
0
X
1
X
X
X
X
X
X

I(5)
X
0
0
0
0
0
1
X
X

I(6)
X
0
0
0
0
0
0
1
X

I(7)
X
0
0
0
0
0
0
0
1

Y(2)
0
0
0
0
0
1
1
1
1

Outputs
Y(1) Y(0)
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1

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8:3 Encoder without Priority

Enb
0
1
1
1
1
1
1
1
1

I(0)
X
1
0
0
0
0
0
0
0

I(1)
X
0
1
0
0
0
0
0
0

Inputs
I(2)
I(3)
I(4)
X
X
X
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0

I(5)
X
0
0
0
0
0
1
0
0

I(6)
X
0
0
0
0
0
0
1
0

I(7)
X
0
0
0
0
0
0
0
1

Outputs
Y(2) Y(1) Y(0)
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

--VHDL code for 8 to 3 ENCODER with priority

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prencoder8_3 is
Port ( enb:in std_logic:
i : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end prencoder8_3;
architecture Behavioral of prencoder8_3 is
begin
process(i,enb)
begin
if(enb=1) then
if(i(7)='1') then y<="111";
elsif(i(6)='1') then y<="110";
elsif(i(5)='1') then y<="101";
elsif(i(4)='1') then y<="100";
elsif(i(3)='1') then y<="011";
elsif(i(2)='1') then y<="010";
elsif(i(1)='1') then y<="001";
elsif(i(0)='1') then y<="000";
else y<="ZZZ";
end if;
else
y<=000;
end if;
end process;
end Behavioral;
___________________________________________________________________________

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--Verilog code for 8 to 3 ENCODER with priority

module encoder8_3(i,enb,y);
input [7:0]i;
input enb;
output [2:0]y;
reg [2:0]y;
always @(enb,i)
if(enb==1)
begin
if(i[7]==1)
y=3'b111;
else if(i[6]==1)
y=3'b110;
else if(i[5]==1)
y=3'b101;
else if(i[4]==1)
y=3'b100;
else if(i[3]==1)
y=3'b011;
else if(i[2]==1)
y=3'b010;
else if(i[1]==1)
y=3'b001;
else if(i[0]==1)
y=3'b000;
else y=3'bzzz;
end
else y=3'bzzz;
endmodule
--VHDL code for 8 to 3 ENCODER without priority
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder8_3 is
Port ( en: in std_logic;
i : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end encoder8_3;
architecture Behavioral of encoder8_3 is
begin
process(i,en)
begin
if(en=1) then
case i is
when "00000001"=>y<="000";
when "00000010"=>y<="001";
when "00000100"=>y<="010";
when "00001000"=>y<="011";
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when "00010000"=>y<="100";
when "00100000"=>y<="101";
when "01000000"=>y<="110";
when "10000000"=>y<="111";
when others=>null;
end case;

else
y<=000;
end if;
end process;
end Behavioral;
--Verilog code for 8 to 3 ENCODER without priority
module encoder_wp(i,en,y);
input [7:0]i;
input en;
output [2:0]y;
reg[2:0]y;
always @(en,i)
if(en==1)
begin
case (i)
8'b 00000001: y=0;
8'b 00000010: y=1;
8'b 00000100: y=2;
8'b 00001000: y=3;
8'b 00010000: y=4;
8'b 00100000: y=5;
8'b 01000000: y=6;
8'b 10000000: y=7;
default: y=3'bzzz;
end case
end
else
y=3'bzzz;
endmodule
RESULTS:

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iii). 8 to 1 MUX
AIM: Write VHDL code for 8 to 1 MUX.
THEORY: A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output
line. A multiplexer is also called as data selector, since it selects one of many
inputs and steers the binary information to the output line. The selection of
particular input line is controlled by a set of selection lines. Normally there
are 2n input lines and n selection lines whose bit combinations determine
which input is selected.
BLOCK DIAGRAM:
I(0)
I(1)
I(2)
I(3)

I(4)
I(5)

8:1
MULTIPLEXER

I(6)
I(7)

S(2) S(1) S(0)

TRUTH TABLE:
Inputs
S(2) S(1) S(0)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Outputs
Y
I(0)
I(1)
I(2)
I(3)
I(4)
I(5)
I(6)
I(7)

-- VHDL code for 8 to 1 MUX (using if else statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8_1 is
Port ( i : in std_logic_vector(7 downto 0);
s : in std_logic_vector(2 downto 0);
y : out std_logic);
end mux8_1;
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architecture Behavioral of mux8_1 is

begin
process(s,i)
begin
if (s="000") then y<=i(0);
elsif(s="001") then y<=i(1);
elsif(s="010")then y<=i(2);
elsif(s="011")then y<=i(3);
elsif(s="100")then y<=i(4);
elsi f(s="101")then y<=i(5);
elsif(s="110")then y<=i(6);
else y<=i(7);
end if;
end process;
end Behavioral;
___________________________________________________________________________
-- Verilog code for 8 to 1 MUX (using case statement)
module mux4(i,s,y);
input [7:0] i;
input [2:0] s;
output y;
reg y;
always @(i,s)
begin
case (s)
3'b000: y=i[0];
3'b001:y=i[1];
3'b010:y=i[2];
3'b011:y=i[3];
3'b100:y=i[4];
3'b101:y=i[5];
3'b110:y=i[6];
default:y=i[7];
endcase
end
endmodule
RESULTS:

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iv).BINARY TO GRAY CONVERTER.

AIM:

Write VHDL code for BINARY TO GRAY CONVERTER.

THEORY: A Gray code represents each number in the sequence of integers

as a binary string of length N in an order such that adjacent integers have
Gray code representations that differ in only one bit position. The advantage
of the gray code is that only one bit will change as it proceeds from one
number to the next. To obtain gray code, one can start with any bit
combination by changing only one bit from 0 to 1 or 1 to 0 in any desired
random fashion, as long as two numbers do not have identical code
assignments.
BLOCK DIAGRAM:
B(0)
B(1)
B(2)
B(3)

Binary
to
Gray
Converter

G(0)
G(1)
G(2)
G(3)

TRUTH TABLE:
Inputs
Binary Codes
B(3) B(2) B(1) B(0)
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1

ACIT, BANGALORE

Outputs
Gray Codes
G(3) G(2) G(1) G(0)
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
0

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-- VHDL code for BINARY TO GRAY CONVERTER (using case statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin2gray is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end bin2gray;
architecture Behavioral of bin2gray is
begin
process(b)
begin
case b is
when "0000"=>g<="0000";
when "0001"=>g<="0001";
when "0010"=>g<="0011";
when "0011"=>g<="0010";
when "0100"=>g<="0110";
when "0101"=>g<="0111";
when "0110"=>g<="0101";
when "0111"=>g<="0100";
when "1000"=>g<="1100";
when "1001"=>g<="1101";
when "1010"=>g<="1111";
when "1011"=>g<="1110";
when "1100"=>g<="1010";
when "1101"=>g<="1011";
when "1110"=>g<="1001";
when "1111"=>g<="1000";
when others=>null;
end case;
end process;
end Behavioral;
----------------------------------------------------------------------------------------------- VHDL code for BINARY TO GRAY CONVERTER (Data flow description)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin2gray is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end bin2gray;
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architecture dataflow of bin2gray is

begin
g(0)<=b(0) xor b(1);
g(1)<=b(1) xor b(2);
g(2)<=b(2) xor b(3);
g(3)<=b(3);
end dataflow;
---------------------------------------------------------------------------------------------- Verilog code for BINARY TO GRAY CONVERTER (Data flow description)
module bin2gray(b,g);
input [3:0]b;
output [3:0]g;
assign g[0]=b[0] ^ b[1];
assign g[1]=b[1] ^ b[2];
assign g[2]=b[2] ^ b[3];
assign g[3]=b[3];
endmodule
----------------------------------------------------------------------------------------------- VHDL code for BINARY TO GRAY CONVERTER (Structural description)
--TOP LEVEL MODULE-library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin2gray is
Port(b3,b2,b1,b0: in std_logic;
g3,g2,g1,g0: out std_logic);
end bin2gray;
architecture structural of bin2gray is
component xor2 is
port(a,b:in std_logic;
c:out std_logic);
end component;
begin
g3<=b3;
u0:xor2 port map(b3,b2,g2);
u1:xor2 port map(b2,b1,g1);
u2:xor2 port map(b1,b0,g0);
end structural;
-----------------------------------------------------------------------------------------------LOW LEVEL MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a ,b: in std_logic;
c: out std_logic);
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end xor2;
architecture Behavioral of xor2 is
begin
c<=a xor b;
end Behavioral;

RESULTS:

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v). 1 to 4 DEMUX.
AIM:

Write VHDL code for 1 TO 4 DEMUX.

THEORY: A demultiplexer is a circuit that receives the information on a

single line and transmits this information on one of 2n possible output lines.
The selection of specific output lines is controlled by the values of n
selection lines. For 1: 4 demultiplexers, the single input variable has a path
to all the four outputs, but the input information is directed to only one of
the 4 output lines.
BLOCK DIAGRAM:
Y(0)
Y(1)

Y(2)

1:4 DEMUX

Y(3)

S(1)

S(0)

TRUTH TABLE:
Inputs
Select
Inputs
S(1) S(0)
0
0
0
1
1
0
1
1

Outputs
Demux Output
y(3)
0
0
0
I

y(2)
0
0
I
0

y(1)
0
I
0
0

y(0)
I
0
0
0

-- VHDL code for 1 TO 4 DEMUX (using case statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux1_4 is
Port ( i : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0));
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end demux4_1;
architecture Behavioral of demux1_4 is
begin
process(s,i)
begin
Y<=0000;
case s is
when "00"=>y(0)<=i;
when "01"=>y(1)<=i;
when "10"=>y(2)<=i;
when "11"=>y(3)<=i;
when others=>null;
end case;
end process;
end Behavioral;
---------------------------------------------------------------------------------------------- Verilog code for 1 TO 4 DEMUX (using case statement)
module demux1_4(i,s,y);
input i;
input [1:0]s;
output [3:0]y;
reg [3:0]y;
always @(i,s)
begin
Y=4b0000;
case (s)
2'b00:y[0]=i;
2'b01:y[1]=i;
2'b10:y[2]=i;
default:y[3]=i;
endcase
end
endmodule
RESULTS:

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vi). COMPARATOR.
AIM:

Write VHDL code for 2-BIT COMPARATOR.

THEORY: A comparator is a combinational circuit that compares two

numbers, A and B, and then determines their relative magnitudes. The
comparison of two numbers is an operation that determines if one number
is greater than, less than or equal to the other number. The outcome of the
comparison is specified by three binary variables that indicate whether A >
B, A = B, A < B.
BLOCK DIAGRAM:
A
B

A=B
1:0

1:0

2-BIT
COMPARATOR

A>B
A<B

TRUTH TABLE:

A(1)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

ACIT, BANGALORE

Inputs
A
B
A(0) B(1) B(0)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Outputs
A=B A>B A<B
E
G
L
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0

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-- VHDL code for 2-bit comparator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comp2 is
Port ( a : in std_logic_vector(1 downto 0);
b : in std_logic_vector(1 downto 0);
l ,e,g: out std_logic);
end comp2;
architecture Behavioral of comp2 is
begin
process(a,b)
begin
l<='0';e<='0';g<='0';
if (a<b)then l<='1';
elsif (a=b)then e<='1';
else g<='1';
end if;
end process;
end Behavioral;
---------------------------------------------------------------------------------------------- Verilog code for 2-bit comparator
module comp(a,b,l,e,g);
input [1:0]a,b;
output l,e,g;
reg l,e,g;
always @(a,b)
begin
l=0;e=0;g=0;
if(a > b)
g=1;
else if(a <b)
l=1;
else
e=1;
end
endmodule
----------------------------------------------------------------------------------------------- VHDL code for COMPARATOR (DATA FLOW DESCRIPTION)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity comp2b is
Port ( a,b: in std_logic_vector(1 downto 0);
l,e,g : out std_logic);
end comp2b;
architecture dataflow of comp2b is
begin
l<=( not a(1) and not a(0) and b(0))or (not a(0)and b(1) and b(0))
or(not a(1) and b(1));
e<=(a(0) xnor b(0)) and (a(1) xnor b(1));
g<=(a(0) and not b(1) and not b(0))or (a(1)and not b(1))
or(a(1) and a(0) and not b(0));
end dataflow;

RESULTS:

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EXPERIMENT 3: FULL ADDER

AIM:
i)
ii)
iii)

Write a VHDL code to describe the functions of a FULL ADDER using

Following modeling styles.
Dataflow description
Behavioral description
Structural description

THEORY: A combinational circuit that performs the addition of two bits is

called a half adder. One that performs the addition of three bits (two
significant bits and a previous carry) is a Full adder.
The most basic arithmetic operation is the addition of two binary digits. This
simple addition consists of four possible elementary operations namely 0 + 0
= 0, 0 + 1 = 1, 1 + 0 = 1, 1 + 1 = 10.The first three operations produce a sum
whose length is one digit, but when both augend and addend bits are equal
to 1,the binary sum consists of two digits. The higher significant bit is called
carry.
BLOCK DIAGRAM:
A

Sum

FULL
ADDER

Cin

Cout

TRUTH TABLE:
A
0
0
0
0
1
1
1
1

Inputs
B
0
0
1
1
0
0
1
1

Cin
0
1
0
1
0
1
0
1

Outputs
Sum Cout
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1

--VHDL code for FULL ADDER (Dataflow description)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( a,b,cin: in std_logic;
sum,cout: out std_logic);
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end full_adder;
architecture dataflow of full_adder is
begin
sum<=a xor b xor cin;
cout<=(a and b) or (b and cin) or (cin and a);
end dataflow;
----------------------------------------------------------------------------------------------Verilog code for FULL ADDER (Dataflow description)
module fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a ^ b ^ cin;
assign cout=(a & b)|(b & cin)|(cin & a);
endmodule
-----------------------------------------------------------------------------------------------VHDL code for FULL ADDER (Behavioral description)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( a,b,cin : in std_logic;
sum,cout : out std_logic);
end full_adder;
architecture Behavioral of full_adder is
signal s:std_logic_vector(2 downto 0);
begin
s<=a & b & cin;
process(s)
begin
case s is
when "000"=> sum<='0'; cout<='0';
when "001"=> sum<='1';cout<='0';
when "010"=> sum<='1';cout<='0';
when "011"=> sum<='0';cout<='1';
when "100"=> sum<='1';cout<='0';
when "101"=> sum<='0';cout<='1';
when "110"=> sum<='0';cout<='1';
when "111"=> sum<='1';cout<='1';
when others=> null;
end case;
end process;
end Behavioral;
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--Verilog code for FULL ADDER (Behavioral description)

module fulladderbeh(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always @(a,b,cin)
begin
case ({a,b,cin})
3'b000:begin sum=1'b0;cout=1'b0;end
3'b001:begin sum=1'b1;cout=1'b0;end
3'b010:begin sum=1'b1;cout=1'b0;end
3'b011:begin sum=1'b0;cout=1'b1;end
3'b100:begin sum=1'b1;cout=1'b0;end
3'b101:begin sum=1'b0;cout=1'b1;end
3'b110:begin sum=1'b0;cout=1'b1;end
default:begin sum=1'b1;cout=1'b1;end
endcase
end
endmodule
-----------------------------------------------------------------------------------------------VHDL code for FULL ADDER (Structural description)
--TOP LEVEL MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( a,b,cin : in std_logic;
sum,cout : out std_logic);
end full_adder;
architecture structural of full_adder is
component xorg
port(x,y,z:in std_logic;
w: out std_logic);
end component;
component andg
port(x,y:in std_logic;
z: out std_logic);
end component;
component org
port(x,y,z:in std_logic;
c: out std_logic);
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end component;
signal s1,s2,s3:std_logic;
begin
u0:xorg port map(a,b,cin,sum);
u1:andg port map(a,b,s1);
u2:andg port map(b,cin,s2);
u3:andg port map(cin,a,s3);
u4:org port map(s1,s2,s3,cout);
end structural;
-----------------------------------------------------------------------------------------------------------------------------------------------------------------

--LOW LEVEL MODULE-library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity andg is
Port ( x,y : in std_logic;
z : out std_logic);
end andg;
architecture Behavioral of andg is
begin
z<=x and y;
end Behavioral;
-----------------------------------------------------------------------------------------------LOW LEVEL MODULE-library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity org is
Port ( x,y,z : in std_logic;
c: out std_logic);
end org;
architecture Behavioral of org is
begin
c<=x or y or z;
end Behavioral;
----------------------------------------------------------------------------------------------LOW LEVEL MODULE-library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor3 is
Port ( x,y,z : in std_logic;
w : out std_logic);
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end xor3;
architecture Behavioral of xor3 is
begin
sum<=a xor b xor cin;
end Behavioral;
---------------------------------------------------------------------------------------------//Verilog code for FULL ADDER (Structural description)
//Top level Module
module fulladderstru(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
xorg f1 (a,b,cin,sum);
andg f2 (a,b,s1);
andg f3 (b,cin,s2);
andg f4 (a,cin,s3);
org f5 (s1,s2,s3,cout);
endmodule
---------------------------------------------------------------------------------------------------------------------------------------------

//Low level module of xor gate

module xorg(a,b,c,z);
input a;
input b;
input c;
output z;
reg z;
assign z=a ^ b^c;
endmodule
---------------------------------------------------------------------------------------------//Low level module of and gate
module andg(m,n,o);
input m;
input n;
output o;
assign o=m & n;
endmodule
---------------------------------------------------------------------------------------------//Low level module of 3-input OR gate
module org(w,x,y,t);
input w;
input x;
input y;
output t;
assign t=w| x|y;
endmodule
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RESULTS:

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EXPERIMENT 4: ALU
AIM:

Write a model for 8-bit ALU using schematic diagram shown below

THEORY: The arithmetic logic unit (ALU) is a digital circuit that calculates
an arithmetic operation (like an addition, subtraction, etc.) and logic
operations (like XOR, AND, NOT etc.,) between two numbers. The ALU is a
fundamental building block of the central processing unit of a computer.
Many types of electronic circuits need to perform some type of
arithmetic operation, so even the circuit inside a digital watch will have a
tiny ALU that keeps adding 1 to the current time, and keeps checking if it
should beep the timer, etc...
BLOCK DIAGRAM:

7:0

7:0

7:0

Output

8-BIT
ALU
Op

2:0

Enb

TRUTH TABLE:

Inputs
Opcode
Op(2) Op(1) Op(0)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

ACIT, BANGALORE

Outputs
ALU Operation
A+B
AB
Complement A
AxB
A AND B
A OR B
A NAND B
A XOR B

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--VHDL code for 8-bit ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port ( a,b : in std_logic_vector(7 downto 0);
en : in std_logic;
op : in std_logic_vector(2 downto 0);
outp1 : out std_logic_vector(7 downto 0);
outp2 : out std_logic_vector(15 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(a,b,en,op)
begin
if (en='0') then
outp1<= (others=>Z);
outp2<= (others=>Z);
else
case op is
when "000"=> outp1 <=(a + b);
when "001"=>outp1<=(a - b);
when "010"=>outp1<= not a ;
when "011"=>outp2<=(a * b);
when "100"=>outp1<=(a and b);
when "101"=>outp1<=(a or b);
when "110"=>outp1<=(a nand b);
when "111"=>outp1<=(a xor b);
when others=>null;
end case;
end if;
end process;
end Behavioral;
----------------------------------------------------------------------------------------------Verilog code for 8-bit ALU
module alu(a,b,en,op,result);
input [7:0]a,b;
input en;
input [2:0]op;
output [7:0] result;
reg [7:0] result;
always @(a,b,en,op)
begin
if(en==0)
result=7'bx;
else
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case (op)
3'b000: result=a+b;
3'b001:result=a-b;
3'b010: result= ~(a);
3'b011: result= a * b;
3'b100: result= a & b;
3'b101: result=a|b;
3'b110: result = ~(a & b);
3'b111: result = a^b;
default: result = 7'b00000000;
endcase
end
endmodule
RESULTS:

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EXPERIMENT 5:REALIZATION OF SR, D, JK & T FLIP-FLOPS.

i). SR flip-flop
AIM:

Develop the VHDL code for SR flip-flop.

THEORY: The basic flip-flop is an asynchronous sequential circuit. The RS

flip-flop consists of a basic NOR flip-flop and two AND gates. The outputs of
the two NAND gates remain at 0 as long as the clock pulse is 0, regardless
of the S and R input values.
When the clock pulse goes to 1, the information from the S and R inputs is
allowed to reach the basic flip-flop. The set state is reached with with S = 1
and R = 0 and Clock pulse = 1. To change it to clear state the inputs must
be S = 0, R = 1 and Clock pulse = 1. When both S = R = 1, the occurrence of
the clock pulse causes both outputs to go to 0.
BLOCK DIAGRAM:
S

SR
Flip Flop

Clk

qb

Reset

TRUTH TABLE:
Inputs

Outputs

reset clk

qb

No
change
0
1

Forbidden

--VHDL code for SR flip-flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rsff is
Port ( r,s,reset,clk : in std_logic;
q,qb : out std_logic);
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end rsff;
architecture Behavioral of rsff is
signal p:std_logic:='0';
begin
process(clk,reset,s,r)
begin
if(reset='1') then
p<='0';
elsif (rising_edge(clk)) then
if (s='0' and r='0')then
p<=p;
elsif (s='0' and r='1')then
p<='0';
elsif(s='1' and r='0')then
p<='1';
else
p<='Z';
end if;
end if;
end process;
q<=p;
qb<=not p;
end Behavioral;
-----------------------------------------------------------------------------------------------Verilog code for SR flip-flop
module srff(clk,reset,s,r,q,qb);
input sclk,s,r,reset;
output q,qb;
reg q=1'b0;
reg qb=1'b1;
always @(posedge clk)
begin
if(reset==1)
begin
q=1'b0;
qb=~q;
end
else
begin
case ({s,r})
2'b00: q=q;
2'b01: q=1'b0;
2'b10: q=1'b1;
2'b11: q=1'bz;
endcase
qb=~q;
end
end
endmodule
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ii). D flip-flop
AIM:

Develop the VHDL code for D flip-flop.

THEORY: A flip-flop is a binary cell capable of storing one bit of information.

A flip-flop circuit has two outputs, one for the normal value and one for the
compliment of bit stored in it. A flip-flop circuit can maintain a binary state
indefinitely until directed by an input signal to switch states. The major
difference between various flip-flops is in number of inputs they possess and
in the manner in which the inputs affect the binary state.
The D flip-flop receives the designation from its ability to transfer data into a
flip-flop. Its basically an RS flip-flop with an inverter in the R input. This
type of flip-flop sometimes called as D- latch.
BLOCK DIAGRAM:
q

D
Flip Flop

Clk

qb

Reset

TRUTH TABLE:
Inputs
reset clk
1

Outputs
d q
qb
X 0
1
0 0
1
1 1
0

--VHDL code for D flip-flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d,reset,clk : in std_logic;
q,qb : out std_logic);
end dff;
architecture Behavioral of dff is
signal p:std_logic;
begin

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process(clk,reset)
begin
if(reset='1') then
p<='0';
elsif (rising_edge(clk))then
p<=d;
end if;
end process;
q<=p;
qb<=not p;
end Behavioral;
-----------------------------------------------------------------------------------------------Verilog code for D flip-flop
module dff(clk,reset,d,q,qb);
input clk,d,reset;
output q, qb;
reg q=1'b0;
reg qb=1'b1;
always @(posedge clk)
begin
if(reset= =1)
begin
q=1'b0;
qb=~q;
end
else
begin
q=d;
qb=~q;
end
end
endmodule

RESULTS:

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iii). JK flip-flop.
AIM:

Develop the VHDL code for J K flip-flop.

THEORY: A JK flip-flop is a refinement of the RS flip-flop in that the

indeterminate state of the RS flip-flop is defined in the JK flip-flop. Inputs J
and K behave like inputs S and R to set and clear the flip-flop. The JK flipflop behaves like an RS flip-flop except when both J and K are equal to 1.
When both J and K are 1, the clock pulse is transmitted through one AND
gate only-the one whose Q=1, the output of upper AND gate becomes 1,
upon application of clock pulse, and the flip-flop is cleared. If Q is 1, the
output of lower AND gate becomes a 1, and the flip-flop is set.
BLOCK DIAGRAM:
J

JK
Flip Flop

Clk

qb

Reset

TRUTH TABLE:
Inputs

Outputs

reset clk

qb

No
change
0
1

Toggle

--VHDL code for JK flip-flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( j,k,reset,sclk : in std_logic;
q,qb : out std_logic);
end jkff;
architecture Behavioral of jkff is
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signal p:std_logic:='0';
begin
process(clk,reset,j,k)
begin
if(reset='1') then
p<='0';
elsif (rising_edge(clk)) then
if(j='0' and k='0') then
p<=p;
elsif (j='1' and k='0') then
p<='1';
elsif (j='0' and k='1') then
p<='0';
elsif (j='1' and k='1') then
p<=not p;
end if;
end if;
end process;
q<=p;
qb<=not p;
end Behavioral;
-----------------------------------------------------------------------------------------------Verilog code for JK flip-flop
module jkff(clk,reset,j,k,q,qb);
input clk,j,k,reset;
output q,qb;
reg q=1'b0;
reg qb=1'b1;
always @(posedge clk)
begin
if(reset==1)
begin
q=1'b0;
qb=~q;
end
else
begin
case ({j,k})
2'b00: q=q;
2'b01: q=1'b0;
2'b10: q=1'b1;
2'b11: q=~q;
endcase
qb=~q;
end
end
endmodule
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RESULT:
iv). T flip-flop
AIM:

Develop the VHDL code for T flip-flop.

THEORY: The T flip-flop is a single input version of the JK flip-flop. The T

flip-flop is obtained from JK flip-flop if both the inputs are tied together. The
designation T comes from the ability of the flip-flop to toggle. Regardless of
the present state, it assumes the complement state when the clock pulse
occurs while input T is logic is 1.
BLOCK DIAGRAM:
q

T
Flip Flop

Clk

qb

Reset

TRUTH TABLE:
Inputs
reset clk
1

Outputs
t
q
X
0
0
q
1
~q

--VHDL code for T flip-flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t,reset,clk : in std_logic;
q,qb : out std_logic);
end tff;
architecture Behavioral of tff is
signal p:std_logic:='0';
begin
process(clk,reset,t)
begin
if (reset='1') then
p<='0';
elsif (rising_edge(clk)) then
if(t='1') then
p<= not p;
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else
p<=p;
end if;
end if;
end process;
q<=p;
qb<=not p;
end Behavioral;
-----------------------------------------------------------------------------------------------Verilog code for T flip-flop
module tff(clk,reset,t,q,qb);
input clk,t,reset;
output q,qb;
reg q=1'b0;
reg qb=1'b1;
always @(posedge clk)
begin
if(reset= =1)
begin
q=1'b0;
qb=~q;
end
else
if(t= =1)
begin
q=~q;
qb=~q;
end
else
begin
q=q;
qb=~q;
end
end
endmodule
RESULTS:

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EXPERIMENT 6: DESIGN OF FOUR BIT BINARY & BCD COUNTERS

i). 4-bit BCD Counter
AIM: Design a 4-bit BCD COUNTER with synchronous reset and
asynchronous reset.
THEORY: A counter is a register capable of counting the number of clock
pulses arriving at its clock input. There are two types of counters,
synchronous and asynchronous. In synchronous counter the common clock
input is used to connect all the flip-flops and they are clocked
simultaneously. In Asynchronous counters the external clock pulse clocks
the first flip-flop and then each successive flip-flop is clocked by the output
of previous flip-flop.
BCD stands for Binary Coded Decimal. A BCD counter has four
outputs usually labeled A, B, C, D. By convention A is the least significant
bit, or LSB. In other words, the counter outputs follow a binary sequence
representing the decimal numbers 0-9.... this is why its called as binary
coded decimal counter.
BLOCK DIAGRAM:
ud
Clk

4-bit
BCD
Counter

3:0

Reset

TRUTH TABLE:
Inputs
reset clk
1

ACIT, BANGALORE

ud
X
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0

q(3)
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0

Outputs
q(2) q(1)
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
0

Remarks
q(0)
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1

ud=1 BCD
Up Count

ud=0 BCD
Down Count

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0

--VHDL code for 4-bit BCD COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdcounter is
Port ( clk,reset,ud : in std_logic;
q : out std_logic_vector(3 downto 0));
end bcdcounter;
architecture Behavioral of bcdcounter is
signal p:std_logic_vector(3 downto 0):="0000";
signal clkdiv:std_logic_vector(3 downto 0):= "0000";
begin
process(clk)
begin
if(rising_edge(clk))then
clkdiv<=clkdiv+1;
end if;
end process;
process(clkdiv(3),reset,ud)
begin
if(reset='1')then
p<="0000";
elsif (rising_edge(clkdiv(3))) then
if (ud='1') then
if(p="1001") then
p<="0000";
else
p<=p+1;
end if;
elsif (ud='0')then
if(p="0000") then
p<="1001";
else
p<=p-1;
end if;
end if;
end if;
end process;
q<=p;
end Behavioral;
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-----------------------------------------------------------------------------------------------Verilog code for 4-bit BCD COUNTER

module bcdcounter(clk,ud,reset,q);
input clk,ud,reset;
output [3:0]q;
reg [3:0] q=4'b0000;
reg [3:0] clkdiv=4'b0000;
always @(posedge clk)
begin
clkdiv=clkdiv+1;
end
always @(posedge clkdiv(3))
begin
if(reset==1)
q=4'b0000;
else if(ud==1)
if(q==4'b1001)
q=4'b0000;
else
q=q+1;
else if(ud==0)
if(q==4'b0000)
q=4'b1001;
else
q=q-1;
end
endmodule
-----------------------------------------------------------------------------------------------VHDL code for 4-bit BCD UP COUNTER with asynchronous Reset.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity asbcdcounter is
Port ( clk,reset: in std_logic;
q : out std_logic_vector(3 downto 0));
end asbcdcounter;
architecture Behavioral of asbcdcounter is
signal count:std_logic_vector(3 downto 0):="0000";
process(clk,reset)
begin
if(reset='1')then
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count<="0000";
elsif (rising_edge(clk)) then
if (count="1001") then
count<="0000";
else
count<=count+1;
end if;
end if;
end process;
q<=count;
end Behavioral;
----------------------------------------------------------------------------------------------Verilog code for 4-bit BCD UP COUNTER WITH ASYNCHRONOUS RESET
module bcdc(clk,reset,q);
input reset;
output [3:0]q;
reg [3:0] q=4'b0000;
always @(posedge clk or posedge reset)
begin
if(reset==1)
q=4'b0000;
else
if(q==4'b1001)
q=4'b0000;
else
q=q +1;
end
endmodule
-----------------------------------------------------------------------------------------------VHDL code for 4-bit BCD COUNTER with synchronous Reset.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sbcdcounter is
Port ( clk,reset: in std_logic;
q : out std_logic_vector(3 downto 0));
end sbcdcounter;
architecture Behavioral of sbcdcounter is
signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk,reset)
begin
if(rising_edge(clk)) then
if(reset='1')then
count<="0000";
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else
count<=count+1;
end if;
if(count="1001") then
count<="0000";
end if;
end if;
end process;
q<=count;
end Behavioral;
-----------------------------------------------------------------------------------------------Verilog code for 4-bit BCD UP COUNTER WITH SYNCHRONOUS RESET
module bcdc(clk,reset,q);
input reset;
output [3:0]q;
reg [3:0] q=4'b0000;
always @(posedge clk)
begin
if(reset==1)
q=4'b0000;
else
if(q==4'b1001)
q=4'b0000;
else
q=q +1;
end
endmodule

RESULT: i) Asynchronous BCD COUNTER

ii) Synchronous BCD COUNTER

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ii). BINARY COUNTER

AIM:

Design a 4-bit BINARY COUNTER with synchronous reset and

Asynchronous Reset.

THEORY: Binary counters are the simplest form of counters. An N-bit binary
counter counts from 0 to (2N - 1) and back to 0 again. A binary counter can
be constructed from J-K flip-flops by taking the output of one cell to the
clock input of the next. The J and K inputs of each flip-flop are set to 1 to
produce a toggle at each cycle of the clock input. For each two toggles of the
first cell, a toggle is produced in the second cell, and so on down to the
fourth cell. This produces a binary number equal to the number of cycles of
the input clock signal. This device is sometimes called a "ripple through"
counter
BLOCK DIAGRAM:

ud

4-bit
BCD
Counter

Clk

3:0

Reset

TRUTH TABLE:
Inputs
reset
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

clk

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Remarks

Outputs
ud
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

q(3)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

q(2)
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

q(1)
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

q(0)
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

ud=1 Binary
Up Count

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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

ud=0 Binary
Down Count

--VHDL code for 4-bit BINARY COUNTER with synchronous Reset.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_counter is
Port ( clk,reset,ud : in std_logic;
q : out std_logic_vector(3 downto 0));
end bin_counter;
architecture Behavioral of bin_counter is
signal p:std_logic_vector(3 downto 0):="0000";
begin
process(clk,reset,ud)
begin
if (rising_edge(clk)) then
if(reset='1')then
p<="0000";
elsif (ud='1') then
p<=p+1;
else
p<=p-1;
end if;
end if;
end process;
q<=p;
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end Behavioral;
--Verilog code for 4-bit BINARY COUNTER
module bincounter(clk,ud,reset,q);
input sclk,ud,reset;
output [3:0]q;
reg [3:0]q=4'b0000;
always @(posedge clk)
begin
if(reset==1)
q=4'b0000;
else
if(ud==1)
q=q+1;
else if(ud==0)
q=q-1;
end
endmodule
-----------------------------------------------------------------------------------------------VHDL code for 4-bit BINARY COUNTER with Asynchronous Reset.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity asbin_counter is
Port ( clk,reset: in std_logic;
q : out std_logic_vector(3 downto 0));
end asbin_counter;
architecture Behavioral of asbin_counter is
signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk,reset)
begin
if(reset='1')then
count<="0000";
elsif(rising_edge(clk)) then
count<=count+1;
end if;
end process;
q<=count;
end Behavioral;
-----------------------------------------------------------------------------------------------Verilog code for 4-bit BINARY COUNTER WITH ASYNCHRONOUS RESET
module binc(clk,reset,q);
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input reset;
output [3:0]q;
reg [3:0]q;
always @(posedge clk)
begin
if(reset==1)
q=4'b0000;
else
q=q+1;
end
endmodule
---------------------------------------------------------------------------------------------RESULTS: i) Asynchronous BINARY COUNTER
ii) Synchronous BINARY COUNTER

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INTERFACING EXPERIMENTS
EXPERIMENT1: SEVEN-SEGMENT DISPLAY
AIM: Write the VHDL code to display 0 9 and A F on the given seven
segment display
THEORY: 7-Segment display can display the digits 0-9 and the hex
extension (A-F). A signal-character displays bring out leads for 7-segments &
the common elect code (Common cathode & common anode). Here in
FPGA/CPLD board to interface one 7-segment LED display whose elements
are connected to any I/O pins of the FPGA/CPLD.
Here we can consider common- cathode7-segment LED displays. The
user can then ON by driving associated signal high.
Along with the seven segment data outputs led the position of the display
can be controlled by the position control lines cntl .
cntl = 1110 display at position 1
cntl =1101 display at position 2
cntl=1011 display at position 3
cntl =0111 display at position 4
SEVEN SEGMENT LED DISPLAY DIAGRAM:

Seven Segment display are of 2 types:

a. Common Anode type
0 indicates segment ON
1 indicates segment OFF
b. Common Anode type
1 indicates segment ON
0 indicates segment OFF
BLOCK DIAGRAM:

FPGA
XC3S400
Device

FRC5
6:0

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TRUTH TABLE:
Inputs
bcd(3)bcd(2)bcd(1)bcd(0)

Outputs
led(6) led(5) led(4) led(3) led(2) led(1) led(0)
a
b
c
d
e
f
g

Segment
output

--seven segment display-library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd2_7seg is
Port ( bcd : in bit_vector(3 downto 0);
cntl:out bit_vector(3 downto 0);
led: out bit_vector(6 downto 0));
end bcd2_7seg;
architecture Behavioral of bcd2_7seg is
begin
cntl<=1110;
process(bcd)
begin
case bcd is
when "0000"=>led<="1111110";
when "0001"=>led<="0110000";
when "0010"=>led<="1101101";
when "0011"=>led<="1111001";
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when "0100"=>led<="0110011";
when "0101"=>led<="1011011";
when "0110"=>led<="1011111";
when "0111"=>led<="1110000";
when "1000"=>led<="1111111";
when "1001"=>led<="1111011";
when others=>led<="0000000";
end case;
end process;
end Behavioral;
PIN CONFIGURATION:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET

"bcd<0>" LOC = "p74" ;

"bcd<1>" LOC = "p76" ;
"bcd<2>" LOC = "p77" ;
"bcd<3>" LOC = "p79" ;
cntl<0> LOC= "p23" ;
cntl<1> LOC= "p24" ;
cntl<2> LOC= "p26" ;
cntl<3> LOC= "p27" ;
"led<0>" LOC = "p18" ;
"led<1>" LOC = "p17" ;
"led<2>" LOC = "p15" ;
"led<3>" LOC = "p14" ;
"led<4>" LOC = "p13" ;
"led<5>" LOC = "p12" ;
"led<6>" LOC = "p1" ;

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EXPERIMENT2: EXTERNAL LIGHT CONTROL USING RELAYS

AIM: Write the VHDL code to control external lights using relays
THEORY:
The basic function of the relay is switching of a load circuit is
controlled by a low power, electrically isolated input signal. In
Electromechanical Relays (EMRs) has been the component of choice, largely
due to price, function, and availability. An input voltage is applied to the coil
mechanism. The input voltage magnetizes the core, which pulls the arm
towards it. This action causes the output contacts to touch, closing the load
circuit. When the input voltage is removed, the spring lever will push the
contacts away from each other, breaking the load circuit connection. LED is
connected as load to the relay in this case.
BLOCK DIAGRAM:
FPGA
XC3S400
Device

Relay Module

Cntl1
Cntl2

Output

LED

FRC9

--VHDL code for EXTERNAL LIGHT CONTROL USING RELAYS-library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity extlight is
Port (cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;
architecture Behavioral of extlight is
begin
light<= cntrl1 OR cntrl2 ;
end Behavioral;
Procedure:
1. Make the connection between FRC9 of the FPGA board to the External
light connector
2. Make the connection between FRC1 of the FPGA board to the Dip
switch
PIN CONFIGURATION:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET cntrl1 LOC = p74 ;
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NET cntrl2 LOC = p76 ;

NET light LOC = p5;
EXPERIMENT3: STEPPER MOTOR
AIM: Write the VHDL code to control speed and direction of stepper Motor
THEORY: Stepper motors are electromechanical devices, which convert a
digital pulses in mechanical rotation, that provide accurate incremental
rotation. The most common stepper motor uses four windings for a fourphase operation. A typical four-phase motor driving circuit is shown in
Figure using an FPGA to generate the sequence logic. The clock (CLK) input
synchronizes the logic and determines the speed of rotation. The motor
advances one step per clock period; the angle of rotation of the shaft will
depend on the particular motor. To determine the clock period, consider that
the stepper motor torque increases as frequency decreases. The direction
(DIR) control input changes the sequence at the outputs (PH1 to PH4) to
reverse the motor direction.
BLOCK DIAGRAM:

Coil B
FPGA
XC3S400
Device

Coil A

Coil C

FRC9

Coil D
Coil D

Stepper Motor switching sequence:

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0
0
1
1
1
1
0
0

0
1
1
0
0
1
1
0

1
1
0
0
0
0
1
1

1
0
0
1
1
0
0
1

Motor
Direction
Anti Clock
wise

Clock wise

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--VHDL code for stepper motor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STEPPER is
Port (dout : out std_logic_vector (3 downto 0);
row: in std_logic_vector (1 downto 0);
clk, reset, dir: in std_logic);
end STEPPER;
architecture Behavioral of STEPPER is
signal clk_div : std_logic_vector(25 downto 0);
signal clk_int: std_logic;
signal shift_reg : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div + '1';
end if;
end process;
clk_int <= clk_div(21) when row=00 else
clk_div(19) when row=01 else
clk_div(17) when row= 10 else
clk_div(15);

NET
NET
NET
NET
NET
NET
NET
NET
NET

UCF File:
dir LOC = p74 ;
rst LOC = p76 ;
row(0) LOC = p77 ;
row(1) LOC = p79 ;
clk LOC = p52;
dout(0) LOC = p5 ;
dout(1) LOC = p4 ;
dout(2) LOC = p2 ;
dout(3) LOC = p141 ;

(less speed)

(more speed)

process (reset,clk_int)
begin
if reset='0' then
shift_reg <= "1001";
elsif rising_edge (clk_int) then
if dir=0 then
shift_reg <= shift_reg(0) & shift_reg (3 downto 1); ----clockwise
else
shift_reg <= shift_reg (2 downto 0) & shift_reg (3); ---- anticlockwise
end if;
end if;
end process;
dout <= shift_reg;
end Behavioral;
Procedure:

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1. Make the connection between FRC9 of the FPGA board to the Stepper
motor
2. Make the connection between FRC1 of the FPGA board to the Dip switch
EXPERIMENT 4: D C MOTOR INTERFACE
AIM: Write VHDL code to control the DC motor.
BLOCK DIAGRAM:
FPGA
XC3S400
Device

FRC9

ULN2803A
Motor
Driver

+
M
-

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dcmotor is
Generic (bits : integer := 8 ); -- number of bits used for duty cycle.
port ( clk: in std_logic; -- 4 MHz clock
reset,dir: in std_logic; -- master reset pin
pwm : out std_logic_vector (1 downto 0);
rly: out std_logic;
row: in std_logic_vector (0 to 3) ); -- this are the row lines
end dcmotor;
architecture dcmotor1 of dcmotor is
signal counter : std_logic_vector(bits - 1 downto 0):="11111110";
signal DIV_REG: std_logic_vector (16 downto 0); -- clock divide register
signal DDCLK, tick: std_logic; -- this has the divided clock.
signal duty_cycle: integer range 0 to 255;
signal ROW1 : std_logic_vector(0 to 3); -- this are the row lines
begin
-- select the appropriate lines for setting frequency
process (clk) -- clock divider
begin
if (clk' event and clk='1') then
DIV_REG <= DIV_REG + 1;
end if;
end process;
DDCLK<=DIV_REG(12);
tick <= row(0) and row(1) and row(2) and row(3);

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process (tick)
begin
if falling_edge(tick) then
case row is
when "1110" => duty_cycle <= 255 ;
when "1101" => duty_cycle <= 200 ;
when "1011" => duty_cycle <= 150 ;
when "0111" => duty_cycle <= 100 ;
when others => duty_cycle <= 100;
end case;
end if;
end process;

--motor
--motor
--motor
--motor

speed
speed
speed
speed

1 (less speed)
2
3
4 (high speed)

process (DDCLK, reset)

begin
if reset = '0' then
counter <= (others => '0');
pwm<="01";
elsif (DDCLK'event and DDCLK = '1') then
counter <= counter + 1;
if counter >= duty_cycle then
pwm(1) <= '0';
else
UCF File:
pwm(1) <= '1';
NET dir LOC = p74 ;
end if;
NET reset LOC = p76 ;
end if;
NET clk LOC = p52;
end process;
process(dir)
begin
if(dir='1') then rly<='1';
else
rly<='0';
end if ;
end process;

NET
NET
NET
NET
NET
NET
NET

row(0) LOC = p57 ;

row(1) LOC = p59 ;
row(2) LOC = p63 ;
row(3) LOC = p69 ;
pwm(0) LOC = p4 ;
pwm(1) LOC = p141 ;
rly LOC = p2 ;

end dcmotor1
Procedure:
1. Make the connection between FRC9 of the FPGA board to the DC
motor
2. Make the connection between FRC7 of the FPGA board to the
Keyboard
3. Make the connection between FRC1 of the FPGA board to the Dip
switch

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EXPERIMENT 5: DAC INTERFACE

AIM: Write VHDL code to generate different waveforms using DAC interface
i). Square Waveform
FPGA
XC3S400
Device

FRC5

DAC0808

Analog Output
to CRO

8-bit Digital Data

-VHDL CODE FOR SQUARE WAVE GENERATION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity square_wave is
Port ( clk, rst : in std_logic;
dac_out : out std_logic_vector (0 to 7));
end square_wave;
architecture Behavioral of square_wave is
signal temp : std_logic_vector (3 downto 0);
signal counter : std_logic_vector (0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process (temp(3))
begin
if rst='1' then
counter <= "00000000";

NET
NET
NET
NET
NET
NET
NET
NET
NET
NET

UCF File:
clk LOC = p52 ;
rst LOC = p74 ;
dac_out(0) LOC = p21;
dac_out(1) LOC = p18;
dac_out(2) LOC = p17;
dac_out(3) LOC = p15;
dac_out(4) LOC = p14;
dac_out(5) LOC = p13;
dac_out(6) LOC = p12;
dac_out(7) LOC = p1;

elsif rising_edge (temp(3)) then

if counter<255 and en='0' then
counter <= counter + 1 ;
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en<='0';
dac_out <="00000000";
elsif counter=0 then
en<='0';
else
en<='1';
counter <= counter-1;
dac_out <="11111111";
end if;
end if;
end process;
end Behavioral;
Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC.
2. Make the connection between FRC1 of the FPGA board to the Dip switch
-------------------------------------------------------------------------------------------ii). Ramp Waveform
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ramp_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector (0 to 7));
end ramp_wave;
architecture Behavioral of ramp_wave is
signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge (clk) then
temp <= temp + '1' ;
end if;
end process;

NET
NET
NET
NET
process (temp(3))
NET
begin
NET
if rst='1' then
NET
counter <= "00000000";
NET
elsif rising_edge(temp(3)) then NET
counter <= counter + 15 ;
NET

UCF File:
clk LOC = p52 ;
rst LOC = p74 ;
dac_out(0) LOC = p21;
dac_out(1) LOC = p18;
dac_out(2) LOC = p17;
dac_out(3) LOC = p15;
dac_out(4) LOC = p14;
dac_out(5) LOC = p13;
dac_out(6) LOC = p12;
dac_out(7) LOC = p1;

end if;
end process;
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dac_out <=counter;
end Behavioral;
iii). Triangle waveform
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangular_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end triangular_wave ;
architecture Behavioral of triangular_wave is
signal counter : std_logic_vector (0 to 8);
signal temp : std_logic_vector(3 downto 0);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;

NET
NET
NET
NET
NET
NET
NET
NET
NET
NET

UCF File:
clk LOC = p52 ;
rst LOC = p74 ;
dac_out(0) LOC = p21;
dac_out(1) LOC = p18;
dac_out(2) LOC = p17;
dac_out(3) LOC = p15;
dac_out(4) LOC = p14;
dac_out(5) LOC = p13;
dac_out(6) LOC = p12;
dac_out(7) LOC = p1;

process(temp(3))
begin
if rst='1' then
counter <= "000000000";
elsif rising_edge(temp(3)) then
counter <= counter + 1 ;
if counter(0)='1' then
dac_out <=counter (1 to 8);
else
dac_out <=not(counter(1 to 8));
end if;
end if;
end process;
end Behavioral;

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iv). Sine waveform

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sinewave is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dac_out : out STD_LOGIC_VECTOR (0 to 7));
end sinewave;
architecture Behavioral of sinewave is
signal temp: std_logic_vector (7 downto 0);
signal i: integer range 0 to 179;
type sine is array (0 to 179) of integer range 0 to 255;
constant value :sine :=(128,132,1360,.136,132,128);
begin
process (clk)
begin
if rising_edge (clk) then
temp<=temp+'1';
end if;
end process;

NET
NET
NET
NET
NET
NET
NET
NET
NET
NET

UCF File:
clk LOC = p52 ;
rst LOC = p74 ;
dac_out(0) LOC = p21;
dac_out(1) LOC = p18;
dac_out(2) LOC = p17;
dac_out(3) LOC = p15;
dac_out(4) LOC = p14;
dac_out(5) LOC = p13;
dac_out(6) LOC = p12;
dac_out(7) LOC = p1;

process (temp(7))
begin
if rst='1' then
dac_out<="00000000";
elsif rising_edge (temp(7)) then
dac_out<= conv_std_logic_vector (value(i),8);
i<=i+1;
if (i=179) then
i<=0;
end if;
end if;
end process;
end Behavioral;

NOTE:
Calculate different degree values from 0o to 360o using the formula given by
with a samples of 2o ->
Vout = (5 + 5Sin ) x (256/10)
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EXPERIMENT 6: ELEVATOR OPERATION

AIM: Write VHDL code to simulate elevator operations
THEORY:
An elevator is a transport device used to move goods or people
vertically. Outside North America, elevators are known more commonly as
lifts. The elevator algorithm, a simple algorithm by which a single elevator
can decide where to stop, is summarized as follows:
Continue traveling in the same direction while there are remaining requests
in that same direction.
If there are no further requests in that direction, then stop and become idle,
or change
Direction if there are requests in the opposite direction.

--VHDL code for elevator operations

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K : in std_logic);
end ELE;
architecture behavioral of ELE is
signal
signal
signal
signal
signal
signal
signal

scurflr,snxtflr,skeyflr : integer range 0 to 15;

sdir, skeyhit : std_logic;
skeyscn : std_logic_vector(3 downto 0);
lkeyscn : std_logic_vector(3 downto 0);
lkeyret : std_logic_vector(3 downto 0);
sclkdiv : std_logic_vector(15 downto 0);
sflrclk,skeyclk : std_logic;

begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" =>
when "1101" =>
when "1011" =>
when "0111" =>
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skeyhit
skeyhit
skeyhit
skeyhit

<=
<=
<=
<=

'1';
'1';
'1';
'1';
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when others => skeyhit <= '0';

end case;
end process;
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;
-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyflr <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyflr <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyflr <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyflr <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
then skeyflr <= 4;
elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyflr <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyflr <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyflr <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyflr <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")
then skeyflr <= 9;
elsif(lkeyscn = "1011" and lkeyret = "1011")
then skeyflr <= 10;
elsif(lkeyscn = "1011" and lkeyret = "0111")
then skeyflr <= 11;
elsif(lkeyscn = "0111" and lkeyret = "1110")
then skeyflr <= 12;
elsif(lkeyscn = "0111" and lkeyret = "1101")
then skeyflr <= 13;
elsif(lkeyscn = "0111" and lkeyret = "1011")
then skeyflr <= 14;
elsif(lkeyscn = "0111" and lkeyret = "0111")
then skeyflr <= 15;
end if;
end if;
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end process;

-- process clk divider

-process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
skeyclk <= sclkdiv(6);
sflrclk <= sclkdiv(15);
end process;
-- process for key scan clkscan
process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
elsif skeyscn = "1011" then skeyscn <= "0111";
elsif skeyscn = "0111" then skeyscn <= "1110";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;
-- process floor motion
process(sflrclk)
begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;
end if;
end if;
end if;
end process;
-- process display 7seg
process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101
","0000111","1111111","1101111","1110111","1111100","1011000","101111
0","1111001","1110001");
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
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end process;
end behavioral;
TROUBLE SHOOTING
A. Syntax errors:
1. # ** Error: prog1_a.vhdl(9): near "out": expecting: ':'
Reason: c out std_logic_vector(7 downto 0));
Missing colon (:) between c & out.
2. # ** Error: prog1_a.vhdl(10): near "end": expecting: IDENTIFIER
Reason: c : out std_logic_vector(7 downto 0) ;
Bracket is missing ( ) )
3. Errors due to invalid identifier
i) # ** Error: prog1_a.vhdl(6): near "1": expecting: IDENTIFIER
Entity 1logicgates is
Reason :In the above line name of the entity is started with number (1)
Note: name of the entity should not start with numbers.
ii) # ** Error: prog1_a.vhdl(6): near "logic_ _gates":
contain
Adjacent underscores.

Identifier may not

Entity logic_ _gates is

Reason :In the above line name of the entity contains adjacent underscores.
Note:
i) Name of the entity should not contains adjacent underscores and also
space in
Between (ex. Logic gates)

4. # ** Error: (vcom-11) could not find work.logicgate.

entity logicgates is
Port (.
.. );
end logicgates;
architecture Behavioral of logicgate is
begin
.;
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..;
end Behavioral;
Reason: In the above program, the name of the entity is logicgates but in
the architecture
Corresponding identifier used is logicgate
5. # ** Error: prog2_b.vhdl(24): String literal has a character 'z' not in the
enumeration
type std_logic.
else y<="zzz";
Reason: character z is lower case letter.
Note:
To represent the high impedance state always use character Z (upper
case)
6. # ** Error: prog1_a1.vhdl(18): Case statement covers only 8 out of 729
cases.
Case s is
..;
;
when "110"=> c<=(a nor b);
when "111"=> c<=(a xnor b);
end case;
Reason: when others clause is missing after last statement in the case
Note : write the when others clause after last statement in the case
Ex. when "110"=> c<=(a nor b);
OR when "110"=> c<=(a nor b);
when others=> c<=(a xnor b);
when "111"=> c<=(a xnor b);
end case;
when others=> null;
end case;
7. # ** Error: prog1_a.vhdl(15): Cannot assign to signal 'c'.
# ** Error: prog1_a.vhdl(15): Illegal concurrent statement.
c(0) := a and b;
Reason :In the above line, c(0) is the signal but variable assignment
operator(:=)is used
instead of signal assignment operator(<=).
8. # ** Error: prog6_a1.vhdl(13): near "signal": expecting: END
architecture Behavioral of asbcdcounter is
begin
signal count:std_logic_vector(3 downto 0);
signal clkdiv:std_logic_vector(0 to 3);
.;
.;
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end behavior;

Reason: In the above program signals count & clkdiv are declared after the
begin.
Note: always signals are declared before the begin.
9. # ** Error: prog6_a1.vhdl(15): Variable declaration 's' not allowed in this
region.
architecture Behavioral of asbcdcounter is
variable s:integer:=1;
begin
process(.)
begin
;
;
end process;
end behavioral;
Reason: In the above program variable (s) is declared before the begin and
also out
Side the process.
Note: Always variables are declared inside the process.
10. # ** Error: prog2_e1.vhdl(18): Illegal concurrent statement.
# ** Error: prog2_e1.vhdl(22): near "process": expecting: ';'
architecture Behavioral of comp2 is
begin
--process(a,b)
--begin
missing process
l<='0';e<='0';g<='0';
if (a<b)then l<='1';
elsif (a=b)then e<='1';
else g<='1';
end if;
--end process;
end behavioral;
Reason: In the above program process is missing before concurrent
statements.
B.Semantic errors:
1. Label mismatch error
i) # ** Error: prog1_a.vhdl(10): Labels do not match: 'logicgat' and
'logicgates'.
entity logicgat is
Port ( a : in std_logic: b : in std_logic;
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c : out std_logic_vector(7 downto 0));

end logicgates;
Reason: In the above entity, the name of the entity is logicgat but it ends
with
Logicgates.
Note: Always the entity should ends with name of the entity.
ii). # ** Error: prog1_a.vhdl(24): Labels do not match: 'behavioral' and
'behavior'.
architecture Behavioral of logicgates is
begin
.;
..;
end Behavior;
Reason: In the above architecture, the name of the architecture is
Behavioral but it
Ends With Behavior.
Note: Always the architecture should ends with name of the architecture.
2.Error due mismatch of input types
# ** Error: prog1_a.vhdl(15): No feasible entries for infix op: "and".
# ** Error: prog1_a.vhdl(15): Bad right hand side in assignment.
Port ( a : in std_logic;
b : in std_logic_vector(2 downto 0);
c : out std_logic_vector(7 downto 0));
architecture Behavioral of logicgates is
begin
c(0)<= a and b;
..;
End Behavioral;
Reason: In the above program, input a is declared as 1-bit & input b is
declared as 3Bits, hence in the statement c (0)<= a and b; the right-hand side is
not matched.
Note: In any statement, the size of the inputs used is of equal size.

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Model Viva Questions in HDL

1.
What does VHDL stands for?
2.
Which IEEE standard describes the VHDL language?
3.
List the three popular Hardware languages.
4.
Which are the different levels of abstraction that can be specified
using VHDL?
5.
List the different design units of VHDL.
6.
Which are the mandatory design units to write VHDL code?
7.
Which are the different modes of port declaration?
8.
Which are the valid characters for identifier declaration?
9.
Which are the different classes of operators?
10. Where do you write the concurrent statements
11.
Where do you write the sequential statement?
12.
In which model process statement appears?
13.
What is the importance of sensitivity list in process statement?
14. Is VHDL is Case sensitive?
15.
Is VHDL support multi dimensional arrays
16. Is combinational circuits can be code inside the process
17. Is VHDL support operator overloading
18. Is it possible to write multiple entities for a single architecture?
19. Is it possible to write multiple architecture for a single entity?
20.
Where we declare the variable?
21.
Device configuration for CPLD and FPGA Used in your Lab.
22. Expand CPLD and FPGA.
23. Differentiate sequential and concurrent statement.
24. List the different types of wait statements.
25. How you model your program using wait statement.
26. What are the different modeling styles in VHDL?
27. What is the difference between the bit and std_logic
28. What is the difference between the variable, signals?
29. Name the different VHDL objects.
30. Name the different data types used in VHDL.
31. Explain the VHDL term i)Entity ii)Architecture iii)Configuration
iv)package v) driver, vi) process vii) attribute viii) generic ix) bus.
32. Write the general syntax for Case, LOOP, Architecture Configuration
,package process, Exit.
33. Differentiate between Procedure and Function
34. Explain attribute event, range
35. How to detect signal edge using attribute.
36. What is synthesis
37. What is simulation
38. Differentiate between syntax error and semantic error.
39. Is other clause necessary in VHDL case statement, why?
40. What are the i/ps required for synthesis.
41. Which architecture description you preferred, why?
42. Which Tool you used for simulation.
43. Which Tool you used for synthesis.
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44. XC2S100PQ208what 2s stands for, what 100 stands for, what

pq208 stands for
45. What is the difference between CPLD and FPGA?
46. What is the difference between synchronous and asynchronous reset.
47. What is the basic element of memory?
48. What do you mean by latch?
49. How you model latch in VHDL.
50. What is the difference between synchronous and asynchronous
counter.
51. Which signal counter counts
52. What is the difference between backend and front-end?
53. Expand ASIC.
54. Expand JTAG.
55. Expand ISP.
56. Which IEEE standard supports JTAG
57. What information is present in .Bit or .Jed File
58. What do you mean by configuration?
59. Which file used to configure the CPLD
60. Which file used to configure the FPGA

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