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WritingIsolationStrategyinUPF|VLSICOMMUNITY
hhharishhh
Jul 27, 2014
Low
Power
Design
0
Isolation
strategy
is
required
implementation
to
tool
instruct
to
insert
the
PST
state
implementation
table,
tools
the
doesnt
specified.
do
not
Also
provide
the
the
PST
tools
set_isolation
set_isolation
map_isolation_cell
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WritingIsolationStrategyinUPF|VLSICOMMUNITY
determines
the
type
of
suggests
this
strategy
is
By
specifying
the
source
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WritingIsolationStrategyinUPF|VLSICOMMUNITY
domain
is
also
an
in
OFF
state.
The
option
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WritingIsolationStrategyinUPF|VLSICOMMUNITY
option
-elements
can
be
and
fmg/read_ack_out
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WritingIsolationStrategyinUPF|VLSICOMMUNITY
[blockquote align=center]
set_isolation ISO_VDDA_TO_VDDB
-domain VDDA
-source VDDA_SUPPLY
-diff_supply_only TRUE
-isolation_power_net VDDB
-isolation_ground_net VSS
-name_suffix
ISO_LOW_VDDA_TO_VDDB
-clamp_value 0
-elements
fmg/write_req_out
fmg/read_ack_out}
[/blockquote][space_20]
3. Control signals like clocks should
not be routed through relatively less
ON domain than the sinks because
the isolation cell when enabled can
block its propagation. Designer can
explicitly specify tool not to isolate
specific signals using -no_isolation
option
[blockquote align=center]
set_isolation
NOISO_VDDA_TO_VDDB
-domain VDDA
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-no_isolation
-elements {fmg/core_clk}
[/blockquote][space_20]
4. Isolation cell can be forced on a
signal
by
option.
using
When
-force_isolation
the
option
force
isolation
even
when
its
not
command
is
http://www.vlsicommunity.com/2014/07/writingisolationstrategyinupf/
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WritingIsolationStrategyinUPF|VLSICOMMUNITY
[blockquote align=center]
set_isolation_control ISO_VDDA_TO_VDDB
-domain VDDA
-isolation_signal
pwr_ctrlr/iso_enable_vdda_to_vddb
-location parent
-isolation_sense low
[/blockquote][space_20]
In
the
example
we
defined
isolation
the
control
signal pwr_ctrlr/iso_enable_vdda_to_vddb
to
the
already
defined
isolation
The
option
-domain
1801-2013
command
deprecated
standard
set_isolation_control
by
enhancing
the
is
the
low
power
tools
still
set_isolation_control
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command.
Isolation sense together with the
clamp value determines the type of
isolation cell to be used for the
strategy
implementation.
Isolation
cell
is
used
for
the
implementation.
OR style: When the isolation sense is
high and the clamp value is 1 then an
OR gate can be used as an isolation
cell. Hence an OR style isolation cell
is used for the implementation.
The location of the isolation cell
placement (with respect to the power
domains) can be controlled by the
designer using -location. Allowed
values for the option -location in
synopsys tools are self, parent and
fanout.
Self: Tool implements the isolation
cell in power domain that is specified
in the -domain option of the isolation
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strategy.
is
placed
in
each
of
the
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specified
in
the
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