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28202A
SLA7042M AND
SLA7044M
VREF
VCC
6
7
9
10
OUTB
11
GROUND B
12
STROBE B
13
REF/ENABLE B
14
CNTRL SPLY B
15
18
17
D/A
16
OUT B
SR/LATCH
CLOCK B
SERIAL DATA B
CONTROL/LOGIC
SENSE B
VREF VCC
OUT A
SENSE A
GROUND A
CLOCK A
SERIAL DATA A
CONTROL/LOGIC
CNTRL SPLY A
D/A
REF/ENABLE A
SR/LATCH
OUTA
STROBE A
Dwg. PK-008
OUT A/B
11
18
15
V
REF/ENABLE
14
OUT
A/B
DD
ENABLE
+
STROBE
13
DD
D/A
REF
PROGRAMMABLE
PWM OFF TIMER
NOISE FILTER
LATCHES
PHASE
DATA
17
CLOCK
16
SHIFT REG
12
10
GROUND
SENSE
ALLOWABLE PACKAGE
POWER DISSIPATION
Dwg. FK-006
25
20
R JM = 5.0C/W
15
10
R JA = 28C/W
0
25
50
75
100
TEMPERATURE in C
125
150
Dwg. GK-018-1
FET ON Resistance
Symbol
IDSS
Test Conditions
Min
Typ
Max
Units
VDS = 100 V
4.0
mA
800
mV
SLA7044M, IOUT = 3 A
855
mV
0.67
SLA7044M, IOUT = 3 A
0.285
1.2
SLA7044M, IOUT = 3 A
1.6
VDD
Operating
4.5
5.0
5.5
IDD
VDS(ON)
rDS(on)
VSD
7.0
mA
VIN(1)
3.5
VIN(0)
1.5
IIN(1)
VIN(1) = VDD
1.0
IIN(0)
VIN(0) = 0
1.0
0.4
2.5
VDD - 1
VREF/EN
IREF/EN
0 V VREF/EN 5 V
1.0
Step Reference
SRCR
20
40
55.5
Current Ratio
71.4
83
91
100
NOTE: Negative current is defined as coming out of (sourcing) the specified device pin.
TYPICAL AC CHARACTERISTICS at TA = +25C, VDD = 5 V, IOUT = 1 A, Logic Levels are VDD and
Ground
DATA Input = 001X ................................................................. 7 s
DATA Input = 010X ................................................................. 7 s
tr
CLOCK
A
DATA
C
C
STROBE
Dwg. WK-002
Minimum Data Active Time Before Clock Falling Edge (Data Set-Up Time) ...........
Minimum Data Active Time After Clock Falling Edge (Data Hold Time) ..................
Minimum Data Pulse Width ......................................................................................
Minimum Clock Pulse Width ....................................................................................
Minimum Time Between Clock and Strobe Falling Edges .......................................
Minimum Strobe Pulse Width ...................................................................................
150 ns
150 ns
350 ns
350 ns
650 ns
500 ns
APPLICATIONS INFORMATION
The SLA7042M and SLA7044M modules integrate two
CMOS controller ICs and four NMOS FETs. Each half of the
device operates independently, although the CLOCK inputs
may be connected together and the STROBE inputs may be
connected together. Pulling VREF/EN low (<2.5 V) allows the 4bit shift registers to be serially loaded with motor phase and
output currrent ratioing data.
The first bit selects the motor phase (logic high = Output A
or B, logic low = Output A or B); the next three bits determine
the motor current ratio (eight steps, 0% to 100%). The internal
D/A converter, in conjunction with a current-sensing resistor
and input reference voltage, completes the microstepping
current control.
Pulling VREF/EN high (within 1 V of VDD) resets the shift
register and latches to turn the MOS drivers OFF and inhibits
the serial DATA input.
IOUT max
IOUT max
R2
R1 + R2
Vb
3 RS
VREF/EN
3 RS
I OUT
PHASE A
PHASE A
Alternative REFERENCE/ENABLE input configurations provide for more complete motor control. A tri-state
logic element and a voltage divider allows a fixed reference voltage, with both output disable and data enable
functions. Complete P control is usually accomplished
with a D/A converter as shown in Figure 3. Here, digital
control provides an output disable (>VDD - 1 V), VREF, and
VEN (<2.5 V).
Dwg. WK-001
VDD
SERIAL DATA
V BB
B
Vb
TO CHANNEL B
R1
VREF/EN
ENABLE
DATA
D/A
PWM
OFF-TIME
CONTROL
CONTROL
LOGIC
DRIVE
R2
SENSE
RS
Dwg. EK-011
V DD
TO OTHER CHANNEL
(OPTIONAL)
R1
D/A
REF/EN
......
R2
FROM P
111...1 = OFF
000...0 = ENABLE DATA
H = OFF
Z = REFERENCE
L = ENABLE DATA
Dwg. EK-012
There are four bits: the first bit entered controls the
LOAD CURRENT
(NOT TO SCALE)
DISABLED
VDD
VDD - 1 V
MOTOR PWM OPERATION
2.5 V
ENTER
DATA
REFERENCE/ENABLE
0
3.1 s
MIN
VDD
CLOCK
0
VDD
SERIAL DATA
0
DON'T CARE
1 0 0
= 20%
0
DATA LATCHED
0 1 0
= 40%
VDD
STROBE
0
Dwg. WK-003A
2.5
2.0
1.5
1.0
0.5
0
-40
+40
+80
JUNCTION TEMPERATURE in C
+120
+160
Dwg. GK-017
1.22 0.008
0.126
0.006
0.961 0.008
0.189
0.008
0.646
0.067
0.512
0.008
0.390
0.008
0.630
0.004
0.008
0.008
0.096
0.008
0.264
0.020
0.118
1
18
1.232 0.008
+0.008
0.026 0.004
0.022 +0.008
0.004
0.157
0.066
0.028
0.016
Dwg MK-002-18 in
Dimensions in Millimeters
(controlling dimensions)
310.2
3.2
0.15
24.4 0.2
4.8
0.2
16.4 0.2
1.7
13 0.2
9.9 0.2
16 0.2
0.1
2.45
0.2
6.7
0.5
3.0
1
18
0.55 +0.2
0.1
31.3 0.2
+0.2
0.65 0.1
1.68
0.4
4.0
0.7
Dwg. MK-002-18 mm
The products described here are manufactured in Japan by Sanken Electric Co.,
Ltd. for sale by Allegro MicroSystems, Inc.
Sanken Electric Co., Ltd. and Allegro MicroSystems, Inc. reserve the right to
make, from time to time, such departures from the detail specifications as may be
required to permit improvements in the design of their products.
The information included herein is believed to be accurate and reliable.
However, Sanken Electric Co., Ltd. and Allegro MicroSystems, Inc. assume no
responsibility for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.