Design and Implementation of Three Level DC-DC Multiplier

Boost Converter with Resonant Switching

V. Prem Sai Reddy, P.Venkatesh, K. LeelaMadhav, N.Sudhakar
VIT University, Vellore 632014, Tamilnadu, India
ABSTRACT
Now a days demand for electrical power is increasing gradually and conventional energy resources are
depleting day by day. The best alternate choice for conventional energy resources is Renewable energy
sources like solar energy, wind energy etc. But the output of photovoltaic cells and wind mills is less and
Dc in form. A DCDC converter topology is designed. The DCDC multilevel boost converter (MBC) is a
pulse width modulation (PWM)- based DCDC converter, which joins the conventional converter and the
switched capacitor topology to give distinctive yield voltages and a self-adjusted voltage utilizing stand
out driven switch, one inductor, 2N-1diodes and 2N-1 capacitors for a N*MBC. It is proposed to be
utilized as DC connection as a part of uses where a few controlled voltage levels are required with selfadjusting and unidirectional current stream, for example, photovoltaic (PV) or power device era
frameworks with multilevel inverters; every gadget squares one and only voltage level, accomplishing
high-voltage converters with low-voltage gadgets.
KEY WORDS: -MBC, PV, Switched capacitor converter
1. INTRODUCTION
There are numerous down to earth
applications where Switched Mode Power Supply
(SMPS) requires wide transformation proportions,
for example, laser, X-beam frameworks, car,
telecom, UPS, modern frameworks, electrostatic
frameworks, battery-fuelled compact gadgets, and
renewable vitality change frameworks. PV boards
and energy units create a low abundance to dcvoltage that should be helped to somewhere in the
range of hundred volts to encourage matrix tie
inverters [1-3].
That transformer or coupled-inductor-based
topologies are normally utilized [4]. However, it is
likewise realized that there exist a few
inconveniences regarding the utilization of
transformers, for example, size, and weight and
recurrence constraint for the resultant topologies
[5-9].
For the procedure of venture down there are
numerous topologies which uses switched capacitor
and transformer less models which gives high gain.
For venture up case a few models has the blend of
ordinary converters with diode capacitor voltage
multiplier which accomplishes a high voltage gain
which may be unrealistic [10-12].
Essentially, consider Multi-level boost
converter [13] is only mix of conventional
converter with voltage multiplier and controls the

yield voltage by pulse width modulation (PWM),

accomplishing a high efficiency as a result of diode
capacitor mix.
There are various topologies of Voltage
Multiplier circuit. Every circuit having its own
advantages and disadvantages too. The benefit of
this model is all capacitors holds same voltage [14].
Diode
capacitor
voltage
multiplier
cell
unidirectional switched capacitor converters
worked in full charge interchange [15]. Their
primary burden is present waveform among
capacitors has spikes [16-17]. The present for this
situation can be restricted by utilizing parasitic
resistances. Conduction misfortunes in MOSFETs
and capacitors are corresponding to RMS streams
so the spike prompts higher conduction misfortunes
for low.
To conquer that issue thunderous exchanging
can be utilized with sensible size and cost.
Contrasting the capacitor streams and full and nonresounding exchanging the spikes in the capacitor
ebbs and flows can be cut down.
This paper proposes an expanded form of
multiplier support converter taking into account full
exchanging. The proposed converter accomplishes
a high voltage pick up without utilization of high
obligation cycle .
The primary attributes:

(i) Same voltage is blocked by every switching

device.
(ii) Data current is continuous and uses one and
only inductor for storage of energy.
Fig.1 (d) Current passing through capacitors based
upon switching behaviour

S6

S5

C5

2. PROPOSED TOPOLOGY

C4
S4

C2

S3

C3

S2

C1

The main aim of the topology design is by

adding a resonant inductor to an N level DC-DC
Multiplier (N*MBC). Because of resonant Inductor
the spike currents flowing through the switching
devices and capacitors will going to reduce. In this
Designed circuit there is necessary to place one
resonant inductor in order to shape current for all
switches and capacitors without spikes as shown in
the Figure 2(a). This is the only Point for draining
the current among the capacitors during all
switching modes of circuit

L
Vg

S1

Fig 1(a)
S6

S5
C4

C5

S4
S3

C2

S6

C3

S5
S2

C1

S4

L
Vg

S1

C4 C2

C5

S3

C3

Fig 1(b)
S6

Lr

S2

C1

S5

Vg
S4

C4 C2

C5

S3

S1

C3

Fig 2(a).DC-DC Multiplier Using Resonant

Inductor

S2

C1

2.1. CONVENTIONAL STEP UP CONVERTER

L
Vg

S1

Fig 1(c)
Fig 1. (a), (b), (c) Multiplier Boost Converters

In the proposed circuit Vg-L-S1-S2-C3-Vg forms

a conventional step up converter. The average
Voltage across the inductor when there is a small
ripple and continuous conduction mode [18] of
converter is VL

diL
VL Vg (1 D)V 1
dt

(1)

Where D is the converters duty cycle

characterized as the time when the switch S1is on
over the aggregate exchanging Period T, Vg and V1
are the data voltage and the voltage crosswise over
C1, separately. At steady express, the normal
voltage crosswise over L is zero. Accepting that the
derivative in Eq. (1) is zero the voltage crosswise
over C1 may be communicated by

V1

1
Vg
1 D

(2)

The converter has two equal circuits as per the

switching state. At the point when the switch is on,
the converter carries on as the circuit delineated in
Fig. 2(b). For the off condition, the converter
carries on as the Fig.2(c)

Fig. 2(d) current flowing through switches and

inductor

S6

2.2 VOLTAGE MULTIPLIER STAGE

S5
S4
S3

C4 C2

C3

S2

Lr

C5

It is imperative that the aforementioned standard

may be connected to the next voltage multipliers
installing a resonant inductor at the transport where
the energy storage capacitor is associated with the
voltage multiplier stage.

C1

Vg

Fig 2(b) S1 is ON
S6

S5
S4

C4 C2

L
Vg

Lr

C5

S3

S2

C3

The switch is on, capacitor C1 exchanges charge

to C2 through S1, S3 and the resonant inductor Lr.
Lr is utilized for reverberation purposes, not for
energy storage. Subsequently, it is a few hundred
times littler than the principle inductor L, and its
put away energy may be dismissed. Perfect
switches and capacitors sufficiently extensive to
work with a little ripple are expected [18]. The
exchanged capacitor activity makes the same
enduring state voltage in C2 and C1.Fig. 2(d)
shows the present iL through the energy storage
inductor. Notice that when current iL begins rising,
a resonant current is3 moves through S3, Fig. 2(b).
The basic of is3 turns into the charge that C1
exchanges to C2. On the off chance that the
inductor is uprooted, the current would be nonresonant as appeared in Fig. 1(d), prompting higher
conduction losses in transistors and capacitors, and
expanding the EMC issues [19].

C1

S1

Fig 2(c) S1 is off

At the point when the switch is off, diode s2

closes because of the current in L, connecting the
negative side of C2 to the same capability of the
positive side of C1, Fig. 1(c). Such quasi series
arrangement association is in parallel with C3, and
after that C3 is accused of double the voltage
communicated in (2). Fig. 2(d) demonstrates the

current is2 through s2. Such present tends to be iL

yet since Lr begins depleting current (the one
through S4 and S6), is3 gradually diminishes as iLr
builds attempting to reach iL. When the switch is on
once more, C3 exchanges charge to C4 clipping it to
the same voltage and after that both C3 and C4 hold
double the voltage in Eq. (2). The enduring state
current is5 is additionally appeared in Fig.
2(d).When the switch is off once more, the quasi
series arrangement association ofC4and C1charges
C5to three times the support converter voltage
communicated. As in Fig. 1(c) capacitors hold
distinctive voltages. C1 and C2 hold a lower
voltage, which relates to the routine help converter
mathematical statement (2). C3and C4 holds twice
this voltage, while C5 holds three times that
voltage. It is important that capacitors lost their
charge when transfer charge to others. Be that as it
may, as in any force converter, they may be chose
effectively and keep their voltage in a certain
adequate reach named little ripple approximation.
The current among diodes is the same in normal,
see Fig. 2(d).The territory under the current is hard
to express from the waveform but notice that the
DC segment of the yield current is depleted by all
diodes (since the dc-current through capacitors get
to be zero).

then abatements to zero. Currents is4 and is6

decrease the length of C3and C5 are charged,
reducing the current through Lr. At the point when
the current iLr is lower than iL the rest of iL
smoothly closes S2 once more. The current tends to
be iL until the principle switch S1 closes in the
following exchanging period.

The charge interchange Q during one switching

period is, s3 and s5 are off. The utilization of the
averaging method

Where Ce2 is the proportional capacitance of

the arrangement association C3C4.The resonant
frequencies may be decided to contrast from one
another yet capacitors in voltage multipliers are
generally chosen to be equivalent, and in such case
they produce the same resonant recurrence. It is
essential to indicate this recurrence in light of the
fact that charge-trade relies on upon it. Keeping in
mind the end goal to abstain from covering
permitting the current to be zero and lessening
exchanging losses, it is conceivable to set a base
estimation of the duty cycle.

t Ts

ioutdt Iout Ts

(3)

Where iout is the output current and T s is the

switching period.
The current through the resonant inductor Lr is
zero, since it is the sum of the current (zero in
average) of two capacitors. In Fig. 2(d) the area
under currents is the same for all The present in the
energy storage inductor L shows the traditional
triangular waveform, which rises when the switch
s1is on with an incline of (Vg/L), and reductions
when the s1is off. When the switch opens, S2 closes
in light of the fact that the current through Lr is
zero and after that the current through L is at first
depleted through S2, which is shut, for all intents
and purposes associating the negative side of C2
and C4 to the positive side of C1. This tends to close
S4 and S6 to transfer charge towards C3 and C5
from the charge in C2 and C4, respectively. This
prompts a present augmentation through Lr, which
is the total of i and is6 at such minute, Fig. 2(d). At
the point when the current through Lr reaches the
present in L, s2 naturally opens. Consequently is6
becomes similar to Fig. 2(d). It tends to be iL and

C2and C4 has been released in the last

switching cycle, and the current from C1and C3
begins to charge them through s3and s5. The
present introduces a semi-sinusoidal waveform;
diodes keep the negative semi-cycle. Actually,
there are two resonant circuits in this exchanging
state, one made by Lr and the arrangement
association of C1and C2, which resonant
recurrence
gets
to
be
diodes.

f1

w1
1

2 2 LrCe1

(4)

Where Ce1 is the equal capacitance of the

arrangement connection C1C2. The other resonant
circuit is made by Lr and the arrangement
connection of C3C4, which recurrence

f2

w2
1

2 2 LrCe 2

(5)

At the point when the current is3 achieves zero

(see Fig. 2(d)), the voltages across the capacitor
C2, v2 is somewhat bigger than V1 (V2 is precisely
equivalent to V1 when the current achieves the
most extreme worth), and S3 keeps open whatever
remains of the exchanging period (after the half of
a sinusoidal cycle).
3. DESIGN OF CIRCUIT PARAMETERS
The selection of components main designed
guidelines is explained in this below section.
3.1. ENERGY STORAGE INDUCTOR (L)
The energy storage inductor L may be selected
using the traditional method. Where the inductor is

connected to the input voltage source Vg, during a

period given by the duty cycle D times the
switching period Ts .According to the desired
current ripple IL. The following expression may be
used

diL
iL
iL
L
Vg L
dt
t
DTs
L

(6)

VgDTs
iL

(7)

3.2. CAPACITOR DESIGN

IS6

IL

Where QX, represents the amount of charge is being

inter-changed. This assumption may be used to
calculate C4. Then dc component of the load
current is drained by all diodes (due to the null dc
current through the capacitors), and then C4receives
Q through s5 from C3 when the switch is on C4can
be predicted as

C5

When switch is on capacitor c is discharge with the

output voltage

dVc
Vc V 5
C
ic C

dt
t
R

(8)

Let time increment t = DTs, then capacitor can be

V 5t V 5Ts
V 5D

V 5R V 5R V 5 FsR

(9)

Where, V is the voltage in capacitor C .v is the

voltage ripple performed for C5, T is the switching
period, and f is the switching frequency. Then
resonant inductor Lr is too small this time is
shorter.
This topology is useful then current has low
ripple. In switched capacitor this principle cannot
be used because the current waveform. This
topology presents a comfortable, constructive, and
simplified method to calculate the capacitors in the
switched capacitors stage.
Concern at steady state, when the switch is off,
C5 receives through s6 the total charge required for
deliver the load. In the subsequent cycle, this
charge is expressed. This charge inter change
always appears in the procedures for capacitors
selection. Then, rewriting the charge may be

1
Q
V 4

(11)

V4 is ripple voltage expected for C the charge

interchange may also be used to find out C3,C2, C1

C3

1
Q
V 3

C2

1
Q
V 2

C1

1
Q
V 1

(3) Equivalent circuit for output capacitor

C5

1
V5
1
DTs

QX (10)
V 5
R
Vx

C5

C4

Its also same procedure for calculating the

capacitor in a SMPS is similar to those Inductors
(L)

VDc

conformed as the product of time and current.

(12)

Where v , v2 and v1 are voltage ripple

expected for C3,C2,C1, respectively
Then C1 can be estimated. For all the C1 current
discharge flows through s3 in the resonant shape
and its integral is equal to Q.
Capacitor C5 act as the boost output capacitor,
which is charged from the input-part and
discharged to the load. Thus its important to select
C5 and also decoupling the load effect to the inputpart of the converter.
3.3 MINIMUM DUTY CYCLE
The minimum duty cycle that can be used during
the design process. Randomly, an improper duty
cycle reduces.
If switch is open before the current reaches
zero, then switching losses will increase and EMI
should be generated because of discontinuous
current in some paths of the circuit. This must be
sets in a minimum duty cycle for the converter,
which can be expressed as the half-period of the
resonant current divided by the switching period.

D min

1
LrCe
Ts

(13)

The resonant current is the RMS value is lower,

reducing the conduction losses. Then it gets large
minimum duty cycle, between the output voltage
ranges and conduction losses.
4. SIMULATION RESULTS
Fig 2(a) is proposed topology where the Input
Voltage is 15 Volts and switching frequency is 200

KHZ and Duty cycle of 0.5 with a load of 200.

The below Table (1) summarizes the experimental
components parameters

S.No

Component

Rating

MOSFET S1

200 V , Ron = 10.7m

Ultra-Fast Diodes S2-S6

200 V, Vf=1.5V

Energy Stored Inductor(L)

40uH

Resonant Inductor(Lr)

100nH

Capacitor

3.3uF

Resistor

200

Table (1) Components Ratings

Figure 4(a) shows the Inductor current and resonant
current waveforms where the average Inductor
current is 2.75A, with a ripple of 0.9. From Eq 7

Vg * D * Ts 15 * 0.5 * 5 * 10^ 6

iL
0.9

=40uH
Voltage across C1 is V 1

Vg
30v
1 D

voltage ripple across C1 can be calculated from eq 11

V 1

Q 2.2u

0.66v
C1 3.3u

Calculation for voltage ripple is may be

approximated due to the components tolerance.
Voltage ripple across C5

V5

D * Ts * Vs
C5 * R
=0.33

Fig 4(a). Inductor Current and Current through S3 (Resonant Current)

Fig 4(b).Output voltage and output current

95%
90%

Resonant
Switching

85%
80%

Non Resonant
Switching

75%
40
80
120
Watts Watts Wattts

Fig.5. Efficiency of resonant switching converter vs a non-resonant switching converter

5 DISCUSSIONS
The designed DC-DC Converter is a hybrid
Converter where a simple conventional converter
is merged with a Diode Capacitor multiplier along
with Resonant Inductor. The main advantages of
this converter are
I.
II.

III.

IV.

For this prototype only one switching

transistor is enough to drive the circuit.
The spike currents passing through
capacitors (Diodes) are reduced by using
resonant Inductor.
Resonant inductor rating is negligibly
small compared to the Energy stored
inductor.
Efficiency of converter is very high
especially for lesser loads.

6. CONCLUSION
This proposed convertor achieves a high
voltage gain without using high Duty Cycles. By
adding two diodes and two capacitors level if
converter will be increases. Simulation results are
provided to demonstrate the feasibility of the
proposition,
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