8259A PRIORITY INTERRUPT CONTROLLER

The priority interrupt controller is used when several I/O devices transfer data using interrupt
and they are to be connected to the same interrupt level of the Microprocessor. When the number of the
I/O devices is less than the number of interrupt levels of the Microprocessor, such controllers are not
required.
The Intel 8259 is a single chip priority interrupt controller. It is a 28 pin DIP (Dual Inline
Package) I.C. and uses N-MOS technology.

INTA
D 7 D0

RD
WR
A0

DATA
BUS
BUFFER

READ/
WRITE
LOGIC

CS

CAS0
CAS1
CAS2
SP/EN

CASCADE
BUFFER/
COMPARA
TOR

INT

CONTROL LOGIC

In
Service
Reg
(ISR)

Priority
Resolver

Interrupt
request
register

IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7

Interrupt Mask REG

INTERNAL BUS

8259 programmable Interrupt controller handles up to eight vectored priority interrupts for the CPU. It
is cascadable for up to 64 vectored priority interrupts without additional circuitry.

CS: (Chip select) : The low status of this signal enables communication between CPU and 8259.
WR: 0 Enables Intel 8259 to accept command word from CPU.
RD : 0 On this pin enables Intel 8259 to send the various status signal on the data bus for CPU.
D0 D7 : Bi-directional data bus. Control status and interrupt vector informations are transferred via
this bus.
CAS0 CAS2: Cascade lines.
SP / EN : Slave program / Enable buffer.
INT: Interrupt. It is used to interrupt the CPU.
INTA: Interrupt acknowledge.
IR0 IR7 : Interrupt requests. I/O devices send interrupt request through these lines.
A0 :Address line. It acts in conjunction with RD,WR, and CS. The Intel 8259 uses it to interrupt
command words, the CPU writes and status the CPU wants to read.

INTEL 8085/86

INTR

INT

RAM

INTEL
8259

ROM

Input
Device

Output
Device

Output
Device

Fig B:

Input
Device

Interfacing of 8259 and I/O devices

Fig B shows the connections of PIC (programmable Interrupt Controller) and I/O devices to
the Microprocessor. The priority can be assigned to the I/O devices connected to PIC. 8 I/O devices
can be connected to 8259 through IR0 IR7 lines.
8259 accepts requests from I/O devices and determines which of the incoming request is of
highest priority. After checking the priority of the interrupt request, the 8259 sends an interrupt signal
to the Microprocessor through INT line. The Microprocessor sends acknowledge signal through INTA
line. On receiving INTA signal all interrupts of lower priority are inhibited (hold back) and the 8259
sends a CALL instruction to the Microprocessor. The CALL instruction is unique so that the
Microprocessor can take up the ISS(Interrupt Service Subroutine) for the I/O device which has
requested for data transfer.

Interrupt Operation:
To implement interrupts, the interrupt enable flip-flop in the Microprocessor should be enabled
by writing the EI instruction, and the 8259 should be initialized by writing control words in the control
register. 8259 requires two types of control words:
Initialization command words (ICWs) and
Operational Command Words (OCWs).
The ICWs are used to setup the proper conditions and specify RST vector addresses. The
OCWs are used to perform functions such as masking interrupts, setting up status, read operations
etc.,.
After 8259 is initialized, the following sequence of events occurs when one or more interrupt request
lines go high.
1. The interrupt request register stores the requests.
2. The priority counter checks three registers:
IRR for interrupt requests
The IMR for masking bits and
ISR for interrupt request being served. It resolves priority and sets the INT high
3. The Microprocessor acknowledges the interrupt by sending INTA.
4. After INTA is received, the appropriate priority bit in the ISR is set to indicate which
interrupt level is being served , and the corresponding bit in the IRR is reset to indicate that
the request is accepted. Then the OP-code for call instruction is placed on the data bus.

8259

PIC

Fully nested mode: This is a general purpose mode in which all IRs are arranged from highest to
lowest, with IR0 as highest and IR7 as the lowest.
In addition, any IR can be assigned the highest priority in this mode. The priority sequence will
then begin at that IR
IR0 IR1 IR2 --------------------- IR7
0
1
2
--------------------7

Automatic Rotation mode: A device after being served, receives the lowest priority. Assuming
that the IR2 has just been serviced. It will receive the seventh priority.
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
5
6
7
0
1
2
3
4

Specific Rotation Mode: This mode is similar to automatic rotation mode, except that the user
can select any IR for the lowest priority. Thus fixing all other priorities. 8259 is a complex device with
various modes of operations.

Interrupt Triggering: 8259 can accept an interrupt request with either the edge triggered mode
or the level triggered mode. This mode is determined by the initialization instructions.

Interrupt status: The status of the interrupt requests (IRR,ISR and IMR) can be read and this
status information can be used to make the interrupt process versatile.

Poll method: The 8259 can be setup to function in a polled environment. The MPU polls the 8259
rather than each peripheral.

Programming 8259: The 8259 requires two bytes of command words. Initialization Command
Words (ICWs), Operational Command Words (OCWs). 8259 can be initialized with four ICWs. The
first two are essential and the other two are optional, based on the modes being used. Once initialized
8259 can be setup to operate in various modes by using three different operational command words.
A0

D7

D6

D5

D4

A7

A6

A5

D3

LTIM

D2

ADI

D1

D0

SNGL

IC4
1

ICW4

needed
0

needed
SNGL - 1 - single
0 - cascade mode

ADI

--

LTIM --

Call Address Interval

1 -- interval of 4
0 -- interval of 8
1 -- Level Triggered Mode
0 -- Edge Triggered Mode

A5 A7 -- Of interrupt vector address.

ICW2
A0

D7

D6

D5

D4

A15

A14

A13

A12

D3

A11

D2

A10

It is the interrupt vector address

D1

A9

D0

A8

not

IR
7
6
5
4
3
2
1
0

D7
A7
A7
A7
A7
A7
A7
A7
A7

D6
A6
A6
A6
A6
A6
A6
A6
A6

D5
A5
A5
A5
A5
A5
A5
A5
A5

INTERVAL 4
D4
D3
D2
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0

D7
A7
A7
A7
A7
A7
A7
A7
A7

D6
A6
A6
A6
A6
A6
A6
A6
A6

D5
1
1
1
1
0
0
0
0

INTERVAL 8
D4
D3
D2
1
1
0
1
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0

IR
7
6
5
4
3
2
1
0

D1
0
0
0
0
0
0
0
0

D0
0
0
0
0
0
0
0
0

D1
0
0
0
0
0
0
0
0

D0
0
0
0
0
0
0
0
0

A7
A6
A5

MSB

3 TO 8
DECODER

A3
A2
A1

8259

LSB

CS
A0

IR0
IR1
IR2
IR3
IR4
IR5
IR6

Fig shows an interrupt driven system 8257. Four sources are connected to IR lines of 8259,
emergency signal, A/D converter, keyboard and printer of these emergency signal has highest priority
and produces has lowest priority. Explain the following initialization instructions.
D1
MV1
OUT
MV1
OUT

Initialization
A,76H
80H
A, 20H
81H

Instructions
ICW1
Initialize 8259A
ICW2
Initialize 8259

1. The DI instruction disables the interrupts. So that the initialization process will not be interrupted.
2. The command word 76H specifies the following parameters.

A0

D7

D6

D5

D4

D3

D2

D1

A7

A6

A5

LTIM

ADI

SNGL

IC4

A0 A4 will be supplied by 8259

Address lines
D0
D1
D2
D3
D5 D 7

D0

indicates NO ICW$ is needed.

indicates single 8259 is used.
call address interval is 4 locations
edge triggered mode
are address lines A5 A7

A7

A6

A5

A4

A3

A2

A1

A0

The address bits A0 A4 are supplied by 8259. The subsequent addresses are four locations a part leg.
IR1 = 64
IR0 has the highest priority. The low order byte of IR0 call address.

D7

D6

D5

D4

D3

D2

D1

D0

A7

A6

A5

A0 A4 are supplied by 8259 and A5 A7 are supplied by ICW1

0

The low order byte of IR0 call address is 60H.

3. The port address of 8259 for ICW1 is 80H. A0 should be at logic 0 and the other bits are determined
the decoder
4. Command word ICW2is 20H, which specifies the high order byte of the call address.

D7

D6

D5

D4

D3

D2

D1

D0

A15

A14

A13

A12

A11

A10

A9

A8

5. The port address of ICW2 is 81H. A0 should by at logic 1.

The low order byte of IR0 call address is 60H.
IR1
64H
IR2
68H
.
IR6
78H
From ICW1

8259

The RST code for

Port addresses for command Words

IR0
2060
IR1
2064
IR2
2068
.
IR6
2078
ICW1
80
ICW2
81
ICW3
82
ICW4
83

INITIALISING AN 8259:

The base address for the 8259A is FFOOh. For an 8259 the two internal addresses are selected by a
high or a low on the Ao pin.
The two system addresses of 8259A are
FFOOH
FFO2H
ICW'S are needed for various 8259 applications Fig shows this in flowchart form. According to this an ICW1
and ICW2 must be sent to any 8259 in the system. If the system has any slave 8259 (cascade mode)then an
ICW3 must be sent to the master and a different ICW3 must be sent to the slave..
If the system is an 8086 or of you want to specify certain special conditions, then you have to send an ICW4 to
the master and to each slave. Now let us look at the formats for the different ICW'S.
The first thing to notice about the ICW formats in fig is that the bit Ao on the left end of each of these is
not part of the actual command word. This bit tells you the internal address that the control word must be sent
to. The Ao = O next to ICW1 tells you that ICW1 must be sent to internal address O, which for our 8259A
corresponds to system address FFOOH.

ICW1

No
SNGL = 1

In
Cascade
Mode
Yes
SNGL = 0

ICW3

Is ICW4
Needed
No
IC4 = 0
Yes IC4 = 1
ICW4

ICW2
Ready to accept
interrupt requests

8259A initialization command word formats sending order.

A0

D7

D6

D5

D4

D3

D2

D1

A7

A6

A5

LTIM

ADI

SNGL

D0

IC4

The A0 in the left end of each of the command word is not part or actual command word.
This bit tells you the internal address that the control word must be sent to.
If Ao=0 The command word corresponds to the system address FFOOH.
If A0=1 The command word corresponds to the system address FFO2H
DO: The least significant bit of ICW1 tells the 8259 whether it needs to look for an ICW4 or not. Since we are
using the device in an 8086 system, we need to send ICW4. Therefore we make bit Do a 1.
D1: 1-single 8259 is used
0 -cascade mode.
D2: Is a don't care, so we make it a D.
D3:

1-level triggered mode

0-edge triggered mode.

We usually use edge-triggered mode.

D5 / D6 / D7: are don't cares.
So we make them O's.

ICW2
Ao
1

D7
A15

D6
A14

D5
A13

D4
A12

D3
A11

D2
A10

D1
A9

D0
A8

ICW2 is used to tall the 8259 the type number to send in response to an interrupt signal on the IRO input in
response to an interrupt signal on same other IR input, the 8259 will automatically add the number of the IR
input to this base number and send the result to the 8086 as the type number for that input.
Interrupt types O-31 are dedicated / reserved type 32-is the lowest type number available highest.

ICW3(Master Device):
Ao
1

D7
S7

D6
S6

D5
S5

D4
S4

D3
S3

D2
S2

D1
S1

D0
S0

1 - IR input has a slave

O - IR input does not have a slave
ICW3(Slave Device):
Ao
1

D7
0

D6
0

D5
0

D4

D3
0

ID2
0
0
0
0
1
1
1
1

ID1
0
0
1
1
0
0
1
1

D2
ID2

ID0
0
1
0
1
0
1
0
1

D1
ID1

D0
ID0

Slave ID
0
1
2
3
4
5
6
7

If we are not using a slave we need not send ICW3.

If we are using a slave 8259 in a system, we have to send an ICW3 to the master to tell it which IR inputs have
slaves.
You have to send an ICW3 to a slave 8259 to give it an ID number. The ID number you give a slave is equal to
the IR input of the master.
ICW4
Ao
1

D7
0

D6
0

D5
0

D4
SFNM

DO = 1 - 8086 Mode
D1 = 1 - Auto EOI
D4: 1 - Special fully nested mode
0 - Not special fully nested mode

D3
BUF

D2
M/S

D1
AEOI

D0
PM

O - 8085 Mode
O - Normal EOI

Because we are operating on 8086 we have to send an ICW4.

If the automatic end of interrupt bit is set in ICW4 the 8259 will automatically reset the in-service register bit
for the interrupt input that is being responded to when the second interrupt acknowledge pulse is received.

OCW'S

In addition to the initialization command words 8259 has a second set of command words called
operational command words.

A0

OCW1:

D7

M7

D6

D5

M6

D4

M5

M4

D3

M3

D2

D1

M2

D0

M1 M0

Interrupt Mask
1 - Mask Set
0 - Mask Reset

An OCW1 must be sent to an 8259 to unmask any IR input that you want it to respond to.
For example let's assume that we want to use only IR2 and IR3.
0-unmask
1-mask.
OCW1

A0
1

OCW2

D7
1

A0

D6

D5

D7

D6

D4

D3

D5

D4

SL EOI 0

D2
0

D3

D2

L2

L2

L1

L0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

D1 D0
1

D1

L1

D0

L0

IR Level to be
acted upon
0
1
2
3
4
5
6
7

OCW2 is used to reset a bit in the in-service register. This is usually done at the end of the interrupt service
procedure. But it can be done at any time in the procedure.
Once the bit in ISR is reset the 8259 can respond to interrupt signal of lower priority.
In small systems we usually use the non-specific end of interrupt command word.
OCW2 is used is used to tell 8259 to rotate the priorities of the IR inputs so that after an IR input is serviced, it
drops to the lowest priority.
OCW3
A0
D7
D6
D5
D4
D3
D2
D1
D0

ESMM SMM 0

RR

RIS

D0, D1- Read Register Command

D2 - 1 - Poll command
0 - No poll command
D5, D6 - Special Mask Mode

SOFTWARE INTERRUPT APPLICATIONS

The 8086 Software Interrupt Instruction INT N can be used to test any type of interrupt procedure. For
example to test a type 64 interrupt procedure without the need for external hardware you can just execute the
instruction INT 64.
Another important use of software interrupts is to call basis input output system, or BIOS, procedures in
an IBM-PC type computer these procedures in the system rolls perform specific input or output functions, such
as reading a character from the keyboard, working some characters to the CRT, or reading some information
from a disk.
INT 17h instruction can be used to call a procedure which sends some characters to the printer.
MOV AX, 4C00H
Int 21h

Graceful exit to DOS with function call 4CH