PACKAGE n_bit_int is

CONSTANT word_length_in: INTEGER :=9;

CONSTANT word_length_out: INTEGER :=20;
END n_bit_int;
LIBRARY work;
USE work.n_bit_int.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY lowpass2 IS
port(clk,rst : in std_logic;
x_in
: in std_logic_vector(word_length_in downto 0);
y_out : out std_logic_vector(word_length_out downto 0));
END lowpass2;
Architecture behavior of lowpass2 is
signal ff0,ff1,ff2,ff3,ff4,ff5,ff6,ff7,ff8,ff9,ff10 : std_logic_vector(word_leng
th_out downto 0);
signal a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11, aux_x : std_logic_vector(word_length_
out downto 0);
BEGIN
sxtcomp1: process (x_in)
begin
aux_x(word_length_in downto 0) <= x_in;
for k in word_length_out downto word_length_in LOOP
aux_x(k) <=x_in(word_length_in);
END LOOP;
END PROCESS sxtcomp1;
registros: PROCESS (clk,rst)
begin
if (rst='1') then
ff0<=conv_std_logic_vector(0,
ord_length_out+1);
ff2<=conv_std_logic_vector(0,
ord_length_out+1);
ff4<=conv_std_logic_vector(0,
ord_length_out+1);
ff6<=conv_std_logic_vector(0,
ord_length_out+1);
ff8<=conv_std_logic_vector(0,
ord_length_out+1);

word_length_out+1);ff1<=conv_std_logic_vector(0, w
word_length_out+1);ff3<=conv_std_logic_vector(0, w
word_length_out+1);ff5<=conv_std_logic_vector(0, w
word_length_out+1);ff7<=conv_std_logic_vector(0, w
word_length_out+1);ff9<=conv_std_logic_vector(0, w

elsif(clk='1' and clk'event) then

ff0<=a1;
ff1<=a2+ff0;
ff2<=a3+ff1;
ff3<=a4+ff2;
ff4<=a5+ff3;

ff5<=a6+ff4;
ff6<=a7+ff5;
ff7<=a8+ff6;
ff8<=a9+ff7;
ff9<=a10+ff8;
ff10<=a11+ff9;
end if;
END PROCESS registros;
a1<=conv_std_logic_vector(conv_integer (aux_x)*89,word_length_out +1);
a2<=conv_std_logic_vector(conv_integer (aux_x)*38,word_length_out +1);
a3<=conv_std_logic_vector(conv_integer (aux_x)*101,word_length_out +1);
a4<=conv_std_logic_vector(conv_integer (aux_x)*180,word_length_out +1);
a5<=conv_std_logic_vector(conv_integer (aux_x)*245,word_length_out +1);
a6<=conv_std_logic_vector(conv_integer (aux_x)*270,word_length_out +1);
a7<=conv_std_logic_vector(conv_integer (aux_x)*245,word_length_out +1);
a8<=conv_std_logic_vector(conv_integer (aux_x)*180,word_length_out +1);
a9<=conv_std_logic_vector(conv_integer (aux_x)*101,word_length_out +1);
a10<=conv_std_logic_vector(conv_integer (aux_x)*38,word_length_out +1);
a11<=conv_std_logic_vector(conv_integer (aux_x)*89,word_length_out +1);
salida: process (clk,rst)
begin
if(rst='1') then
y_out<=CONV_STD_LOGIC_VECTOR(0,word_length_out +1);
elsif(clk='1' and clk'event) then
y_out<=ff10;
end if;
end process salida;
end behavior;