module fulladd(a,b,cin,sum,cout);

input cin;
input [15:0]a,b;//8-bit inputs
output [16:0]sum; // = 9-bit output
wire [15:0]sum_temp;//temp reg to store 8-bit sum
output cout;//MSB of 9-bit sum or carry out
wire
cy_0,cy_1,cy_add1,cy_add2,cy_add3,cy_add4,cy_add5,cy_add6,cy_add7,cy_add8,cy_add9,cy_add1
0,cy_add11,cy_add12;
wire [1:0] sum_low,a_1,b_1;
wire [3:2] sum_0,sum_1,sum_high,a_2,b_2;
wire[6:4] sum_2,sum_3,a_3,b_3,sum_high_1;
wire [10:7] sum_4,sum_5,a_4,b_4,sum_high_2;
wire [15:11] sum_6,sum_7,a_5,b_5,sum_high_3;
assign cy_0=1'b0;
assign cy_1=1'b1;
assign a_1={a[1],a[0]};//lower bits of input a
assign b_1={b[1],b[0]};//lower bits of input b
assign a_2={a[3],a[2]};//higher bits of input a
assign b_2={b[3],b[2]};//higher bits of input b
assign a_3={a[6],a[5],a[4]};//higher bits of input a
assign b_3={b[6],b[5],b[4]};//higher bits of input b
assign a_4={a[10],a[9],a[8],a[7]};//higher bits of input a
assign b_4={b[10],b[9],b[8],b[7]};//higher bits of input b
assign a_5={a[15],a[14],a[13],a[12],a[11]};//higher bits of input a
assign b_5={b[15],b[14],b[13],b[12],b[11]};//higher bits of input b

adder_2_bit ADD1(a_1,b_1,cin,sum_low,cy_add1);//lower k/2 bit adder

adder_2_bit ADD2(a_2,b_2,cy_0,sum_0,cy_add2);//upper k/2 bit adder with cin=0

adder_2_bit ADD3(a_2,b_2,cy_1,sum_1,cy_add3);//upper k/2 bit adder with cin=1
adder_3_bit ADD4(a_3,b_3,cy_0,sum_2,cy_add4);//upper k/2 bit adder with cin=0
adder_3_bit ADD5(a_3,b_3,cy_1,sum_3,cy_add5);//upper k/2 bit adder with cin=1
adder_4_bit ADD6(a_4,b_4,cy_0,sum_4,cy_add6);//upper k/2 bit adder with cin=0
adder_4_bit ADD7(a_4,b_4,cy_1,sum_5,cy_add7);//upper k/2 bit adder with cin=1
adder_5_bit ADD8(a_5,b_5,cy_0,sum_6,cy_add8);//upper k/2 bit adder with cin=0
adder_5_bit ADD9(a_5,b_5,cy_1,sum_7,cy_add9);//upper k/2 bit adder with cin=1

muxs_2_to_1 MUX1(sum_0,sum_1,cy_add1,sum_high);

muxs_3_to_1 MUX2(sum_2,sum_3,cy_add1,sum_high_1);

muxs_4_to_1 MUX3(sum_4,sum_5,cy_add1,sum_high_2);
muxs_5_to_1 MUX4(sum_6,sum_7,cy_add1,sum_high_3);

muxc_2_to_1 MUX5(cy_add2,cy_add3,cy_add1,cy_add10);

muxc_2_to_1 MUX6(cy_add4,cy_add5,cy_add10,cy_add11);

muxc_2_to_1 MUX7(cy_add6,cy_add7,cy_add11,cy_add12);

muxc_2_to_1 MUX8(cy_add8,cy_add9,cy_add12,cy_add13);

assign sum_temp={sum_high,sum_high_1,sum_high_2,sum_high_3,sum_low};
assign cout={cy_add13};

assign sum={cout,sum_temp};
endmodule
module adder_2_bit(a,b,cin,sum,cout);
input[1:0]a,b;
input cin;
output[1:0]sum;
output cout;
wire cy;

full_adder FA1(a[0],b[0],cin,sum[0],cy);
full_adder FA2(a[1],b[1],cy,sum[1],cout);

endmodule

module adder_3_bit(a,b,cin,sum,cout);
input[2:0]a,b;
input cin;
output[2:0]sum;
output cout;
wire [1:0]cy;

full_adder FA3(a[0],b[0],cin,sum[0],cy[0]);
full_adder FA4(a[1],b[1],cy[0],sum[1],cy[1]);
full_adder FA5(a[2],b[2],cy[1],sum[2],cout);
endmodule

module adder_4_bit(a,b,cin,sum,cout);

input[3:0]a,b;
input cin;
output[3:0]sum;
output cout;
wire [2:0]cy;

full_adder FA6(a[0],b[0],cin,sum[0],cy[0]);
full_adder FA7(a[1],b[1],cy[0],sum[1],cy[1]);
full_adder FA8(a[2],b[2],cy[1],sum[2],cy[2]);
full_adder FA9(a[3],b[3],cy[2],sum[3],cout);

endmodule
module adder_5_bit(a,b,cin,sum,cout);
input[4:0]a,b;
input cin;
output[4:0]sum;
output cout;
wire [3:0]cy;

full_adder FA10(a[0],b[0],cin,sum[0],cy[0]);
full_adder FA11(a[1],b[1],cy[0],sum[1],cy[1]);
full_adder FA12(a[2],b[2],cy[1],sum[2],cy[2]);
full_adder FA14(a[3],b[3],cy[2],sum[3],cy[3]);
full_adder FA15(a[4],b[4],cy[3],sum[4],cout);

endmodule

module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=(a^b^cin);
assign cout=((a&b)|(b&cin)|(a&cin));
endmodule

module muxs_2_to_1(i0,i1,s,out);
input[1:0]i0,i1;
input s;
output[1:0]out;
assign out=s?i1:i0;
endmodule

module muxs_3_to_1(i0,i1,s,out);
input[2:0]i0,i1;
input s;
output[2:0]out;
assign out=s?i1:i0;
endmodule

module muxs_4_to_1(i0,i1,s,out);
input[3:0]i0,i1;
input s;
output[3:0]out;
assign out=s?i1:i0;
endmodule

module muxs_5_to_1(i0,i1,s,out);
input[4:0]i0,i1;
input s;
output[4:0]out;
assign out=s?i1:i0;
endmodule

module muxc_2_to_1(i0,i1,c,out1);
input i0,i1;
input c;
output out1;
assign out1=c?i1:i0;
endmodule

modified:

module csa(a,b,cin,sum,cout);
input cin;
input [15:0]a,b;//8-bit inputs
output [16:0]sum; // = 9-bit output
output cout;
wire [15:0]sum_temp;//temp reg to store 8-bit sum
wire c1,c2,c3,c4,c5;
wire [1:0] sum_0,a_1,b_1;
wire[3:2] sum_1,a_2,b_2;
wire [6:4] sum_2,a_3,b_3;
wire [10:7] sum_3,a_4,b_4;
wire [15:11] sum_4,a_5,b_5;
assign a_1={a[1],a[0]};//lower bits of input a
assign b_1={b[1],b[0]};//lower bits of input b
assign a_2={a[3],a[2]};//higher bits of input a
assign b_2={b[3],b[2]};//higher bits of input b
assign a_3={a[6],a[5],a[4]};//higher bits of input a
assign b_3={b[6],b[5],b[4]};//higher bits of input b
assign a_4={a[10],a[9],a[8],a[7]};//higher bits of input a
assign b_4={b[10],b[9],b[8],b[7]};//higher bits of input b

assign a_5={a[15],a[14],a[13],a[12],a[11]};//higher bits of input a

assign b_5={b[15],b[14],b[13],b[12],b[11]};//higher bits of input b

adder_2_bit ADD1(a_1,b_1,cin,sum_0,c1);//lower k/2 bit adder

adder_2_bit ADD2(a_2,b_2,c1,sum_1,c2);//upper k/2 bit adder
with cin=0
adder_3_bit ADD3(a_3,b_3,c2,sum_2,c3);//upper k/2 bit adder
with cin=1
adder_4_bit ADD4(a_4,b_4,c3,sum_3,c4);//upper k/2 bit adder
with cin=0
adder_5_bit ADD5(a_5,b_5,c4,sum_4,c5);//upper k/2 bit adder
with cin=1
assign sum_temp={sum_0,sum_1,sum_2,sum_3,sum_4};
assign cout={c5};
assign sum={cout,sum_temp};

endmodule
module adder_2_bit(a,b,cin,sum,cout);
input[1:0]a,b;
input cin;
output[1:0]sum;
output cout;
wire cy;

full_adder FA1(a[0],b[0],cin,sum[0],cy);
full_adder FA2(a[1],b[1],cy,sum[1],cout);

endmodule

module adder_3_bit(a,b,cin,sum,cout);
input[2:0]a,b;
input cin;
output[2:0]sum;
output cout;
wire [1:0]cy;

full_adder FA3(a[0],b[0],cin,sum[0],cy[0]);
full_adder FA4(a[1],b[1],cy[0],sum[1],cy[1]);
full_adder FA5(a[2],b[2],cy[1],sum[2],cout);
endmodule

module adder_4_bit(a,b,cin,sum,cout);
input[3:0]a,b;
input cin;
output[3:0]sum;
output cout;

wire [2:0]cy;

full_adder FA6(a[0],b[0],cin,sum[0],cy[0]);
full_adder FA7(a[1],b[1],cy[0],sum[1],cy[1]);
full_adder FA8(a[2],b[2],cy[1],sum[2],cy[2]);
full_adder FA9(a[3],b[3],cy[2],sum[3],cout);
endmodule
module adder_5_bit(a,b,cin,sum,cout);
input[4:0]a,b;
input cin;
output[4:0]sum;
output cout;
wire [3:0]cy;

full_adder FA10(a[0],b[0],cin,sum[0],cy[0]);
full_adder FA11(a[1],b[1],cy[0],sum[1],cy[1]);
full_adder FA12(a[2],b[2],cy[1],sum[2],cy[2]);
full_adder FA14(a[3],b[3],cy[2],sum[3],cy[3]);
full_adder FA115(a[4],b[4],cy[3],sum[4],cout);

endmodule

module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=(a^b^cin);
assign cout=(((a^b)&cin)+(a&b));
endmodule