module fulladd(a,b,cin,sum,cout);

input cin;
input [15:0]a,b;//8-bit inputs
output [16:0]sum; // = 9-bit output
wire [15:0]sum_temp;//temp reg to store 8-bit sum
output cout;//MSB of 9-bit sum or carry out
wire
cy_0,cy_1,cy_add1,cy_add2,cy_add3,cy_add4,cy_add5,cy_add6,cy_add7,cy_add8,cy_add9,c
y_add10;
wire [3:0]
sum_0,sum_1,sum_2,sum_3,sum_4,sum_5,a_1,b_1,a_2,b_2,a_3,b_3,a_4,b_4,sum_low,sum_
high,sum_high_1,sum_high_2;
assign cy_0=1'b0;
assign cy_1=1'b1;
assign a_1={a[3],a[2],a[1],a[0]};//lower bits of input a
assign b_1={b[3],b[2],b[1],b[0]};//lower bits of input b
assign a_2={a[7],a[6],a[5],a[4]};//higher bits of input a
assign b_2={b[7],b[6],b[5],b[4]};//higher bits of input b
assign a_3={a[11],a[10],a[9],a[8]};//higher bits of input a
assign b_3={b[11],b[10],b[9],b[8]};//higher bits of input b
assign a_4={a[15],a[14],a[13],a[12]};//higher bits of input a
assign b_4={b[15],b[14],b[13],b[12]};//higher bits of input b

adder_4_bit ADD1(a_1,b_1,cin,sum_low,cy_add1);//lower k/2 bit adder

adder_4_bit ADD2(a_2,b_2,cy_0,sum_0,cy_add2);//upper k/2 bit adder with cin=0
adder_4_bit ADD3(a_2,b_2,cy_1,sum_1,cy_add3);//upper k/2 bit adder with cin=1
adder_4_bit ADD4(a_3,b_3,cy_0,sum_2,cy_add4);//upper k/2 bit adder with cin=0
adder_4_bit ADD5(a_3,b_3,cy_1,sum_3,cy_add5);//upper k/2 bit adder with cin=1
adder_4_bit ADD6(a_4,b_4,cy_0,sum_4,cy_add6);//upper k/2 bit adder with cin=0
adder_4_bit ADD7(a_4,b_4,cy_1,sum_5,cy_add7);//upper k/2 bit adder with cin=1

muxs_2_to_1 MUX1(sum_0,sum_1,cy_add1,sum_high);

muxs_2_to_1 MUX2(sum_2,sum_3,cy_add8,sum_high_1);

muxs_2_to_1 MUX3(sum_4,sum_5,cy_add9,sum_high_2);

muxc_2_to_1 MUX4(cy_add2,cy_add3,cy_add1,cy_add8);

muxc_2_to_1 MUX5(cy_add4,cy_add5,cy_add8,cy_add9);

muxc_2_to_1 MUX6(cy_add6,cy_add7,cy_add9,cy_add10);

assign sum_temp={sum_high,sum_high_1,sum_high_2,sum_low};
assign cout={cy_add10};
assign sum={cout,sum_temp};
endmodule

module adder_4_bit(a,b,cin,sum,cout);
input[3:0]a,b;
input cin;
output[3:0]sum;
output cout;
wire [2:0]cy;

full_adder FA1(a[0],b[0],cin,sum[0],cy[0]);
full_adder FA2(a[1],b[1],cy[0],sum[1],cy[1]);
full_adder FA3(a[2],b[2],cy[1],sum[2],cy[2]);
full_adder FA4(a[3],b[3],cy[2],sum[3],cout);

endmodule

module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=(((~a)&b&(~cin))+(a&(~b)&(~cin))+((~a)&(~b)&cin)+(a&b&cin));
assign cout=((a&b)+(a&cin)+(b&cin));
endmodule

module muxs_2_to_1(i0,i1,s,out);
input[3:0]i0,i1;
input s;
output[3:0]out;
assign out=s?i1:i0;
endmodule

module muxc_2_to_1(i0,i1,c,out1);
input i0,i1;
input c;
output out1;
assign out1=c?i1:i0;
endmodule