library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ncoR is

-- Top level Entity

generic
(
size : integer := 20
);

port
(
clk

: in std_logic;

reset : in std_logic;
x0

: in std_logic_vector (size-1 downto 0);

y0

: in std_logic_vector (size-1 downto 0);

z0

: in std_logic_vector (size-1 downto 0);

phase : out std_logic_vector (size-1 downto 0);

quad : out std_logic_vector (size-1 downto 0);
angle : buffer std_logic_vector (size-1 downto 0);
start : in std_logic;
done : out std_logic
);

end ncoR ;

architecture arch of ncoR is

signal cnt : std_logic_vector(4 downto 0);

signal newx : std_logic_vector(size-1 downto 0);
signal newy : std_logic_vector(size-1 downto 0);
signal newz : std_logic_vector(size-1 downto 0);
signal xreg : std_logic_vector(size-1 downto 0);
signal yreg : std_logic_vector(size-1 downto 0);
signal zreg : std_logic_vector(size-1 downto 0);
signal sxreg : std_logic_vector(size-1 downto 0);
signal syreg : std_logic_vector(size-1 downto 0);
signal atan : std_logic_vector(size-1 downto 0);
signal fin : std_logic;
signal nxt : std_logic;
signal as

: std_logic;

signal nas : std_logic;

-- Component declarations

component addsubR
generic
(
size : integer := 20
);

-- Adder

port
(
dataa : in

std_logic_vector (size-1 downto 0);

datab : in

std_logic_vector (size-1 downto 0);

result : out

std_logic_vector (size-1 downto 0);

as

: in

std_logic

);
end component;

component anglelut

-- Angle Look-Up Table

generic
(
size : integer := 20
);

port
(
index : in std_logic_vector (4 downto 0);
atan

: out std_logic_vector (size-1 downto 0)

);
end component;

component fsmR

port
(

-- Finite State Machine

clk : in std_logic ;
reset : in std_logic ;
start : in std_logic ;
cnt : in std_logic_vector (4 downto 0);
initial : out std_logic ;
nxt : out std_logic ;
done : out std_logic
);

end component;

component shiftR

-- Shifter

generic
(
size : integer := 20
);

port
(
data : in

std_logic_vector (size-1 downto 0);

sdata : out
n
);
end component;

begin

: in

std_logic_vector (size-1 downto 0);

std_logic_vector (4 downto 0)

process (clk,newx,newy,newz,z0,nxt,fin)
begin
if (rising_edge(clk)) then
if fin='1' then
xreg <= x0;
yreg <= y0;
zreg <= z0;
cnt<=(others=> '0');
elsif nxt='1' then
xreg <= newx;
yreg <= newy;
zreg <= newz;
cnt <= cnt + '1';
end if;
end if;
end process;

as <= yreg(size-1);

-- MSB of y register

phase <= yreg;

quad <= xreg;
angle <= zreg;
nas <= not(as);

addx : addsubR
register

-- Accumulator for x

generic map
(
size => size
)

port map
(
dataa => xreg,
datab => syreg,
result => newx,
as => as
);

addy : addsubR
register
generic map
(
size => size
)

port map
(
dataa => yreg,
datab => sxreg,
result => newy,
as => nas
);

-- Accumulator for y

addz : addsubR
register

-- Accumulator for z

generic map
(
size => size
)

port map
(
dataa => zreg,
datab => atan,
result => newz,
as => as
);

lut : anglelut
generic map
(
size => size
)

port map
(
index

=> cnt,

atan => atan

);

state_mach : fsmR
port map
(
clk => clk,
reset => reset,
start => start,
cnt => cnt,
initial => fin,
nxt => nxt,
done => done
);

shiftx : shiftR

-- Shifting x value

generic map
(
size => size
)

port map
(
data => xreg,
sdata => sxreg,
n
);

=> cnt

shifty : shiftR

-- Shifting y value

generic map
(
size => size
)

port map
(
data => yreg,
sdata => syreg,
n

=> cnt

);

end arch;

Lookup table

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;

entity anglelut is

generic
(

size : positive := 20
);
port
(
index

: in std_logic_vector (4 downto 0);

atan

: out std_logic_vector (size-1 downto 0)

);

end anglelut ;

architecture table of anglelut Is

signal tinfo : std_logic_vector(19 downto 0);

begin

atan <= tinfo;

process(index)
begin

case index is
when "00000" => tinfo <= X"3243F"; -- 45
when "00001" => tinfo <= X"1DAC6"; -- 26.565
when "00010" => tinfo <= X"0FADB"; -- 14.036
when "00011" => tinfo <= X"07F56"; -- 7.125

when "00100" => tinfo <= X"03FEA"; -- 3.576

when "00101" => tinfo <= X"01FFD"; -- 1.789
when "00110" => tinfo <= X"00FFF"; -- 0.8951
when "00111" => tinfo <= X"007FF"; -- 0.4476
when "01000" => tinfo <= X"003FF"; -- 0.2238
when "01001" => tinfo <= X"001FF"; -- 0.1119
when "01010" => tinfo <= X"000FF"; -- 0.0559
when "01011" => tinfo <= X"0007F"; -- 0.0279
when "01100" => tinfo <= X"0003F"; -- 0.0139
when "01101" => tinfo <= X"0001F"; -- 0.00699
when "01110" => tinfo <= X"0000F"; -- 0.00349
when "01111" => tinfo <= X"00007"; -- 0.00174
when "10000" => tinfo <= X"00003"; -- 0.00087
when "10001" => tinfo <= X"00001"; -- 0.00043
when "10010" => tinfo <= X"00000"; -- 0.00021
when "10011" => tinfo <= X"00000"; -- 0.00010
when others => tinfo <= "--------------------";

end case;
end process;
end table;