Digital Fundamentals Digital Fundamentals

DIGITAL
U
COPYRIGHT ©

No part of this book may be reproduced or

FUNDAMENTALS
U
transmitted in any form or by any means, electronic
or mechanical, without permission in writing from
the authors and publishers.
(FIRST EDITION)
Edition
For

B-TECH &Engineering Students

By
EDITION … 2008
Engr. Waqas Naeem PRICE … Rs. 175/-
BS Computer Engg. (SSUET)
ME C&SP (UIT)

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Digital Fundamentals Digital Fundamentals

PREFACE
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TABLE OF CONTENTS
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FIRST EDITION
S# TOPIC PAGE#
The book has been designed for B-Tech & Engineering 1 Number Systems 7 –17
students of the Universities & Institutes of Pakistan. It 1.1 Types 7
covers the specific material required to have a basic 1.2 Conversion between numeral systems 7
knowledge of Logic Designing & Theory. The author has 1.2.1 Decimal 7
made an attempt to present the material in a simple, clear 1.2.2 Hexa-Decimal 11
and straightforward manner. Exercises are given at the 1.2.3 Octal 13
end of each section. Students are urged to grapple with
1.2.4 Practice 16
these exercises for acquiring solid understanding and
insight of the subject. 2 Binary Arithmetic 18—30
2.1 Addition 18
I wish to express my infinite gratitude to my family 2.2 Subtraction 20
members who encourages me to achieve this valuable 2.3 Multiplication 20
target. I am responsible for the mistakes and misprints 2.4 Division 21
that might have been left unnoticed. Thanks are also due 2.5 Boolean Algebra 23
to Mr. Riaz Ahmed (HOD Tech. IIHE) who took pains 2.6 Practice 30
for the publication of this book. 3 Logic Gates 31—37
3.1 AND Gate 32
Suggestions for further improvements will be gratefully 3.2 OR Gate 32
acknowledged. 3.3 NOT Gate 33
3.4 NAND Gate 34
KARACHI AUTHOR 3.5 NOR Gate 34
3.6 XOR Gate 35
JUNE, 2008 3.7 XNOR Gate 36
3.8 Summary Truth Table 37

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Digital Fundamentals Digital Fundamentals

4 Combinations of Logic Gates 38—44 8.2 RS NAND 72

4.1 Function of Combination of Logic Gates 38 8.3 JK Flip Flop 74
4.2 Substitution of Alternate Gates 39 8.4 Data Latch 76
4.3 Alternate Gate Building NOR/NAND Gates 40 8.5 Toggle Latch 77
4.3.1 NAND Gate Equivalent 41 9 MUX & DE-MUX 79—81
4.4 Examples 42 9.1 MUX 79
4.5 Practice 44 9.2 DE-MUX 80
5 Circuit, Expression, Truth Table & 45—52
Conditions
5.1 Gates Boolean Expression Representations 45
5.2 Boolean Expression 45
5.3 Truth Table 48
5.4 Circuit Building with Conditions 49
5.5 Practice 52
6 Adder 53—54
6.1 Half Adder 53
6.2 Full Adder 54
7 Karnaugh Map 55—63
7.1 Introduction 55
7.2 K-Map Representation 55
7.3 Minimization Using K-Map 57
7.4 Grouping Minterms 59
7.5 Folding Groups 60
7.6 Incompletely Specified Function 65
7.7 Populating Maps Using 0’s versus 1’s 67
7.8 Practice 69
8 Latches 70—78
8.1 RS NOR 70

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Digital Fundamentals Digital Fundamentals

For example, 11810, in binary, are:

B B

1. NUMBER SYSTEMS
U U

Operation Remainder

1.1 Types
T

118 ÷ 2 = 59 0

There are four (4) types of number systems used in

computer systems to interpret data in different modes, 59 ÷ 2 = 29 1
listed below:

1. Binary Æ 0&1 29 ÷ 2 = 14 1
2. Octal Æ 0,1,2,3,4,5,6 & 7
3. Decimal Æ 0,1,2,3,4,5,6,7,8 & 9
4. Hexadecimal Æ 0,1,2,3,4,5,6,7,8,9,A,B,C, 14 ÷ 2 = 7 0
D, E & F

1.2 Conversion to and from other numeral 7÷2=3 1

systems

1.2.1 Decimal 3÷2=1 1

To convert from a base-10 integer numeral to its base-2

(binary) equivalent, the number is divided by two, and 1÷2=0 1
the remainder is the least-significant bit. The (integer)
result is again divided by two; its remainder is the next
most significant bit. This process repeats until the result
of further division becomes zero.

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Digital Fundamentals Digital Fundamentals

Reading the sequence of remainders from the bottom up

gives the binary numeral 11101102.
T B TB
12 × 2 + 1 = 25 0101101

This method works for conversion from any base, but

there are better methods for bases which are powers of 25 × 2 + 0 = 50 101101
two, such as octal and hexadecimal given below.

To convert from base-2 to base-10 is the reverse 50 × 2 + 1 = 101 01101

algorithm. Starting from the left, double the result and
add the next digit until there are no more. For example to
convert 1100101011012 to decimal:
101 × 2 + 0 = 202 1101
B B

Result Remaining digits

202 × 2 + 1 = 405 101

0 110010101101
405 × 2 + 1 = 811 01

0×2+1=1 10010101101
811 × 2 + 0 = 1622 1

1×2+1=3 0010101101
1622 × 2 + 1 = 3245

3×2+0=6 010101101
The result is 324510.
B B

6 × 2 + 0 = 12 10101101

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Digital Fundamentals Digital Fundamentals

1.2.2 Hexadecimal D 13 1101

E 14 1110
Binary may be converted to and from hexadecimal F 15 1111
somewhat more easily. This is due to the fact that the
radix of the hexadecimal system (16) is a power of the
radix of the binary system (2). More specifically, 16 = 24,
P P

so it takes four digits of binary to represent one digit of To convert a hexadecimal number into its binary
hexadecimal. equivalent, simply substitute the corresponding binary
digits:
The following table shows each hexadecimal digit along
with the equivalent decimal value and four-digit binary 3A16 = 0011 10102
B B B B

sequence: E716 = 1110 01112

B B B B

To convert a binary number into its hexadecimal

equivalent, divide it into groups of four bits. If the
Hexa-Decimal Decimal Binary number of bits isn't a multiple of four, simply insert extra
0 0 0000 0 bits at the left (called padding). For example:
1 1 0001
2 2 0010 10100102 = 0101 0010 grouped with padding =
B B

3 3 0011 5216
B B

4 4 0100 110111012 = 1101 1101 grouped = DD16

B B B B

5 5 0101
6 6 0110 To convert a hexadecimal number into its decimal
7 7 0111 equivalent, multiply the decimal equivalent of each
8 8 1000 hexadecimal digit by the corresponding power of 16 and
9 9 1001 add the resulting values:
A 10 1010
B 11 1011
C 12 1100

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Digital Fundamentals Digital Fundamentals

C0E716 = (12 × 163) + (0 × 162) + (14 × 161) + (7

B B P P P P P P

× 160) = (12 × 4096) + (0 × 256) + (14 × 16) + (7

P P
3 011
× 1) = 49,38310 B B

4 100

1.2.3 Octal
5 101
Binary is also easily converted to the octal numeral
system, since octal uses a radix of 8, which is a power of
two (namely, 23, so it takes exactly three binary digits to
P P

6 110
represent an octal digit). The correspondence between
octal and binary numerals is the same as for the first
eight digits of hexadecimal in the table above. Binary 7 111
000 is equivalent to the octal digit 0, binary 111 is
equivalent to octal 7, and so on.
Converting from octal to binary proceeds in the same
fashion as it does for hexadecimal:
Octal Binary
658 = 110 1012
B B B B

0 000 178 = 001 1112

B B B B

1 001 And from binary to octal:

1011002 = 101 1002 (grouped) = 548

B B B B B B

2 010
100112 = 010 0112 (grouped with padding) = 238
B B B B B B

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Digital Fundamentals Digital Fundamentals

And from octal to decimal:

Practice
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1 0
658 = (6 × 8 ) + (5 × 8 ) = (6 × 8) + (5 × 1) = 5310
B B P P P P B B

1. Conversion between Base-2 & Base-8:

B B
2
1278 = (1 × 8 ) + (2 × 8 ) + (7 × 8 ) = (1 × 64) +
P P
1
P P
0
P P
• (1001010100001111010101)2 = (
B B )8
• (101001010100101110101000111)2= ( )8
(2 × 8) + (7 × 1) = 8710 B B • (7361421)8 = ( )2
• (276314)8 = ( )2

2. Conversion between Base-2 & Basae-10:

• (111000101010)2 = ( )10
• (1010000111101)2 = ( )10
• (293)10 = ( )2
• (352)10 = ( )2

3. Conversion between Base-2 & Base-16:

• (101000010101010101111010101110100
0)2 = ( )16
• (101010010101010000011110101000010
11)2 = ( )16
• (9AE5F)16 = ( )2
• (ACD106E)16 = ( )2

4. Conversion between Base-8 & Base-10:

• (4723)8 = ( )10
• (71062)8 = ( )10
• (397)10 = ( )8
• (219)10 = ( )8

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Digital Fundamentals Digital Fundamentals

5. Conversion between Base-8 & Base-16: 2. BINARY ARITHMETIC

T T

• (2374)8 = ( )16
• (17260)8 = ( )16
Arithmetic in binary is much like arithmetic in other
• (A912F)16 = ( )8
numeral systems. Addition, subtraction, multiplication,
• (19EDF)16 = ( )8 and division can be performed on binary numerals.
6. Conversion between Base-10 and Base-16:
• (317)10 = ( )16
2.1 Addition
• (2319)10 = ( )16
• (AFC1)16 = ( )10
• (10DCB)16 = ( )10

The circuit diagram for a binary half adder, which adds

two bits together, producing sum and carry bits.

The simplest arithmetic operation in binary is addition.

Adding two single-digit binary numbers is relatively
simple:

0+0=0
0+1=1
1+0=1
1 + 1 = 10 (carry: 1)

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Digital Fundamentals Digital Fundamentals

Adding two "1" values produces the value "10" (spoken and a 1 is written in the bottom row. Proceeding like this
as "one-zero"), equivalent to the decimal value 2. This is gives the final answer 1001002 (36 decimal).
B B

similar to what happens in decimal when certain single-

digit numbers are added together; if the result equals or 2.2 Subtraction
exceeds the value of the radix (10), the digit to the left is
incremented: Subtraction works in much the same way:
HTU UTH

5 + 5 = 10 0−0=0
7 + 9 = 16 0 − 1 = 1 (with borrow)
1−0=1
This is known as carrying in most numeral systems. 1−1=0
When the result of an addition exceeds the value of the
radix, the procedure is to "carry the one" to the left, One binary numeral can be subtracted from another as
adding it to the next positional value. Carrying works the follows:
same way in binary:
* * * * (starred columns are borrowed from)
1 1 1 1 1 (carry) 1101110
01101 − 10111
+ 10111 ----------------
------------- =1010111
=100100
2.3 Multiplication
In this example, two numerals are being added together:
011012 (13 decimal) and 101112 (23 decimal). The top
B B B B

Multiplication in binary is similar to its decimal

row shows the carry bits used. Starting in the rightmost counterpart. Two numbers A and B can be multiplied by
column, 1 + 1 = 102. The 1 is carried to the left, and the 0
B B

partial products: for each digit in B, the product of that

is written at the bottom of the rightmost column. The digit in A is calculated and written on a new line, shifted
second column from the right is added: 1 + 0 + 1 = 102 B B

leftward so that its rightmost digit lines up with the digit

again; the 1 is carried, and 0 is written at the bottom. The in B that was used. The sum of all these partial products
third column: 1 + 1 + 1 = 112. This time, a 1 is carried,
B B

gives the final result.

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Digital Fundamentals Digital Fundamentals

Since there are only two digits in binary, there are only 1012 goes into the first three digits 1102 of the dividend
B B B B

two possible outcomes of each partial multiplication: one time, so a "1" is written on the top line. This result is
multiplied by the divisor, and subtracted from the first
• If the digit in B is 0, the partial product is also 0 three digits of the dividend; the next digit (a "1") is
• If the digit in B is 1, the partial product is equal to included to obtain a new three-digit sequence:
A
1
For example, the binary numbers 1011 and 1010 are __________
101 |11011
multiplied as follows: − 101 U U

011
1 0 1 1 (A)
× 1 0 1 0 (B)
---------
The procedure is then repeated with the new sequence,
0 0 0 0 ← Corresponds to a zero in B continuing until the digits in the dividend have been
+ 1 0 1 1 ← Corresponds to a one in B exhausted:
+ 0000
+1011 101
--------------- __________
=1101110 101 |11011
− 101 U U

2.4 Division 011

− 000 U U

111
Binary division is again similar to its decimal − 101 U U

counterpart: 10

__________ Thus, the quotient of 110112 divided by 1012 is 1012, as

B B B B B B

101 |11011 shown on the top line, while the remainder, shown on the
bottom line, is 102. In decimal, 27 divided by 5 is 5, with
Here, the divisor is 1012, or 5 decimal, while the
B B

B B

a remainder of 2.
dividend is 110112, or 27 decimal. The procedure is the
B B

same as that of decimal long division; here, the divisor

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Digital Fundamentals Digital Fundamentals

2.5 Boolean Algebra

• Digital computers contain circuits that implement

Boolean functions.
• The simpler we can make a Boolean function, the
smaller the circuit that will result.
• Simpler circuits are cheaper to build, consume
3. Our last group of Boolean identities is perhaps the
less power, and run faster than complex circuits.
most useful. If you have studied set theory or formal
• With this in mind, we always want to reduce our
logic, these laws are also familiar to you.
Boolean functions to their simplest form.
• There are a number of Boolean identities that
help us to do this.

1. Most Boolean identities have an AND (product) form

as well as an OR (sum) form. We give our identities
using both forms. Our first group is rather intuitive:

Example: We can use Boolean identities to simplify the

function: as follows:

2. Our second group of Boolean identities should be

familiar to you from your study of algebra:

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Digital Fundamentals Digital Fundamentals

2. Simplify: ¬(AB)(¬A + B)(¬B + B)

Expression
U U Rule(s) Used
U U

¬(AB)(¬A + B)(¬B + B) Original Expression

¬(AB)(¬A + B) Compliment law,
Identity law.
(¬A + ¬B)(¬A + B) DeMorgan's Law
Here are some examples of Boolean algebra ¬A + (¬B)B Distributive law. This
simplifications. Each line gives a form of the expression, step uses the fact that or
and the rule or rules used to derive it from the previous distributes over and. It
one. Generally, there are several ways to reach the result. can look a bit strange
As before, I use ¬A to denote not A. since addition does not
distribute over
multiplication.
¬A Compliment, Identity.
1. Simplify: C + ¬(BC)

Expression
U U Rule(s) Used
U U

C + ¬(BC) Original Expression

C + (¬B + ¬C) DeMorgan's Law.
3. Simplify: (A + C)(AD + A(¬D)) + AC + C
(C + ¬C) + ¬B Commutative, Associative Laws.
T + ¬B Compliment Law. Expression
U U Rule(s) Used
U U

T Identity Law. (A + C)(AD + A(¬D)) + AC + C Original

Expression

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Digital Fundamentals Digital Fundamentals

(A + C)A(D + ¬D) + AC + C Distributive. used twice.

(A + C)A + AC + C Compliment, (¬A)B + (B + A)A + (B + A)(¬B) Compliment,
Identity. then Identity.
(Strictly
A((A + C) + C) + C Commutative,
speaking, we
Distributive.
also used the
A(A + C) + C Associative, Commutative
Idempotent. Law for each
AA + AC + C Distributive. of these
applications.)
A + (A + T)C Idempotent,
Identity, (¬A)B + BA + AA + B(¬B) + Distributive,
Distributive. A(¬B) two places.

A+C Identity, twice. (¬A)B + BA + A + A(¬B) Idempotent

(for the A's),
then
4. You can also use distribution of or over and Compliment
starting from A(A+C)+C to reach the same result and Identity
by another route. to remove
5. Simplify: (¬A)(A + B) + (B + AA)(A + ¬B) B(¬B).
(¬A)B + AB + AT + A(¬B) Commutative
Expression
U U Rule(s) Used
U U

, Identity;
(¬A)(A + B) + (B + AA)(A + ¬B) Original setting up for
Expression the next step.
(¬A)A + (¬A)B + (B + A)A + (B Idempotent (¬A)B + A(B + T + ¬B) Distributive.
+ A)(¬B) (AA to A), (¬A)B + A Identity,
then twice
Distributive,

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Digital Fundamentals Digital Fundamentals

(depending Practice
how you
U U

count it).
1. Addition
A + (¬A)B Commutative • 1011101 + 1110101 =
. • 1111010101 + 1010000101 =
(A + ¬A)(A + B) Distributive. • 00010101 + 1001010100 =
• 1011001111 + 10001010100 =
A+B Compliment,
2. Subtraction
Identity.
• 11100111 – 1101 =
• 10011101010 – 100011 =
• 11010101 – 100110 =
• 1011001100 – 1110001 =
3. Multiplication
• 10100001 x 11011 =
• 11101010 x 1010 =
• 11010001 x 100110 =
• 111001110 x 11010 =
4. Division
• 1110001100 divide by 110 =
• 10011110010 divide by 100 =
• 110101000111 divide by 101 =
• 100011110100 divide by 1001 =
5. Solve the Boolean expression by using
different laws:
• {A(¬A+C)&(B+¬B)}
• [{C(A&¬A) & 0} + {C(A+¬C) & B(¬C)}

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Digital Fundamentals Digital Fundamentals

3. LOGIC GATES
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3.1 AND gate

The AND gate is so named because, if 0 is called "false"

Keep in mind that computers work on an electrical flow
and 1 is called "true," the gate acts in the same way as
where a high voltage is considered a 1 and a low voltage
the logical "and" operator. The following illustration and
is considered a 0. Using these highs and lows, data are
table show the circuit symbol and logic combinations for
represented. Electronic circuits must be designed to
an AND gate. (In the symbol, the input terminals are at
manipulate these positive and negative pulses into
left and the output terminal is at right.) The output is
meaningful logic.
"true" when both inputs are "true." Otherwise, the output
is "false."
Logic gates are the building blocks of digital circuits.
Combinations of logic gates form circuits designed with
specific tasks in mind. For example, logic gates are
combined to form circuits to add binary numbers
(adders), set and reset bits of memory (flip flops),
multiplex multiple inputs, etc. Input 1 Input 2 Output

A logic gate is an elementary building block of a digital 0 0 0

circuit. Most logic gates have two inputs and one output. 0 1 0
At any given moment, every terminal is in one of the two
1 0 0
binary conditions low (0) or high (1), represented by
different voltage levels. The logic state of a terminal can, 1 1 1
and generally does, change often, as the circuit processes
data. In most logic gates, the low state is approximately
zero volts (0 V), while the high state is approximately
3.2 OR gate
five volts positive (+5 V).
The OR gate gets its name from the fact that it behaves
after the fashion of the logical inclusive "or." The output
There are seven basic logic gates: AND, OR, XOR,
is "true" if either or both of the inputs are "true." If both
NOT, NAND, NOR, and XNOR.
inputs are "false," then the output is "false."

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3.4 NAND gate

The NAND gate operates as an AND gate followed by a

NOT gate. It acts in the manner of the logical operation
Input 1 Input 2 Output
"and" followed by negation. The output is "false" if both
0 0 0 inputs are "true." Otherwise, the output is "true."
0 1 1
1 0 1
1 1 1
Input 1 Input 2 Output
3.3 Inverter or NOT gate 0 0 1
A logical inverter, sometimes called a NOT gate to 0 1 1
differentiate it from other types of electronic inverter 1 0 1
devices, has only one input. It reverses the logic state.
1 1 0

3.5 NOR gate

Input Output The NOR gate is a combination OR gate followed by an

inverter. Its output is "true" if both inputs are "false."
1 0 Otherwise, the output is "false."
0 1

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Digital Fundamentals Digital Fundamentals

Input 1 Input 2 Output 3.7 XNOR gate

0 0 1 The XNOR (exclusive-NOR) gate is a combination XOR
0 1 0 gate followed by an inverter. Its output is "true" if the
inputs are the same and "false" if the inputs are different.
1 0 0
1 1 0

3.6 XOR gate

Input 1 Input 2 Output
The XOR (exclusive-OR) gate acts in the same way as
the logical "either/or." The output is "true" if either, but 0 0 1
not both, of the inputs are "true." The output is "false" if 0 1 0
both inputs are "false" or if both inputs are "true."
Another way of looking at this circuit is to observe that 1 0 0
the output is 1 if the inputs are different, but 0 if the 1 1 1
inputs are the same.
Using combinations of logic gates, complex operations
can be performed. In theory, there is no limit to the
number of gates that can be arrayed together in a single
device. But in practice, there is a limit to the number of
Input 1 Input 2 Output gates that can be packed into a given physical space.
Arrays of logic gates are found in digital integrated
0 0 0 circuits (ICs). As IC technology advances, the required
0 1 1 physical volume for each individual logic gate decreases
and digital devices of the same or smaller size become
1 0 1 capable of performing ever-more-complicated operations
1 1 0 at ever-increasing speeds.

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Digital Fundamentals Digital Fundamentals

4. COMBINATIONS OF
U

3.8 Summary truth tables

LOGIC GATES
The summary truth tables below show the output states
Logic gates can be combined to produce more complex
for all types of 2-input and 3-input gates.
functions. They can also be combined to substitute one
type of gate for another.
Summary for all 2-input gates For example to produce an Input A Input B Output Q
Inputs Output of each gate output Q which is true only
when input A is true and 0 0 0
A B AND NAND OR NOR EX-OR EX-NOR input B is false, as shown in 0 1 0
the truth table on the right, 1 0 1
0 0 0 1 0 1 0 1
we can combine a NOT gate
1 1 0
0 1 0 1 1 0 1 0 and an AND gate like this:
1 0 0 1 1 0 1 0

1 1 1 0 1 0 0 1

Summary for all 3-input gates

Inputs Output of each gate

A B C AND NAND OR NOR

Q = A AND NOT B
0 0 0 0 1 0 1

0 0 1 0 1 1 0

0 1 0 0 1 1 0 4.1 Working out the function of a

0 1 1 0 1 1 0 combination of gates
1 0 0 0 1 1 0
Truth tables can be used to work out the function of a
1 0 1 0 1 1 0
combination of gates.
1 1 0 0 1 1 0
1 1 1 1 0 1 0

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Digital Fundamentals Digital Fundamentals

For example the truth table on Inputs Outputs reduce the number of gate inputs or substitute one type of
the right show the intermediate gate for another.
outputs D and E as well as the A B C D E Q
final output Q for the system 0 0 0 1 0 1 Reducing the number of
shown below. 0 0 1 1 0 1 inputs
0 1 0 0 0 0 The number of inputs to a gate can be
reduced by connecting two (or more) inputs together.
0 1 1 0 1 1
The diagram shows a 3-input AND gate operating as a 2-
1 0 0 0 0 0 input AND gate.
1 0 1 0 0 0
1 1 0 0 0 0
Making a NOT gate from a
1 1 1 0 1 1 NAND or NOR gate
Reducing a NAND or NOR gate to
just one input creates a NOT gate. The diagram shows
this for a 2-input NAND gate.
D = NOT (A OR B)
E = B AND C
Q = D OR E = (NOT (A OR B)) OR (B AND C)
4.3 Any gate can be built from NAND or NOR
gates
As well as making a NOT gate, NAND or NOR gates
4.2 Substituting one type of gate for another can be combined to create any type of gate! This enables
a circuit to be built from just one type of gate, either
Logic gates are available on ICs which usually contain NAND or NOR. For example an AND gate is a NAND
several gates of the same type, for example four 2-input gate then a NOT gate (to undo the inverting function).
NAND gates or three 3-input NAND gates. This can be Note that AND and OR gates cannot be used to create
wasteful if only a few gates are required unless they are other gates because they lack the inverting (NOT)
all the same type. To avoid using too many ICs you can function.

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Digital Fundamentals Digital Fundamentals

To change the type of gate, such as changing OR to

AND, you must do three things:
OR
• Invert (NOT) each input.
• Change the gate type (OR to AND, or AND to
OR)
• Invert (NOT) the output.
NOR
For example an OR gate can be built from NOTed inputs
fed into a NAND (AND + NOT) gate.

4.3.1 NAND gate equivalents

4.4 Substituting gates in an example logic
The table below shows the NAND gate equivalents of
NOT, AND, OR and NOR gates: system
The original system has 3 different gates: NOR, AND
and OR. This requires three ICs (one for each type of
Gate Equivalent in NAND gates gate). To re-design this system using NAND gates only
begin by replacing each gate with its NAND gate
NOT equivalent, as shown in the diagram below.

AND

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Digital Fundamentals Digital Fundamentals

Practice
U U

1. What is the NAND equivalent of NOR gate?

2. Construct an equivalent circuit of XOR gate by using
NAND gate.
3. Construct an equivalent circuit of Half Adder by
using NAND gate.
Then simplify the system by deleting adjacent pairs of
NOT gates (marked X above). This can be done because
the second NOT gate cancels the action of the first.

The final system is shown below. It has five NAND

gates and requires two ICs (with four gates on each IC).
This is better than the original system which required
three ICs (one for each type of gate).

Substituting NAND (or NOR) gates does not always

increase the number of gates, but when it does (as in this
example) the increase is usually only one or two gates.
The real benefit is
reducing the number of
ICs required by using just
one type of gate.

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Digital Fundamentals Digital Fundamentals

5. CIRCUIT, EQUATION,
U

TRUTH TABLE &

CONDITIONS

5.1 GATES REPRESENTATIONS

In this topic we will discuss how to represent any circuit
in a Boolean expression or vice versa. For this concern,
primarily we should know the symbolic representation of
each operation i.e. OR, AND etc. Following are the
different symbols to represent different gates or
Considering the above circuitry, break it into the gate
operations:
level circuits. What I mean to say that firstly write the
expression for the NOR gate, secondly for the AND gate
1. AND Æ “&” “x” “.”
and then finally for an OR gate with results the final
2. OR Æ “|” “+”
output. See below for the specific expression of all gates:
3. N OT Æ “¬” “’”
NOR Æ (A + B)’ Æ D
The above mentioned symbols are for the basic gates and
AND Æ (B & C) Æ E
we can use it for the derived gates as well by the
OR Æ (D + E) Æ (A+B)’ + (B&C) -
combination of different symbols.
-- (i)
5.2 BOOLEAN EXPRESSION Now we succeeded to achieve the final Boolean equation
for the given circuit in Eq. (i). Let’s see even more
Now proceeding to the Boolean expression, in the first complex logic circuit to achieve its Boolean expression:
step we are expressing a simple logic circuit into its
Boolean expression.

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Digital Fundamentals Digital Fundamentals

Here we achieve the final and complex expression of the

given logic circuit in Eq. (ii). The point should be
reviewed in this expression is [(A+B)’&C’] which
should be NOTed two times as per circuit. As we can
remind that inverting the original signal two times will
give you the original signal again which reflects that two
times inversion will not effect the Boolean expression, so
it can be eliminated.

5.3 TRUTH TABLE

The core motive to design any circuit is to achieve the
required pattern of output for any productive use. Output
pattern of any circuit is the major concern for any
designer.

Boolean expression for each gate is given below:

NOR Æ (A + B)’ Æ G
AND Æ (C & D) Æ H
NAND Æ (E & F)’ Æ I
NAND Æ (G & C’)’ Æ J
NOR Æ (C’ + H)’ Æ K
OR Æ (E’ + I) Æ M
NAND Æ (J & K & M & E’)’
Æ {[(A+B)’&C’] & [C’+(C&D)] & [E’+ (E & F)’] &
E’}---- (ii)

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Again the same simple circuit (It might be a traditional (0 or 1). For example we have the following condition to
one …Cheers). Number of possible combination for the construct a circuit for a specified output:
given circuit can be calculated by the formula:
A=B=1; C=0
n
Number of possible combinations = 2
P P O/p = 1

Where “n” is the total number of inputs in the circuit Now we have to precisely examine the input and the
which is “3” in this case (A, B & C). Now the total logical gates we have to satisfy the condition of input. It
possible combinations for the input are 8 (23) and they
P P is known that the functionality of AND gate is that it
are stated below with their respective output: provides logical output HIGH when all the inputs are
HIGH. Leading with this statement we can satisfy the
S# A B C Q conditions for input A and B by using AND gate. Now
1 0 0 0 1 proceeding to the third and last input condition which is
2 0 0 1 1 LOW, we already knows that out of the previous AND
3 0 1 0 0 gate will be HIGH in only condition when A and B will
4 0 1 1 1 be HIGH. Then we should have any gate which checks
5 1 0 0 0 the output of AND and input C. look into the below
6 1 0 1 0 circuit:
7 1 1 0 0
8 1 1 1 1

5.4 CONDITIONS
By verifying the above circuit, we come to know that it
also satisfies our remaining condition. Now the final
As stated earlier that the major concern to design any circuit we achieve is:
logical circuit is to achieve the specific pattern of output.
Here we will discuss how to create a circuit when the
conditions of inputs are given to get any particular output

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Practice
U U

1. Find the circuit on behalf of the following

Boolean expressions:
a. {(¬A+B) & (B&¬C)}
b. [{(A+B+¬C) & (¬B &A)} + (A&¬D)]
And the required truth table is:
c. {(¬C&A) + ¬(¬B&C)}
S# A B C o/p 2. Find the Truth Tables of the circuits constructed
1 0 0 0 0 in the above part (1).
2 0 0 1 0 3. Construct circuits which fulfills the following
3 0 1 0 0 condition with required output pattern:
a. Circuit#1
4 0 1 1 0
5 1 0 0 0 i. A=B=0
6 1 0 1 0 ii. C=1
7 1 1 0 1
iii. DE= 00,01 & 11
8 1 1 1 0
iv. Output should be high on these
You can verify the above truth table by applying all the conditions.
inputs to the constructed circuit. I suppose that you will b. Circuit#2
the same output. i. A=1
ii. BC=00 & 01
iii. Any one condition
a) D= Unspecified
b) EF=10 & 11

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6. ADDERS
U U
6.2 FULL ADDER

The full-adder circuit adds three one-bit binary numbers

6.1 HALF ADDER (C A B) and outputs two one-bit binary numbers, a sum
(S) and a carry (C1). The full-adder is usually a
The half adder is an example of a simple, functional component in a cascade of adders, which add 8, 16, 32,
digital circuit built from two logic gates. The half adder etc. binary numbers. The carry input for the full-adder
adds to one-bit binary numbers (AB). The output is the circuit is from the carry output from the circuit "above"
sum of the two bits (S) and the carry (C). itself in the cascade. The carry output from the full adder
is fed to another full adder "below" itself in the cascade.
Note how the same two inputs are directed to two
different gates. The inputs to the XOR gate are also the If you look closely, you'll see the full adder is simply two
inputs to the AND gate. The input "wires" to the XOR half adders joined by an OR.
gate are tied to the input wires of the AND gate; thus,
when voltage is applied to the A input of the XOR gate,
the A input to the AND gate receives the same voltage. Full Adder Circuit TT
Input Output
ABC S C
Truth
Half Adder Table 0 0 0 0 0
0 0 1 1 0
Input Output
0 1 0 1 0
A B S C 0 1 1 0 1
0 0 0 0 1 0 0 1 0
0 1 1 0 1 0 1 0 1
1 0 1 0 1 1 0 0 1
1 1 0 1 1 1 1 1 1

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7. KARNAUGH MAPS
U

The y column in the truth table shows all the 0 and 1

values associated with the gate's output. Similarly, all of
the output values could be entered into the Karnaugh
7.1 Introduction
map. However, for reasons of clarity, it is common for
only a single set of values to be used, typically the 1s.
Karnaugh maps provide an alternative technique for
Similar maps can be constructed for 3-input and 4-input
representing Boolean functions. For example, consider
functions. In the case of a 4-input map, the values
the Karnaugh map for a 2-input AND gate.
associated with the c and d inputs must also be ordered
as a gray code; that is, ordered in such a way that the
values for adjacent rows vary by only a single bit.

Karnaugh map for a 2-input AND gate.

7.2 Representation
The Karnaugh map comprises a box for every line in the
truth table; the binary values above the boxes are those
associated with the a and b inputs. Unlike a truth table, in
which the input values typically follow a standard binary
sequence (00, 01, 10, 11), the Karnaugh map's input
values must be ordered such that the values for adjacent
Karnaugh maps for 3-input and 4-input functions.
columns vary by only a single bit, for example, 00, 01,
11, and 10. This ordering is known as a gray code, and it
is a key factor in the way in which Karnaugh maps work.

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Digital Fundamentals
7.3 Minimization Using Karnaugh Maps
Karnaugh maps often prove useful in the simplification
and minimization of Boolean functions. Consider an
example 3-input function represented as a black box with
an associated truth table (Figure 3). (Note that the values
assigned to the y output in the truth table were selected
randomly, and have no significance beyond the purposes
of this example.)
Example 3-input function.
The equation extracted from the truth table in sum-of-
products form contains four minterms, one for each of
the 1s assigned to the output. Algebraic simplification
techniques could be employed to minimize this equation,
but this would necessitate every minterm being
compared to each of the others which can be somewhat
time-consuming.
This is where Karnaugh maps enter the game. The 1s
assigned to the map's boxes represent the same minterms
as the 1s in the truth table's output column; however, as
the input values associated with each row and column in
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Digital Fundamentals
the map differ by only one bit, any pair of horizontally or
vertically adjacent boxes corresponds to minterms that
differ by only a single variable. Such pairs of minterms
can be grouped together and the variable that differs can
be discarded (Figure 4).
Karnaugh map minimization of example 3-input function.
In the case of the horizontal group, input a is 0 for both
boxes, input c is 1 for both boxes, and input b is 0 for one
box and 1 for the other. Thus, for this group, changing
the value on b does not affect the value of the output.
This means that b is redundant and can be discarded from
the equation representing this group. Similarly, in the
case of the vertical group, input a is 1 for both boxes,
input b is 0 for both boxes, and input c is 0 for one box
and 1 for the other. Thus, for this group, input c is
redundant and can be discarded.
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Digital Fundamentals
7.4 Grouping Minterms
In the case of a 3-input Karnaugh map, any two
horizontally or vertically adjacent minterms, each
composed of three variables, can be combined to form a
new product term composed of only two variables.
Similarly, in the case of a 4-input map, any two adjacent
minterms, each composed of four variables, can be
combined to form a new product term composed of only
three variables. Additionally, the 1s associated with the
minterms can be used to form multiple groups. For
example, consider a new 3-input function.
Karnaugh map minterms can be used to form multiple groups.
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Digital Fundamentals
7.5 Folding Groups
In addition to the above methods of groups, we can also
make groups by folding the Karnaugh map from
horizontal and vertical center lines. In the results of
folding, the elements overlaps each others can make
relatively larger groups.
Now either fold up the corners or center lines (RED) of
the map below like it is a napkin to make the four cells
physically adjacent.
The four cells above are a group of four because they all
have the Boolean variables B' and D' in common. In
other words, B=0 for the four cells, and D=0 for the four
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Digital Fundamentals
cells. The other variables (A, B) are 0 in some cases, 1 in
other cases with respect to the four corner cells. Thus,
these variables (A, B) are not involved with this group of
four. This single group comes out of the map as one
product term for the simplified result: Out=B'C'
For the K-map below, roll the top and bottom edges into
a cylinder (Horizontal Fold) forming eight adjacent cells.
The above group of eight has one Boolean variable in
common: B=0. Therefore, the one group of eight is
covered by one p-term: B'. The original eight term
Boolean expression simplifies to Out=B'
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Digital Fundamentals
The Boolean expression below has nine p-terms, three of
which have three Booleans instead of four. The
difference is that while four Boolean variable product
terms cover one cell, the three Boolean p-terms cover a
pair of cells each.
The six product terms of four Boolean variables map in
the usual manner above as single cells. The three
Boolean variable terms (three each) map as cell pairs,
which is shown above. Note that we are mapping p-terms
into the K-map, not pulling them out at this point.
For the simplification, we form two groups of eight.
Cells in the corners are shared with both groups. This is
fine. In fact, this leads to a better solution than forming a
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Digital Fundamentals
group of eight and a group of four without sharing any
cells. Final Solution is Out=B'+D'
Below we map the unsimplified Boolean expression to
the Karnaugh map.
Above, three of the cells form into groups of two cells. A
fourth cell cannot be combined with anything, which
often happens in "real world" problems. In this case, the
Boolean p-term ABCD is unchanged in the
simplification process. Result: Out=
B'C'D'+A'B'D'+ABCD
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Digital Fundamentals
Often times there are more than one minimum cost
solution to a simplification problem. Such is the case
illustrated below.
Both results above have four product terms of three
Boolean variables each. Both are equally valid minimal
cost solutions. The difference in the final solution is due
to how the cells are grouped as shown above. A minimal
cost solution is a valid logic design with the minimum
number of gates with the minimum number of inputs.
Below we map the unsimplified Boolean equation as
usual and form a group of four as a first simplification
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Digital Fundamentals
step. It may not be obvious how to pick up the remaining
cells.
Pick up three more cells in a group of four, center above.
There are still two cells remaining. The minimal cost
method to pick up those is to group them with
neighboring cells as groups of four as at above right.
On a cautionary note, do not attempt to form groups of
three. Groupings must be powers of 2 that is, 1, 2, 4, 8...
7.6 Incompletely Specified Functions
In certain cases a function may be incompletely
specified; that is, the output may be undefined for some
of the input combinations. If the designer knows that
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Digital Fundamentals
certain input combinations will never occur, then the
value assigned to the output for these combinations is
irrelevant.
Alternatively, for some input combinations the designer
may simply not care about the value on the output. In
both cases, the designer can represent the output values
associated with the relevant input combinations as
question marks in the map.
Karnaugh map for an incompletely specified function.
The ? characters indicate don't care states which can be
considered to represent either 0 or 1 values at the
designer's discretion. It should be noted that many
electronics references use X characters to represent don't
care states. Unfortunately, this may lead to confusion as
design tools such as logic simulators use X characters to
represent don't know states. Unless otherwise indicated,
this book uses? And X to represent doesn’t care and don't
know states respectively.
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7.7 Populating Maps Using 0s Versus 1s
When a Karnaugh map is populated using the 1s
assigned to the truth table's output, the resulting Boolean
expression is extracted from the map in sum-of-products
form. As an alternative, the Karnaugh map can be
populated using the 0s assigned to the truth table's
output. In this case, groupings of 0's are used to generate
expressions in product-of-sums format.
Karnaugh maps are most often used to represent 3-input
and 4-input functions. It is possible to create similar
maps for 5-input and 6-input functions, but these maps
can become unwieldy and difficult to use. The Karnaugh
technique is generally not considered to have any
application for functions with more than six inputs.

Although the sum-of-products and product-of-sums

expressions appear to be somewhat different, they do
produce identical results. The expressions can be shown
to be equivalent using algebraic means, or by
constructing truth tables for each expression and
comparing the outputs.

Karnaugh maps populated using 0s versus 1s.

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Practice 8. LATCHES
U

Find the simplified SOP and POS equations by using

the different condition given below:
1. When the outputs are high on the following 8.1 RS NOR LATCH
inputs: 0, 2, 3, 4, 6, 8, A, B & C
2. With the given un-simplified POS equation: While most of our demonstration circuits use
O/p= (¬A+¬B+¬C) & (¬A+¬B+C) & (¬A+B+C) NAND gates, the same functions can also be
& (A+B+C) performed using NOR gates. A few adjustments
3. Truth Table given: must be made to allow for the difference in the logic
function, but the logic involved is quite similar.
A B C D O/P
0 0 0 0 0 The circuit shown below is a basic NOR latch. The
0 0 0 1 1 inputs are generally designated "S" and "R" for
0 0 1 0 0 "Set" and "Reset" respectively. Because the NOR
0 0 1 1 0 inputs must normally be logic 0 to avoid overriding
0 1 0 0 0 the latching action, the inputs are not inverted in this
0 1 0 1 1 circuit. The NOR-based latch circuit is:
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1 For the NOR latch circuit, both inputs should normally
1 1 1 0 0 be at a logic 0 level. Changing an input to logic 1 level
1 1 1 1 1 will force that output to logic 0. The same logic 0 will

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Digital Fundamentals Digital Fundamentals

also be applied to the second input of the other NOR confusing when you first try to deal with NOR-
gate, allowing that output to rise to logic 1 level. This based circuits.
in turn feeds back to the second input of the original
gate, forcing its output to remain at logic 0 even after S R Q n+1B B

the external input is removed. 0 0 Qn B B

0 1 Reset
Applying another logic 1 input to the same gate will
have no further effect on this circuit. However, 1 0 Set
applying logic 1 to the other gate will cause the same 1 1 Undefined
reaction in the other direction, thus changing the state
of the latch circuit the other way. 8.2 RS NAND Latch
T T

Note that it is forbidden to have both inputs at logic
1 level at the same time. That state will force both
outputs to logic 0, overriding the feedback latching
action. In this condition, whichever input goes to
logic 0 first will lose control, while the other input
(still at logic 1) controls the resulting state of the
latch. If both inputs go to logic 0 simultaneously,
the result is a "race" condition, and the final state of
the latch cannot be determined ahead of time.
One problem with the basic RS NOR latch is that
the input signals actively drive their respective
outputs to a logic 0, rather than to a logic 1. Thus,
the S input signal is applied to the gate that
produces the Q' output, while the R input signal is
applied to the gate that produces the Q output. The
circuit works fine, but this reversal of inputs can be
In order for a logical circuit to "remember" and
retain its logical state even after the controlling
input signal(s) have been removed, it is necessary
for the circuit to include some form of feedback. We
might start with a pair of inverters, each having its
input connected to the other's output. The two
outputs will always have opposite logic levels.
The problem with this is that we don't have any
additional inputs that we can use to change the logic
states if we want. We can solve this problem by
replacing the inverters with NAND or NOR gates,
and using the extra input lines to control the circuit.
The circuit shown below is a basic NAND latch.
The inputs are generally designated "S" and "R" for
"Set" and "Reset" respectively. Because the NAND

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inputs must normally be logic 1 to avoid affecting
the latching action, the inputs are considered to be
inverted in this circuit.
The outputs of any single-bit latch or memory are
traditionally designated Q and Q'. In a commercial
latch circuit, either or both of these may be available
for use by other circuits. In any case, the circuit
itself is:
reaction in the other direction, thus changing the state
of the latch circuit the other way.
Note that it is forbidden to have both inputs at a
logic 0 level at the same time. That state will force
both outputs to logic 1, overriding the feedback
latching action. In this condition, whichever input
goes to logic 1 first will lose control, while the other
input (still at logic 0) controls the resulting state of
the latch. If both inputs go to logic 1
simultaneously, the result is a "race" condition, and
the final state of the latch cannot be determined
ahead of time.

S R Q n+1
B B

0 0 Undefined
For the NAND latch circuit, both inputs should 0 1 Set
normally be at logic 1 level. Changing an input to a 1 0 Reset
logic 0 level will force that output to logic 1. The same 1 1 Qn
logic 1 will also be applied to the second input of the
B B

other NAND gate, allowing that output to fall to a

logic 0 level. This in turn feeds back to the second 8.3 J-K Flip Flop
T T

input of the original gate, forcing its output to remain

at logic 1.
Applying another logic 0 input to the same gate will
have no further effect on this circuit. However,
applying logic 0 to the other gate will cause the same
To prevent any possibility of a "race" condition
occurring when both the S and R inputs are at logic 1 we
construct JK Flip Flop. The basic J-K Flip-flop is shown

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J K Q Q’
0 0 No change
0 1 0 1
1 0 1 0
1 1 Toggle

8.4 D Latch
T T

One very useful variation on the RS latch circuit is

the Data latch, or D latch as it is generally called.
As shown in the logic diagram below, the D latch is
constructed by using the inverted S input & the R
input signal. The single remaining input is
Like the R-S flip-flop the outputs follow the inputs when designated "D" to distinguish its operation from
the Clk is logic, but there are two inputs, traditionally other types of latches. It makes no difference that
labeled J and K. If J and K are different then the output Q the R input signal is effectively clocked twice, since
takes the value of J at the next clock edge. If J and K are the CLK signal will either allow the signals to pass
both low then no change occurs. If J and K are both high both gates or it will not.
at the clock edge then the output will toggle from one
state to the other. It can perform the functions of the R-S
Flip-flop and has the advantage that there are no
ambiguous states. Due to the extra logic that ensures only
one of the R and S inputs is enabled at any time. This
prevents possible oscillation, which can occur when both
inputs of an RS flip-flop are active at the same time.

The truth table of this J-K flip-flop is shown below:

In the D latch, when the CLK input is logic 1, the Q
output will always reflect the logic level present at the

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Digital Fundamentals Digital Fundamentals

D input, no matter how that changes. When the CLK Converting a D flip-flop to T operation is quite similar;
input falls to logic 0, the last state of the D input is the Q' output is connected back to the D input.
trapped and held in the latch, for use by whatever
other circuits may need this signal.

Because the single D input is also inverted to

provide the signal to reset the latch, this latch circuit
cannot experience a "race" condition caused by all
inputs being at logic 1 simultaneously. Therefore
the D latch circuit can be safely used in any circuit.

Although the D latch does not have to be made edge

triggered for safe operation, there are some
applications where an edge-triggered D flip-flop is
desirable. This can be accomplished by using a D
latch circuit as the master section of an RS flip-flop.
Both types are useful, so both are made
commercially available.

8.5 T Flip-Flop

We've already seen that a JK flip-flop with its J and K

inputs connected to a logic 1 will operate as a T flip-flop.
Converting an RS flip-flop involves a bit more, as shown
below. However, the simple feedback connections shown
will ensure that the S and R inputs will always tell the
flip-flop to change state at each clock pulse.

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9. MUX & DEMUX This circuit can be scaled upward to 3 by 8 MUX (three
NOT gates, eight 4-input AND gates, one 8-input OR
U U

gate) etc. Multiplexors can be used to control the flow of

9.1 Multiplexor (MUX): "data" through the circuits of a computer.

A multiplexor circuit has N selector lines, 2N input lines

P P
C0 C1 Output
and 1 output line. The N selector lines determine which
0 0 D0
of the 2N input lines is connected to the output. A simple
P P

2 by 4 MUX can be constructed out of two NOT gates, 0 1 D1

four 3-input AND gate and one 4-input OR gate. Here 1 0 D2
the configuration of the two control lines c0 and c1
determines which of the four input data lines (data in 0 1 1 D3
thru data in 3) is connected to the data out line. For
example of c0 = 1 and c1 = 0 then Data In 1 is connected
to Data Out through the second And gate. 9.2 Decoder:
A Decoder is the opposite of a multiplexor (also called a
Demultiplexor). Here N control inputs are decoded to
connect the single input to one of 2N outputs. If the single
P P

data in is set to 1, all other data outs except the one

selected are 0. A simple 2 to 4 Decoder can be
constructed out of two NOT and four 3-input AND gates.
Observe that if c1 equals 1 and c0 equals 0 (10 forms a
binary 2), Data In is connected to Data Out 2. Data Out
0, 1, and 3 are all 0. Like multiplexors, decoders can be
scaled upward.

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Digital Fundamentals

C1 C0 Output
0 0 D0
0 1 D1
1 0 D2
1 1 D3

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