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(b)
(c)
Figure 16: A 1 Mb CMOS EPROM. (a) Sense amplifier circuit structure. (b)
Memory cell array structure. (c) Threshold monitoring program (TMP) circuit.
Figure 17 : (a) A four-transistor memory cell with read and
program transistors implanted separately. (b) Four-transistor
memory cell with differential sensing scheme.
(a) (b)