Course Information

Lecturers
Real-time Digital Signal Processing Mike Brookes, Peter Cheung, Darren Ward
with the TMS320C6000 Web page
http://www.ee.ic.ac.uk/pcheung/teaching/ee3_Study_Project/index.html
Assessment
Objectives: Test (14 June) 25%,
Learn the architecture of a typical DSP Labs (22 June) 30%, Project (22 June) 45%

Deliverables
Learn how to perform basic real-time DSP tasks on ‘real’
hardware 1.Labs 3-4,6-8: Program listings (with comments) with
 evidence that programs work
Learn about interrupts and I/O devices
2. Project: Full listing of your program with a short
description (2-9) pages and assessment of performance
You will be working in pairs, each pair submits a single set of
reports

Digital Signal Processing DSP vs VLSI

 
Digital signal processing involves the DSPs have more application flexibility
manipulation of digital signals to extract 
useful information from them. DSPs are more cost effective; VLSI are
normally built for a single application /
customer

Higher sampling rates can typically be
achieved using VLSI

New features (bug fixes) can be added to
DSP with software upgrade

DSP vs Microprocessor Present Day Applications


DSPs can do several memory accesses in
a single instruction Wireless / Cellular HDD
 Voice-band audio  PRML read channel
 RF codecs  MR pre-amp
DSPs are optimized to handle repitition  Voltage regulation  Servo control
/ looping operations common in signal  SCSI tranceivers
processing algorithms Consumer Audio

 Stereo A/D, D/A DSP: Automotive
DSPs allow specialized addressing PLL Technology  Digital radio A/D/A
 Mixers 
modes (e.g., circular, indirect) to Enabler 
Active suspension
Voltage regulation
implement SP algorithms Multimedia
  Stereo audio
DSPs possess peripherals that allow for  Imaging DTAD
  Speech synthesizer
efficient I/O interfacing 
Graphics palette  Mixed-signal
Voltage regulation
processor
 What Problem Are We Trying To Solve? C6000 Architecture
Memory
x Y 8 functional units:
ADC DSP DAC
.D (data) 32-bit operands
A0 B0
.D1 .D2 .L (ALU) 32- or 40-bit operands
.S (shift) 32- or 40-bit operands
Digital sampling of Most DSP algorithms can be .M (multiply) 16x16 bit integer
.M1 .M2 or 32x32 bit floating point
an analog signal: expressed as:
count

Σ
A
Y = ai * xi .L1 .L2
2 register files (32-bit)
i = 1 .. ..

for (i = 1; i < count; i++){ All 8 units can be used in

t sum += m[i] * n[i]; } .S1 parallel each cycle
.S2
A15 B15

Controller/Decoder

6000 Series Devices Fast MAC using Natural C

Device MIPS MHz !#"%$ &(' Pins W $ Periphs
? J @5G(H7DFG(.(n ? J @\G(H O DF]M? J @5G(H O =5]M- =7H5.(@7o5=7H p
Memory qd- =7H5- ]M? J @5G(H7r(o5Dtsvu N
6201 1600 200 128 352 1.3 80 - 100 D2H
6202 2000 250 384 384/352 2.1 110 - 170 D3X
A0 B0 ? @7Adn - s\u N -Mwv.(@5o7=7H N - [\[7pCq
6203 2400 300 896 384 1.3 150 - 190 D3X .D1 .D2 r(o5Dt[\sCD j - k O = j - k N7xzy
6204 1600 200 128 384 0.8 30 - 60 D2X

NOO >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>O
6205 1600 200 128 306 0.8 40 - 70 D2P
6211 1200 150 72 256 0.9 25 - 40 E2H .M1 4769698#L N 8#P 8#Q#)R456;698 Q#S+T!Q#4
47)+)!UWV )+X  Y!Z([\[\] Y!^(L Y+_
.M2
)+*(,(- ./*1032547698#:
MHz ;#"<$ &(' Pins W $ Periphs
`` 47)+)!UWV )+a b!Z([\[\] b!^(L b+_
6701 1000 167 128 352 1.4 110 - 170 D2H `` 038#c#:d8eV 03X(fgY!_(] b+_(] Y+h
6711 900 150 72 256 1.1 25 - 50 E2H .. .L1 .L2 .. `` 038#c#:d8eV 03a(fgY!^(] b+^(] b+h
6712 600 100 72 256 0.7 10 - 22 E2 `` Y+)+)!:#8eV 47X Y!h(] Y+i(] Y+i
`` Y+)+)!:#8eV 47a b!h(] b+i(] b+i
8#- =7> ? @5A > 8#- =CB!@7DFE7G(H - I7- J - H KML .S1
` `Mj Y+X(klb V :#a 456;698
Peripherals Legend: .S2
A15 B15 ` `Mj Y+X(kl:#m+b V :#X Y!X(] X(] Y!X
D,E DMA (4), EDMA (16) 6201 & 6701
2,3 # of McBSP Serial Ports 6211 & 6711 & 6712 NOO >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>O
H,X,P HPI (Host Port), XBUS, PCI 6202 & 6203 & 6204 Controller/Decoder

The Core of DSP : Sum of Products Working Variables : The Register File

40 Register File A 40
y = ∑ an * xn a y = ∑ an * xn
Mult
.M n = 1 .M n = 1
x
The ’C6000
16 registers

MPY .M a, x, prod MPY .M a, x, prod

Designed to ALU
.L ADD .L y, prod, y prod .L ADD .L y, prod, y
handle DSP’s y
math-intensive
calculations ..
Note:
.
You don’t have to
specify functional
units (.M or .L)
32-bits

Where are the variables? How are the number of iterations specified?
 Loops: Coding on a RISC Processor The “S” Unit : For Standard Operations

Register File A 40
1. Program flow: the branch instruction a y = ∑ an * xn
.S n = 1
B loop x
MVK .S 40, cnt
cnt

16 registers
loop:
2. Initialization: setting the loop count prod .M
MPY .M a, x, prod
y
MVK 40, cnt ADD .L y, prod, y
.. .L SUB .L cnt, 1, cnt
3. Decrement: subtract 1 from the loop counter . B .S loop

SUB cnt, 1, cnt

32-bits

How is the loop terminated?

Conditional Instruction Execution Loop Control via Conditional Branch

Register File A 40
To minimize branching, all instructions are conditional y = ∑ an * xn
a
.S n = 1
[condition] B loop x
MVK .S 40, cnt
cnt
loop:
prod .M
MPY .M a, x, prod
Execution based on [zero/non-zero] value of specified variable y
ADD .L y, prod, y
.. .L SUB .L cnt, 1, cnt
Code Syntax Execute if:
. [cnt] B .S loop
[ cnt ] cnt ≠ 0
[ !cnt ] cnt = 0

32-bits

How are the a and x array values brought in from memory?

Memory Access via “.D” Unit Auto-Increment of Pointers

Register File A 40 Register File A 40

a y = ∑ an * xn a y = ∑ an * xn
.S n = 1 .S n = 1
x x
MVK .S 40, cnt MVK .S 40, cnt
cnt cnt
loop: loop:
16 registers

16 registers

prod .M prod .M
LDH .D *ap ,a LDH .D *ap++, a
y y
LDH .D *xp ,x LDH .D *xp++, x
*ap *ap
.L MPY .M a, x, prod .L MPY .M a, x, prod
*xp *xp
ADD .L y, prod, y ADD .L y, prod, y
*yp *yp
SUB .L cnt, 1, cnt SUB .L cnt, 1, cnt
.D .D
[cnt] B .S loop [cnt] B .S loop

Data Memory: Data Memory:

x(40), a(40), y x(40), a(40), y
How do we increment through the arrays? How do we store results back to memory?
 Storing Results Back to Memory ‘C6700 : RISC-like instruction set
–†7† ‰7ˆM.SŒ Unit– ’(( ‹ – (’  ‰\.LŠ5 Unit –†5†  ‹
Register File A 40 –†7†— ‰\Š5 – ’( †5‹ –d†7† Š#Ž –†5†7†7‹
y = ∑ an * xn –†7† “ Š#Ž ˜ ™›‹MŒ5  ‹ –d‰7†  –†5† \‘5’\ ‹
a .S –‰7†  ˆ% ˜ ™›‹(ˆMœ  ‹ ˜ ™›‹(ˆMœ  –\ \‘5’ †7‹
x
.S n = 1 ’ \ ‡ ˜ ™›‹(‡  ‹ ˜ ™›‹MŒ5 (\‘5’ … ‰M  ‹
MVK .S 40, cnt ˜ ‡/Ž \ Ž ˜ ™›‹MŒ5\†7‹ ˜ ™›‹(‡ž \‘5’ … ‰M\†7‹
cnt ˆ%”( (\ ‡ ˜ ™›‹(ˆMœ#†7‹ ‡/™ ’ † \‘5’\˜  ‹(… ‰M
loop: .L ™dš \‘5’ ˜ ™›‹(‡(†5‹ ™dš ”7Š#Ž †7‹(… ‰(
prod .M ™dš ˜ \‘5’(“ Ž˜ ‹‹ ‰5ˆMŒ •Mˆ(Ž7Š  ‹(ŽM ‘ ‰ ˜
y LDH .D *ap++, a ™dš5— ”7Š#Ž Ž ˜ ‹(†5‹ ‰7ŠdŽ5™ †7‹%\Ž ‘ ‰ ˜
LDH .D *xp++, x ™dš5—  •Mˆ(Ž7Š Ž  œ#Ž  ‹ †7‹  ‹
*ap .D Ž  œ#Ž7†5‹
.L MPY .M a, x, prod  ‹(†7‹ .M Unit
*xp ™›‹/Ÿ  ™›‹/Ÿ
™›‹/Ÿ  ‹
*yp
ADD .L y, prod, y
.D Unit ™›‹/Ÿ   ™›‹/Ÿ 
™›‹/Ÿ7†5‹
SUB .L cnt, 1, cnt .M –†5† ‰5ˆMŒ ™›‹/Ÿ7‡  ™›‹/Ÿ7…
.D –†5†(– ’§  ’%¢ %¢ £¥¤   ’¡  ’<¢ /¢ £¥¤ ™›‹/Ÿ  ‡ ™›‹/Ÿ7… †
[cnt] B .S loop ‡%† ’¨  ’%¢ %¢ £¥¤ \‘’ {d|C}#~7 €}‚/ƒ/„
‡%†5† £ \‘’ – ’¦  ’<¢ /¢ £¥¤
STW .D y, *yp ™dš •(ˆ(Ž\Š ‰\Š#‹ … †7‡/ˆ
Data Memory:
x(40), a(40), y

'C6000 System Block Diagram ‘C6000 Internal Buses

Internal Program Addr x32
Memory
PC
P Internal Program Data x256
E Memory
©dª#« ¬#­ž®;¯d° Data Addr - T1 x32
±R¬#²´³;­žµ R Internal Buses A
I Data Data - T1 x32/64 regs
P
H ¶· .D1 .D2 ¸ ¶·¹
External Data Addr - T2 x32 B
¸¹ Memory
E º ü .M1 .M2 º »¼
Data Data - T2 x32/64 regs
R þ ½ »¾ ½
A ¿ÀÁ¾ .L1 .L2 ÀÁ¾¿ DMA Addr - Read x32
L Â .S1 .S2 Â
DMA Data - Read x32
S Peripherals DMA
DMA Addr - Write x32
CPU
DMA Data - Write x32

'C6000 Peripherals 'C6000 Peripherals (EMIF)

ÐCÔ µ#®!Õ
Host Port Internal Internal
Interface Memory Memory

©dª#« ¬#­ž®;¯d° Ä(Å(Æ Ç/È

Ä(Å(Æ Ç/È ÌÎÍCϛР±
±R¬#²´³;­žµ EMIF Internal Buses EMIF Internal Buses

McBSPs ¶· .D1 .D2 ¸ ¶·¹ ¶· .D1 .D2 ¸ ¶·¹

¸¹ ÌÎÖ+ÌÎÏ+Ð ± ¸¹
EDMA
º ü .M1 .M2 º »¼ º ü .M1 .M2 º »¼
þ ½ »¾ ½ þ ½ »¾ ½
DMA
b+@7@5H745@7G(Ë7*(A ¿ÀÁ¾ .L1 .L2 ÀÁ¾¿ ¿ÀÁ¾ .L1 .L2 ÀÁ¾¿
 .S1 .S2   .S1 .S2 Â
É - DF*(A Ê B+@5o7=5H
EMIF
CPU Ñ Glueless access to async/sync memory
CPU
Ò Works with PC100 SDRAM (cheap, fast, and easy!)
Ó 8/16/32-bit data or 32-bit program access
 ’C6000 Peripherals (HPI/XB/PCI) ’C6000 Peripherals (McBSP)
XB
ØC³ Ô « 16/32 Host Port Internal ØC³ Ô « Internal
µÙ Interface Memory
µÙ Host Port
Memory
PCI
©dª#« ¬#­ž®;¯d° ©#ª#« ¬#­ž®;¯°
±R¬#²´³;­žµ EMIF Internal Buses ±R¬#²´³;­žµ EMIF Internal Buses

¶· .D1 .D2 ¸ ¶·¹ McBSP ¶· .D1 .D2 ¸ ¶·¹

¸¹ ¸¹
º ü .M1 .M2 º »¼ º ü .M1 .M2 º »¼
þ ½ »¾ ½ þ ½ »¾ ½
¿ÀÁ¾ .L1 .L2 ÀÁ¾¿ ¿ÀÁ¾ .L1 .L2 ÀÁ¾¿
HPI Â .S1 .S2 Â Â .S1 .S2 Â
× McBSP (serial port)
Provides 16 / 32-bit dedicated host ↔ µP bus Ú 2 (or 3) full-duplex, synchronous serial-ports CPU
CPU Û Up to 100 Mb/sec performance
Ü Supports multi-channel operation (T1, E1, MVIP, …)

’C6000 Peripherals (DMA/EDMA) ’C6000 Peripherals (Timer/Counter)

XB XB
ØC³ Ô « Internal ØC³ Ô « Internal
µÙ Host Port
Memory
µÙ Host Port
Memory
PCI PCI
©dª#« ¬#­ž®;¯d° ©#ª#« ¬#­ž®;¯°
±R¬#²´³;­žµ EMIF Internal Buses ±R¬#²´³;­žµ EMIF Internal Buses

McBSP ¶· .D1 .D2 ¸ ¶·¹ McBSP ¶· .D1 .D2 ¸ ¶·¹

¸¹ Timer / Counters ¸¹
EDMA
º ü .M1 .M2 º »¼ á Two 32-bit timer/counters
EDMA
º ü .M1 .M2 º »¼
þ ½ »¾ ½ â Can generateDMA
interrupts þ ½ »¾ ½
DMA ã
¿ÀÁ¾ .L1 .L2 ÀÁ¾¿ Input and output pins ¿ÀÁ¾ .L1 .L2 ÀÁ¾¿
 .S1 .S2   .S1 .S2 Â
DMA / EDMA É - DF*(A Ê B+@5o7=7H
Ý Transfers any set of memory locations to another
Þ CPU CPU
4 / 17 channels (transfer parameter sets)
ß Transfers can be triggered by any interrupt (sync)
à Operates independent of CPU

DSP Starter Kit (DSK) ‘C6711 DSK Overview

äæåèçRéžêèëìçíé î X(V iè8#@ 9*(Ad:do7E5E7J K X(_(0ý:#)+S!Y›0 X(a(i 2745Y›:
)!G(o  7H *(AdB+G(A ËCP Ê 2

ï 150 MHz ‘C6711 DSP      
ð TI 16-bit A/D Converter (‘AD535)
ñ External Memory
ò 16M Bytes SDRAM
ó 128K Bytes Flash ROM
ô LED’s 8#G(A G(J J *(J
õ Daughter card expansion 8#@7A H7P Ê 2
ö Power Supply & Parallel Port Cable ;< =>?@A BC DD 8 B!_(^(X/X
)+:#8
÷æø3ùûúüžëýçíé î 8#@ 9*(A
! G(. " )!VMB+G(A ËFP Ê 2
þ Code Generation Tools  9/ . )1/:
8#@9*(A
ÿ
(C Compiler, Assembler & Linker) 47Q#) m!r(*(Ad)+P 8
Code Composer Debugger r9- H . 7*(r
(256K program limitation)
Example Programs & S/W Utilities S+*(r(*(H É 5A *(*3m!r(*(Ad4\Q#)+r

Power-on Self Test # V # Î8#@ 9*(Ad:do7E7E5J K X(_(> I7- H7.(@\Ë5*(.  23 46574*3 2
 Flash Utility Program
Q#DFo7J G(H - @7=
Y $&
+*(G(Ë5*(A
!(É ' 54 - =5*347*(,M*(JMP =5E7o5H  -%. / 0)/1 
 Board Confidence Test (! É Y%$&
!*(G(Ë7*(A 45- =5*347*(,M*(JM69o7H E5o7H  (*)+*, * (
 Host access via DLL
 Sample Program(s)
B!B+:ÎS+*(r(*MH
N&O & M0L '<&P &T Q%$ R S M
DSK Resets Memory Maps
T
&U L0V → HFXW &('&($ TMS320C6x11 DSK
Y&W &('<&($ '6Z [ Å\/Ä(Ä T HF
]&^ S($ & _Z [ Å`%Ä/Ä J &('<&($
0000_0000
16MB SDRAM
L ' USS($ P Sab 64KB Internal
cQJ a '<&(6 Hi (Progam or Data)
Sdfegh
PP ;< =>? @A BC DD
0180_0000 128K byte FLASH
On-chip Periph
TBC
4 byte I/O Port “
9008_0000
LED’s
” Switches
Y+E5E7J K38#@ 9*(A 8000_0000 • DSK status
256MB External – DSK rev#
E&FG6HIKJ LM
Y!I7r(@7J o7H *vS+*M' r(*(H 9000_0000 — Daughter Card
Q#DCo5J G(H - @7=FS+*(rM*(H S+*(r(*(H\8#o5r 7I7o5H H @7= 8#69: É 256MB External
&FL P P t S{!& J‚ aQ u j % Älkm\ Available via
ŽŒW ‹ŒFG6HI†J LM ' [ S LM $ ' A000_0000
ƒ&G6MlJ a J &„SQ/Q/a('R S M &('<&($ h‰ Ua($ n&o _qpfpsr 256MB External Daughter Card
 T  H qW  T S(&(' M~ $ J &('<&($
aP '/S t a J aP P &P t S J $ ˆ H J &('<M&(L$ Š dlR Q6R MtL $ → ' tuJ S L $ B000_0000 Connector
v&w _qxzyfx
…&FG6HI†J LM ' $ a $d3& &d L P (a $ R S M 256MB External
‡&W &('%&($ ' c L P PUSa J b ‘ŒW &('<&($ ';&d L P a($ R S M '/R M &{'a<| & → ' tu/J S L $
} T S M~ $M'%$ a J $[%[ HqLM $ R P
ˆ M MR $ & J c aQ & ˆ FF’I [ Š
R Q/P M‰ &d L P (a $ R S MŠ Ç T c
aP P g ' P (a '€
FFFF_FFFF

Win32 API for Host DSK Help

¬#®´¯ûÕd³+®;®+¬#Õd« › ³+® « ³ « œ;¬ Í#ÌX
dsk6x_open( ) ˜š™
° ³ Ô ¬R¯ûÕd³+®;®+¬#Õ#« › ³+®´« ³´« œ!¬ Í+ÌX
dsk6x_close( ) Ù
Ï ¬ Ô ¬#«+« œ;¬û¬d®+« › ­ž¬ ̞͛&Ÿ ³!¯d­ 
dsk6x_reset_board( )
Ï ¬ Ô ¬#«+³+®;° µR« œ;¬ ͛Ìq¡ ³;®´« œ!¬ ͛ÌX
dsk6x_reset_dsp( )
³+¯ ´¯ › ² ¯¥¤;¬R« ³ ͛Ìq¡ ²´¬#²´³!­žµ
dsk6x_coff_load( ) ¢ Ù ˜s£'£
K
¬#®´« œ!¬ûØ ¡¥¦§ ³;­ « œ;¬ ͛Ìq¡
dsk6x_hpi_open( ) ˜š™
° ³ Ô ¬R« œ;¬ûØ ¡¦§ ³;­ « œ;¬ ͛Ìq¡
dsk6x_hpi_close( ) Ù
Ï ¬#¯  Í+Ìq¡ ²´¬#²´³!­žµŒ¨› ¯R« œ!¬ûØ ¡¦
dsk6x_hpi_read( )
­*› « ¬R« ³ ͛Ìq¡ ² ¬#² ³;­µª¨› ¯í« œ!¬ûØ ¡¦
dsk6x_hpi_write( ) ©
¬#®;¬#­ž¯#« ¬û¯ ͛ÌX¡ › +® « ¬d­­¬ «
dsk6x_generate_int( ) « ™