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A B C D E COMPAL CONFIDENTIAL MODEL NAME : Abacus-MT 1 1 COMPAL P/N
A
B
C
D
E
COMPAL CONFIDENTIAL
MODEL NAME :
Abacus-MT
1
1
COMPAL P/N :
PCB NO :
LA-1682
Revision :
0.2
2
2
Abacus-MT Schematics Document
uFCBGA/uFCPGA NorthWood MT
2003-02-25
3
3
4
4
Dell-Compal Confidential
Compal Electronics, Inc.
Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Tuesday, February 25, 2003
Sheet
1
o f
44
A
B
C
D
E

A

B

C

D

E

1

2

A B C D E 1 2 3 4 1 2 3 4 Compal confidential Model

3

4

1

2

A B C D E 1 2 3 4 1 2 3 4 Compal confidential Model

3

4

Compal confidential

Model : Abacus-MT

Block Diagram

NorthWood-MT

Prescott-MT

uFCPGA CPU

+1.2VP

+CPU_CORE

478pin

page 5,6

CPU Bypass page 7
CPU Bypass
page 7

CPU ITP Port and VID

page 8

Thermal Sensor ADM1032 +5VS page 6
Thermal Sensor
ADM1032
+5VS
page 6
Clock Generator ICS950810 +3VS page 16
Clock Generator
ICS950810
+3VS
page 16

Fan Control 1

+12V

page 7

Fan Control 2 HA#(3 31) System Bus HD#(0 63) +5VS page 7 400/533 MHz INTEL
Fan Control 2
HA#(3
31)
System Bus
HD#(0
63)
+5VS
page 7
400/533 MHz
INTEL
Memory
DDR-DIMM X2
Mainstream
PIRQE#
BANK 0, 1, 2, 3
LVDS Connector
BUS(DDR)
+2.5V 200/266/333MHz
Montara-GT
on VGA Board
AGP Conn
AGP4X(1.5V)
+1.5VS
+2.5V
732 BGA
page 17
+2.5V
+1.25VS
page 13,14,15
TV OUT page 19
+1.25VS
CRT Signal
+CPU_CORE
page 9,10,11,12
Internal LVDS
CRT Connector
Value
page 19
LVDS Connector
HUB LINK 1.5
on M/B Board page 18
+1.5VS
66MHz
+3VS PCI BUS 2X USB Ports +3VS 33MHz INTEL 48MHz USB 2.0/1.1 +3VALW +3VALW +5VALW
+3VS
PCI BUS
2X USB Ports
+3VS 33MHz
INTEL
48MHz
USB 2.0/1.1
+3VALW
+3VALW
+5VALW
page 34
IDSEL:AD18
IDSEL:AD17
IDSEL:AD20
+1.5VS
ICH4-M
(PIRQC,D#,GNT#1,REQ#1)
(PIRQB#,GNT#0,REQ#0)
(PIRQA#,GNT#2,REQ#2)
+1.5VALW
24.576MHz
AC-LINK
421 BGA
+CPU_CORE
CardBus
Debug
Minipci CONN
LAN
ATA100
VCC5REF
WIRELESS
& 1394
BCM-4401L
VCC5REFSUS
page 20,21,22
MDC
+5VS
+3V
PCI4510
+3VS
page 28
page 35
+5VS
+3V
page 24
+3V
page 25,26,27
+3VALW
+3V page 31
LPC BUS
+3VS
33MHz
Cable
IDE
Card Bus
1394
IDE HDD
AC97 Codec
RJ45
CD-ROM
SLOT
CONN
STAC9750
RJ11
page 24
+5VS
+5VS
page 26
page 25
NS PC87591L
+5VDDA
page 23
page 23
page 29
Cable
Embedded
Controller
SIDE IRQ15
PIDE IRQ14
+3VS
page 32
+3VALW
Power On/Off
Reset & RTC
DC/DC Interface
AMP & INT.
Speaker
HeadPhone &
MIC Jack
Suspend
Ext. IO page 33
Touch Pad
+5VALW page 30
+5VDDA page 30
LID Switch
page 34
page 35
Int.KBD
+5VS
page 31
page 33
Power Circuit
LED Indicator
DC/DC
BIOS
EC DEBUG
page
Connector
+3VALW
page 33
+3VALW page 32
36,37,38,39,40,41
page 34
+3VALW page 33 +3VALW page 32 36,37,38,39,40,41 page 34 o f Dell-Compal Confidential Compal Electronics, Inc.
+3VALW page 33 +3VALW page 32 36,37,38,39,40,41 page 34 o f Dell-Compal Confidential Compal Electronics, Inc.

o f

Dell-Compal Confidential

Compal Electronics, Inc.

Title

Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Size

Document Number

Abacus-MT LA-1682

Rev

0.2

Tuesday, February 25, 2003

Sheet

2

44

A

B

C

D

E

5 4 3 2 1 Power Managment table ST2, ST1, ST0 Trip (C0 bit 2:0)
5
4
3
2
1
Power Managment table
ST2, ST1, ST0 Trip (C0 bit 2:0)
+3VS
MHz
+5VS
FSB
MEMORY
GFX-LOW
GFX-HIGH
Cfg#
Signal
+1.5VALW
PCB Rev
Data
+1.5VS
000
400
266
133
200
0
+3VALW
+1.2VP
Bringup-Build
0.1
001
400
200
100
200
1
+5VALW
+3V
SST-Build
D
D
+CPU_CORE
010
400
200
100
133
2
State
+12VALW
+2.5V
+1.25VS
PT-Build
011
400
266
133
266
3
+12V_FAN
100
533
266
133
200
4
ST-Build
101
533
266
133
266
5
S0
ON
ON
ON
110
533
333
166
266
6
QT-Build
111
400
333
166
250
7
S1
ON
ON
ON
S3
ON
ON
OFF
S5 S4/AC
ON
OFF
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
SCHEMATICS VERSION LIST
Ceramic Capacitor Spec Guide:
VERSION
ISSUE DATE
REMARK
C
C
Temperature Characteristics:
0
1
3
Item
Function
Note
Symbol
2
4
5
6
7
0.0A
12/30/2002
First Release
1@
Value
no TV, 1394,
CODE
Z5U
Z5V
Z5P
Y5U
Y5V
Y5P
X5R
X7R
2@
Mainstream
@
DEPOP
8
9
A
B
C
D
E
F
G
NP0
C0G
BJ
CH
CJ
CK
SH
SJ
H
I
J
UJ
UK
SL
Tolerance:
Symbol
A
B
C
D
F
G
H
J
CODE
+-0.05PF
+-0.1PF
+-0.25PF
+-0.5PF
+-1PF
+-2%
+-3%
+-5%
B
B
K
M
N
P
Q
V
X
Z
+-10%
+-20%
+-30%
+100,-0%
+30,-10%
+20,-10%
+40,-20%
+80,-20%
SMBUS Control Table
THERMAL
THERMAL
VGA Thermal
SOURCE
INVERTER
BATT
SERIAL
SENSOR
SENSOR
SODIMM
CLK CHIP
MINI PCI
LCD
EEPROM
(CPU)
(LM75)
ADM1032
SMB_EC_CK1
PC87591L
SMB_EC_DA1
SMB_EC_CK2
PC87591L
SMB_EC_DA2
SMB_CLK
ICH4-M
SMB_CDATA
A
A
LCD_DDCCLK
M-GT
Dell-Compal Confidential
LCD_DDCDATA
Compal Electronics, Inc.
Title
Note & Revision
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Tuesday, February 25, 2003
Sheet
3
o f
44
5
4
3
2
1
5 4 3 2 1 PU22 U66 FAN5234 +1.5VALW +1.5VS SUSP# page 35 page 39
5
4
3
2
1
PU22
U66
FAN5234
+1.5VALW
+1.5VS
SUSP#
page 35
page 39
+5VALW
D
D
U31
+5VS
+5VALW
SUSP#
page 35
PU8
SHDN#
Q6
+5VSHDD
MAX1632
SIDEPWR
page 23
page 38
U26
+5VDDA
SUSP#
page 29
U70
+3VALW
+3V
SYSON
page 35
VR_ON
+12VALW
U20
C
C
+3VS
page 36
PU21
SUSP#
PU27
page 35
AC
LM3485
+12VFANP
CM2843
+1.2VP
B+
page 38
page 41
ENLL
PU23
Mobile
Battery
JP8
page 36
ISL6247
+CPU_CORE
+5VS
page 41
+3VS
B
B
PU20
+1.5VS
SUSP#
VGA Conn.
+1.25VS
ISL6225
180 pin
+2.5V
+2.5V
+3V
page 40
SYSON
+5VALW
+12VALW
B+
page 17
A
A
Dell-Compal Confidential
Compal Electronics, Inc.
Title
POWERDIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
Date:
Tuesday, February 25, 2003
Sheet
4
o f
44
5
4
3
2
1
5 4 3 2 1 +CPU_CORE D D JCPU1A HA#[3 31] HD#[0 63] <9> HA#[3
5
4
3
2
1
+CPU_CORE
D
D
JCPU1A
HA#[3 31]
HD#[0 63]
<9> HA#[3 31]
HD#[0
63]
<9>
HA#3
HD#0
K2
B21
A#3
D#0
HA#4
HD#1
K4
B22
A#4
D#1
HA#5
HD#2
L6
A23
A#5
D#2
HA#6
HD#3
K1
POWER
A25
A#6
D#3
HA#7
HD#4
L3
C21
A#7
D#4
HA#8
HD#5
M6
D22
A#8
D#5
HA#9
HD#6
L2
B24
A#9
D#6
HA#10
HD#7
M3
C23
A#10
D#7
HA#11
HD#8
M4
C24
A#11
D#8
HA#12
HD#9
N1
B25
A#12
D#9
HA#13
HD#10
M1
G22
A#13
D#10
HA#14
HD#11
N2
H21
A#14
D#11
HA#15
HD#12
N4
C26
A#15
D#12
HA#16
HD#13
N5
D23
A#16
D#13
HA#17
HD#14
T1
J21
A#17
D#14
HA#18
HD#15
R2
D25
A#18
D#15
HA#19
HD#16
P3
H22
A#19
D#16
HA#20
HD#17
P4
HOST
E24
A#20
D#17
HA#21
HD#18
R3
G23
A#21
D#18
HA#22
HD#19
T2
F23
A#22
ADDR
D#19
HA#23
HD#20
U1
F24
A#23
D#20
C
HA#24
HD#21
P6
E25
C
A#24
D#21
HA#25
HD#22
U3
F26
A#25
D#22
HA#26
HD#23
T4
D26
A#26
D#23
HA#27
HD#24
V2
L21
A#27
D#24
HA#28
HD#25
R6
G26
A#28
D#25
HA#29
HD#26
W1
H24
A#29
D#26
HA#30
HD#27
T5
M21
A#30
D#27
HA#31
HD#28
U4
L22
A#31
Northwood-MT
D#28
HD#29
V3
J24
A#32
D#29
HOST
HD#30
W2
K23
A#33
D#30
HD#31
Y1
H25
A#34
D#31
HD#32
AB1
M23
A#35
Prescott-MT
ADDR
D#32
H_REQ#[0 4]
HD#33
N22
<9> H_REQ#[0 4]
D#33
HD#34
P21
D#34
H_REQ#0
HD#35
J1
M24
REQ#0
D#35
H_REQ#1
HD#36
K5
N23
REQ#1
D#36
H_REQ#2
HD#37
J4
M26
REQ#2
D#37
H_REQ#3
HD#38
J3
N26
REQ#3
D#38
H_REQ#4
HD#39
H3
N25
REQ#4
D#39
H_ADS#
HD#40
G1
R21
<9> H_ADS#
ADS#
D#40
HD#41
P24
D#41
HD#42
R25
D#42
+CPU_CORE
AC1
CONTROL
HD#43
R24
AP#0
D#43
HD#44
V5
T26
AP#1
D#44
HD#45
AA3
T25
BINIT#
D#45
R284
56 _0402_1%
HD#46
1 2
AC3
T22
IERR#
D#46
HD#47
T23
D#47
R301
220_0402_5%
HD#48
1 2
U26
D#48
HD#49
H6
U24
<9> H_BREQ0#
BR0#
D#49
B
B
HD#50
D2
U23
<9> H_BPRI#
BPRI#
D#50
HD#51
G2
V25
<9> H_BNR#
BNR#
D#51
HD#52
G4
U21
<9> H_LOCK#
LOCK#
D#52
HD#53
V22
D#53
CLK
HD#54
V24
D#54
CLK_CPU_BCLK
HD#55
AF22
W26
<16> CLK_CPU_BCLK
BCLK0
D#55
CLK_CPU_BCLK#
HD#56
AF23
Y26
<16> CLK_CPU_BCLK#
BCLK1
D#56
HD#57
W25
D#57
CON
HD#58
Y23
D#58
HD#59
Y24
D#59
TROL
POWER
HD#60
F3
GND
Y21
<9> H_HIT#
HIT#
D#60
HD#61
E3
AA25
<9> H_HITM#
HITM#
D#61
HD#62
E2
AA22
<9> H_DEFER#
DEFER#
D#62
HD#63
AA24
D#63
FOX_PZ47803-274A-42_P
rescott
+CPU_CORE
A
BOOTSELECT <41>
A
NWD: L
PSD: H
Dell-Compal Confidential
PSD Pull-up internal
Compal Electronics, Inc.
Title
Prescott / P4 uFCPGA (1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
Custom
Date:
Tuesday, February 25, 2003
Sheet
5
o f
44
5
4
3
2
1
A10
VCC_0
A12
VCC_1
H1
A14
VSS_0
VCC_2
H4
A16
VSS_1
VCC_3
H23
A18
VSS_2
VCC_4
H26
A20
VSS_3
VCC_5
A11
A8
VSS_4
VCC_6
A13
AA10
VSS_5
VCC_7
A15
AA12
VSS_6
VCC_8
A17
AA14
VSS_7
VCC_9
A19
AA16
VSS_8
VCC_10
A21
AA18
VSS_9
VCC_11
A24
AA8
VSS_10
VCC_12
A26
AB11
VSS_11
VCC_13
A3
AB13
VSS_12
VCC_14
A9
AB15
VSS_13
VCC_15
AA1
AB17
VSS_14
VCC_16
AA11
AB19
VSS_15
VCC_17
AA13
AB7
VSS_16
VCC_18
AA15
AB9
VSS_17
VCC_19
AA17
AC10
VSS_18
VCC_20
AA19
AC12
VSS_19
VCC_21
AA23
AC14
VSS_20
VCC_22
AA26
AC16
VSS_21
VCC_23
AA4
AC18
VSS_22
VCC_24
AA7
AC8
VSS_23
VCC_25
AA9
AD11
VSS_24
VCC_26
AB10
AD13
VSS_25
VCC_27
AB12
AD15
VSS_26
VCC_28
AB14
AD17
VSS_27
VCC_29
AB16
AD19
VSS_28
VCC_30
AB18
AD7
VSS_29
VCC_31
AB20
AD9
VSS_30
VCC_32
AB21
AE10
VSS_31
VCC_33
AB24
AE12
VSS_32
VCC_34
AB3
AE14
VSS_33
VCC_35
AB6
AE16
VSS_34
VCC_36
AB8
AE18
VSS_35
VCC_37
AC11
AE20
VSS_36
VCC_38
AC13
AE6
VSS_37
VCC_39
AC15
AE8
VSS_38
VCC_40
AC17
AF11
VSS_39
VCC_41
AC19
AF13
VSS_40
VCC_42
AC2
AF15
VSS_41
VCC_43
AC22
AF17
VSS_42
VCC_44
AC25
AF19
VSS_43
VCC_45
AC5
AF2
VSS_44
VCC_46
AC7
AF21
VSS_45
VCC_47
AC9
AF5
VSS_46
VCC_48
AD10
AF7
VSS_47
VCC_49
AD12
AF9
VSS_48
VCC_50
AD14
B11
VSS_49
VCC_51
AD16
B13
VSS_50
VCC_52
AD18
B15
VSS_51
VCC_53
AD21
B17
VSS_52
VCC_54
AD23
B19
VSS_53
VCC_55
AD4
B7
VSS_54
VCC_56
AD8
B9
VSS_55
VCC_57
C10
VCC_58
AD1
C12
BOOTSELECT
VCC_59
C14
VCC_61
F13
C16
VCC_81
VCC_62
F15
C18
VCC_82
VCC_63
F17
C20
VCC_83
VCC_64
F19
C8
VCC_84
VCC_65
F9
D11
VCC_85
VCC_66
F11
D13
VCC_80
VCC_67
E8
D15
VCC_79
VCC_68
E20
D17
VCC_78
VCC_69
E18
D19
VCC_77
VCC_70
E16
D7
VCC_76
VCC_71
E14
D9
VCC_75
VCC_72
E12
E10
VCC_74
VCC_73
5 4 3 2 1 GND H_SKTOCC# R269 and R317 depop for desktop CPU R267
5
4
3
2
1
GND
H_SKTOCC#
R269 and R317 depop for desktop CPU
R267
R269
@33_0402_5%
H_DPSLPR#
1 0_0402_5%
2
H_DPSLP# <10,20>
JCPU1B
H_GHI#
1 2
PM_CPUPERF# <21>
R317
+CPU_CORE
0_0402_5%
H_RS#[0 2]
<9> H_RS#[0 2]
H_RS#0
F1
J26
RS#0
DP#0
H_RESET#
H_RS#1
+H_GTLREF
1
2
G5
K25
RS#1
DP#1
R279
51_0402_5%
H_RS#2
D
F4
GROUND
K26
D
RS#2
DP#2
ITP_BPM#0
1
2
AB2
L25
1
RSP#
DP#3
R262
51_0402_5%
H_TRDY#
J6
<9> H_TRDY#
CON
TRDY#
ITP_BPM#1
C318
1
2
AA21
GTLREF0
R272
51_0402_5%
220P_0603_50V8J
AA6
TROL
GTLREF1
2
ITP_BPM#2
1
2
F20
GTLREF2
R268
51_0402_5%
H_A20M#
C6
<20> H_A20M#
REF
F6
A20M#
GTLREF3
ITP_BPM#3
H_FERR#
1
2
B6
<20> H_FERR#
FERR#
R296
51_0402_5%
H_IGNNE#
B2
AE26
<20> H_IGNNE#
IGNNE#
OPTIMIZED/COMPAT#
ITP_BPM#4
H_SMI#
+CPU_CORE
1
2
B5
<20> H_SMI#
SMI#
R278
51_0402_5%
H_PWRGD
AB23
<20> H_PWRGD
PWRGOOD
ITP_BPM#5
H_STPCLK#
R285
1
2
Y4
AD24
1
2
<20> H_STPCLK#
STPCLK#
TESTHI0
R291
51_0402_5%
56_0402_5%
AA2
TESTHI1
H_INTR
D1
<20> H_INTR
LEGACY
R275
AC21
1
2
LINT0
TESTHI2
H_PWRGD
H_NMI
56_0402_5%
1
2
E5
AC20
<20> H_NMI
LINT1
TESTHI3
R288
300_0402_5%
H_INIT#
W5
AC24
<20> H_INIT#
INIT#
TESTHI4
H_RESET#
AB25
AC23
<8,9> H_RESET#
RESET#
TESTHI5
1 R293
56_0402_5%
AA20
2
TESTHI6
ITP
1 R276
56_0402_5%
AB22
2
TESTHI7
H_DBSY#
1 R294
56_0402_5%
H5
U6
2
<9> H_DBSY#
DBSY#
TESTHI8
H_DRDY#
1 R464
56_0402_5%
H2
W4
<9> H_DRDY#
MISC
2
DRDY#
TESTHI9
H_BSEL0
1 R465
56_0402_5%
AD6
Y3
2
<16> H_BSEL0
BSEL0
TESTHI10
H_GHI#
1 R466
300_0402_5%
AD5
A6
2
BSEL1
TESTHI11
H_DPSLPR#
1 R318
@56_0402_5%
AD25
2
TESTHI12
H_THERMDA
H_DSTBN#[0 3]
B3
THER
THERMDA
H_DSTBN#[0
3]
<9>
+CPU_CORE
H_THERMDC
Northwood-MT
C4
THERMDC
H_DSTBN#0
E22
MAL
DSTBN#0
H_THERMTRIP#
H_DSTBN#1
1
2
A2
K22
THERMTRIP#
DSTBN#1
C
R315
56 _0402_1%
Prescott-MT
H_DSTBN#2
R22
C
DSTBN#2
H_DSTBN#3
W22
DSTBN#3
ITP_BPM#0
H_DSTBP#[0 3]
AC6
<8> ITP_BPM#0
DATA
BPM#0
H_DSTBP#[0
3]
<9>
ITP_BPM#1
AB5
<8> ITP_BPM#1
BPM#1
ITP_BPM#2
MISC
H_DSTBP#0
AC4
F21
<8> ITP_BPM#2
BPM#2
DSTBP#0
ITP_BPM#3
H_DSTBP#1
Y6
J23
<8> ITP_BPM#3
BPM#3
DSTBP#1
ITP_BPM#4
H_DSTBP#2
AA5
P23
<8> ITP_BPM#4
BPM#4
DSTBP#2
ITP_BPM#5
H_DSTBP#3
AB4
W23
<8> ITP_BPM#5
BPM#5
DSTBP#3
H_ADSTB#0 <9>
+IOPLL
+CPU_CORE
H_ADSTB#1 <9>
0_0603_5%
ITP_TCK
<8> ITP_TCK
ADDR
H_ADSTB#0
D4
L5
TCK
ADSTB#0
R207
ITP_TDI
H_ADSTB#1
1
2
C1
R5
<8> ITP_TDI
ITP
TDI
ADSTB#1
+1.2VP
ITP_TDO
H_DBI#[0 3]
D5
<8> ITP_TDO
TDO
H_DBI#[0
3]
<9>
ITP_TMS
F7
<8> ITP_TMS
TMS
R206
@0_0603_5%
ITP_TRST#
H_DBI#0
R266
1
2
E6
E21
<8> ITP_TRST#
TRST#
DBI#0
L24
H_DBI#1
@0_0402_5%
G25
1
2
DBI#1
SYSRST# <21>
VCCIOPLL
1
2
AD20
DATA
H_DBI#2
P26
VCCIOPLL
DBI#2
LQG21F4R7N00_0805
VCCA
H_DBI#3
AE23
V21
VCCA
DBI#3
1
2
1
MISC
LQG21F4R7N00_0805
VCCSENSE
H_DBR#
A5
AE25
<41> VCCSENSE
VCCSENSE
DBR#
H_DBR# <8>
L25
+ C644
VSSSENSE
2
A4
<41> VSSSENSE
VSSSENSE
R311
C320
AF3
+1.2VP
VCCVIDLB
@1U_0603_10V6K
MISC
H_PROCHOT#
+CPU_CORE
C3
1
2
2
PROCHOT#
33U_D2_16VM
VSSA
100K_0402_1%
AD22
V6
1
VSSA
MCERR#
RP61
ITP
H_SLP#
AB26
SLP#
H_SLP# <20>
@0_4P2R_0402_5%
1 ITP_CLK0
4
AC26
A22
<16> CLK_CPU_ITP
ITP_CLK0
CLK
NC1
2 ITP_CLK1
3
AD26
<16> CLK_CPU_ITP#
GROUND
MISC
A7
ITP_CLK1
NC2
AF25
NC3
B
B
R302
1 61.9_0603_1%
2
L24
AF24
COMP0
NC4
R300
1 61.9_0603_1%
2
P1
AE21
RP62
COMP1
NC5
Comp0/1 need keep 25
3
2
<8> CLK_ITP
mils trace width
4
1
<8> CLK_ITP#
+1.2VP
0_4P2R_0402_5%
R467
R572
49.9_0402_1%
ITP_CLK0
2.43K_0603_1%
1
2
+3VS
FOX_PZ47803-274A-42_Prescott
2
1
+1.2VP
1
R573
49.9_0402_1%
ITP_CLK1
+CPU_CORE
1
2
H_VID_PWRGD <35>
C317
0.1U_0402_16V4Z
2
+5VS
R303
<36,38>
SHDN_1632#
CPU_VID[0
5]
<8,41>
8.2K_0402_5%
1K_0402_5%
GTL Reference Voltage
+CPU_CORE
+5VS
R307
Layout note :
+CPU_CORE
470_0402_5%
1
<21,33>
PROCHOT#
1. Place R_A and R_B near CPU (Within 1.5").
R334
R333
C174
R337
R265
H_THERMDA
0.1U_0402_16V4Z
2
2
Q62
60.4_0603_1%
8.2K_0402_5%
R316
Q26
2N7002_SOT23
+H_GTLREF
470_0402_5%
MMBT3904_SOT23
1
@10K_0402_5%
U57
C470
1
3
R320
2200P_0603_50V7K
H_PROCHOT#
2
1
D+
VDD1
<39> H_PROCHOT#
2
H_THERMTRIP#
1
2
A
A
H_THERMTRIP# <21>
H_THERMDC
1
3
6
2
D-
ALERT#
R261
470_0402_5%
102_0603_1%
C319
Q64
8
4
<8,32> SMB_EC_CK2
SCLK
THERM#
1U_0603_6.3V6M
MMBT3904_SOT23
2
Dell-Compal Confidential
2
<10,17,20,24,25,27,28,32,35> PCIRST#
7
5
<8,32> SMB_EC_DA2
SDATA
GND
Q59
Compal Electronics, Inc.
MMBT3904_SOT23
Title
ADM1032ARM_RM8
Prescott / P4 uFCPGA & Thermal sensor (2/2)
Intel change to 0.63VCC, then 60.4/102
CPU Temperature Sensor
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
Custom
Date:
Tuesday, February 25, 2003
Sheet
6
o f
44
5
4
3
2
1
12
F8
AE11
VSS_129
VSS_57
G21
AE13
VSS_130
VSS_58
G24
AE15
VSS_131
VSS_59
G3
AE17
VSS_132
VSS_60
G6
AE19
VSS_133
VSS_61
12
J2
AE22
VSS_134
VSS_62
J22
AE24
VSS_135
VSS_63
J25
AE7
VSS_136
VSS_65
J5
AE9
VSS_137
VSS_66
K21
AF1
VSS_138
VSS_67
12
K24
AF10
VSS_139
VSS_68
K3
AF12
VSS_140
VSS_69
K6
AF14
VSS_141
VSS_70
L1
AF16
VSS_142
VSS_71
L23
AF18
VSS_143
VSS_72
L26
AF20
VSS_144
VSS_73
L4
AF6
VSS_145
VSS_75
M2
AF8
VSS_146
VSS_76
M22
B10
VSS_147
VSS_77
M25
B12
VSS_148
VSS_78
M5
B14
VSS_149
VSS_79
N21
B16
VSS_150
VSS_80
N24
B18
VSS_151
VSS_81
N3
B20
VSS_152
VSS_82
N6
B23
VSS_153
VSS_83
P2
B26
VSS_154
VSS_84
P22
B4
VSS_155
VSS_85
P25
B8
VSS_156
VSS_86
P5
C11
VSS_157
VSS_87
R1
C13
VSS_158
VSS_88
R23
C15
VSS_159
VSS_89
12
R26
C17
VSS_160
VSS_90
R4
C19
VSS_161
VSS_91
T21
C2
VSS_162
VSS_92
T24
C22
VSS_163
VSS_93
T3
C25
VSS_164
VSS_94
T6
C5
VSS_165
VSS_95
U2
C7
VSS_166
VSS_96
U22
C9
VSS_167
VSS_97
U25
D10
VSS_168
VSS_98
U5
D12
VSS_169
VSS_99
V1
D14
VSS_170
VSS_100
V23
D16
VSS_171
VSS_101
V26
D18
VSS_172
VSS_102
V4
D20
VSS_173
VSS_103
W21
D21
VSS_174
VSS_104
W24
D24
VSS_175
VSS_105
W3
D3
VSS_176
VSS_106
W6
D6
VSS_177
VSS_107
Y2
D8
VSS_178
VSS_108
Y22
E1
D
VSS_179
VSS_109
Y25
E11
VSS_180
VSS_110
2
Y5
E13
VSS_181
VSS_111
G
E15
VSS_112
S
E17
VSS_113
E19
VSS_114
CPU_VID0
AE5
E23
VID0
VSS_115
CPU_VID1
AE4
E26
VID1
VSS_116
CPU_VID2
AE3
E4
VID2
VSS_117
CPU_VID3
3
1
AE2
E7
VID3
VSS_118
CPU_VID4
AE1
E9
VID4
VSS_119
CPU_VID5
AD3
F10
VID5
VSS_120
F12
VSS_121
F14
VSS_122
AD2
F16
VIDPWRGD
VSS_123
F18
VSS_124
3
1
12
F2
VSS_125
F22
VSS_126
F25
VSS_127
AF4
F5
VCCVID
VSS_128
AF26
SKTOCC#
12
3
1
1
2
1
2
A B C D E F G H I J +CPU_CORE Layout note : Layout
A
B
C
D
E
F
G
H
I
J
+CPU_CORE
Layout note :
Layout note :
1
1
1
1 1
Place close to CPU, Use 2~3 vias per PAD.
+
+
+
1
Place 22uF caps x31 pcs, populated 14pcs.
Place close to CPU power and
ground pin as possible
C645
+ C646
C647
+ C649
C648
1
@470U_D4_2.5VM
470U_D4_2.5VM
@470U_D4_2.5VM
@470U_D4_2.5VM
470U_D4_2.5VM
(<1inch)
2
2
2
2
2
+CPU_CORE
For Desktop's CPU:
470uFx15/10m ohm each
Total 0.67m ohm
1
1
1
1
1
+CPU_CORE
Place on CPU inside
+
+
+
+
C650
+ C652
C651
C653
C654
@470U_D4_2.5VM
@470U_D4_2.5VM
470U_D4_2.5VM
@470U_D4_2.5VM
470U_D4_2.5VM
1
1
1
1
2
2
2
2
2
C655
C656
C657
C658
2
@22U_1210_6.3V6M
22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
2
2
2
2
2
+CPU_CORE
+CPU_CORE
1
1
1
+
+
+
C661
C662
C663
470U_D4_2.5VM
@470U_D4_2.5VM
470U_D4_2.5VM
1
1
1
1
1
1
2
2
2
C666
C667
C668
C669
C670
C671
@22U_1210_6.3V6M
22U_1210_6.3V6M
22U_1210_6.3V6M
22U_1210_6.3V6M
22U_1210_6.3V6M
22U_1210_6.3V6M
2
2
2
2
2
2
3
+5VS
3
+12V_FAN
Note:When use +5V Fan,
the J2 must be opened. It
prevent the +5VS short to
L53
@FBM-11-201209-300AT_0805
+CPU_CORE
Please place these cap on the socket north side
J2
+12V_FAN
JOPEN
+5VS
+3VS
+12VALW
1
1
1
1
1
Fan1 Control circuit
C673
C674
C675
C676
C677
22U_1210_6.3V6M
@22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
22U_1210_6.3V6M
2 C678
R468
2
2
2
2
2
R469
10K_0402_5%
0.1U_0402_16V4Z
C672
10K_0402_5%
1
U76A
4
0.1U_0402_16V4Z
1
4
LM358
R470
FAN1_TACH <32>
+CPU_CORE
3
+
S
2
FAN1_ON
FAN1_TACH_ON
1
3
1
2
2
Q66
G
HMBT2222A_SOT23
2
<32> EN_FAN1
-
Q65
1
1
1 1
1 1
1
1K_0402_5%
D
1
C679
C680
C681
C682
C683
C684
SI3457DV-T1_TSOP6
C685
@22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
@22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
C686
0.47U_1206_16V4Z
2
2
2 2
2 2
2
1U_0603_10V4Z
2
1
2
C687
@2200P_0603_50V7K
R471
Molex_53398-0410
FAN1_VOUT
1
2
4
4
3
3
FAN1_TACH_FB
1
2
5
300K_0402_5%
2
5
R472
1
1
+
C688
100K_0402_5%
JP28
D47
100U_D_16VM
C27
RB751V_SOD323
1
1
2
1000P_0402_50V7K
JP34
C22
FAN1_VOUT
+CPU_CORE
1
Please place these cap on the socket south side
1000P_0402_50V7K
FAN1_TACH_FB
2
2
2
3
@MOLEX_53398-0390_3P
1
1
1
1
1
Note:R471 change to
66.5K_1%, if use +5V Fan
C689
C690
C691
C692
C693
@22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
+3VS
2
2
2
2
2
+5VS
+5VS
6
6
+CPU_CORE
Fan2 Control circuit
R473
10K_0402_5%
R474
10K_0402_5%
1
1
1
1
1
FAN2_TACH <32>
U76B
C694
C695
C696
C697
C698
D Q67
LM358
R475
@22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
22U_1210_6.3V6M
@22U_1210_6.3V6M
G
5
<32> EN_FAN2
+
2
2
2
2
2
FAN2_ON
FAN2_TACH_ON
7
3
1
2
2
Q68
S
SI3456DV-T1_TSOP6
HMBT2222A_SOT23
6
-
1
1
1K_0402_5%
C699
C700
1U_0603_10V4Z
0.47U_1206_16V4Z
2
2
C701
@2200P_0603_50V7K
7
7
FAN2_VFB
1
2
R476
100K_0402_5%
JP29
FAN2_VOUT
1
2
1
FAN2_TACH_FB
2
1
3
R477
1
1
150K_0603_5%
C702
MOLEX_53398-0390_3P
D48
10U_1206_10V4Z
C28
C29
2
1000P_0402_50V7K
1000P_0402_50V7K
RB751V_SOD323
2
2
Dell-Compal Confidential
Compal Electronics, Inc.
8
8
Title
CPU Decoupling CAP. & Fan control
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
Custom
Date:
Tuesday, February 25, 2003
Sheet
7
o f
44
A
B
C
D
E
F
G
H
I
J
12
12
84
2
1
2
1
1
1
2
2
45
12
4
5
6
6
1
2
12
12
13
12
13
12
10 9 8 7 6 5 4 3 2 1 +3VS <6,41> CPU_VID[0 5] H
10
9
8
7
6
5
4
3
2 1
+3VS
<6,41> CPU_VID[0 5]
H
H
CPU_VID0
2
1
R260
1K_0402_5%
CPU_VID1
2
1
R259
1K_0402_5%
VID [0
5]
CPU_VID2
2
1
R258
1K_0402_5%
CPU_VID3
2
1
R257
1K_0402_5%
VID
43210
V
CPU_VID4
2
1
R256
1K_0402_5%
0
1
0
1
1
1.5750
G
CPU_VID5
1
1
1
0
G
2
0
0 1.5500
R478
1K_0402_5%
0
1
1
0
1 1.5250
VID 5 for Prescott-MT
0
1
1
1
0
1.5000
0
1
1
1
1
1.4750
1
0
0
0
0
1.4500
1
0
0
0
1
1.4250
+3VALW
1
0
0
1
0
1.4000
+CPU_CORE
R479
1
0
0
1
1
1.3750
+CPU_CORE
H_DBR#
1
1
2
F
F
JP30
1
0
1
00
1.3500
C703
150_0402_5%
0.1U_0402_16V4Z
28
1
0
1
0
1
1.3250
2
VTT1
27
R480
VTT0
+CPU_CORE
26
1
0
1
1
0
1.3000
VTAP
H_DBR#
75_0603_1%
25
<6> H_DBR#
DBR#
ITP_TDO
24
1
2
1
0
1
1
1
1.2750
DBA#
23
<6> ITP_BPM#0
BPM0#
22
R481
1
1
0
0
0
1.2500
GND5
21
<6> ITP_BPM#1
BPM1#
150_0402_5%
20
1
1
0
0
1
1.2250
GND4
ITP_TDI
19
1
2
<6> ITP_BPM#2
BPM2#
18
1
1
0
1
0
1.2000
GND3
17
<6> ITP_BPM#3
BPM3#
ITP_TMS
16
1
2
1
1
0
1
1
1.1750
GND2
R482
15
E
<6> ITP_BPM#4
BPM4#
E
14
39.2_0603_1%
1
1
1
0
0
1.1500
GND1
13
<6> ITP_BPM#5
BPM5#
ITP_RESET#
1
2
12
R484
1
1
1
0
1
1.1250
<6,9> H_RESET#
RESET#
R483
ITP_TCK
ITP_TRST#
11
1
2
FBO
150_0402_5%
680_0402_5%
10
1
1
1
1
0
1.1000
GND0
9
<6> CLK_ITP
BCLKP
8
1
1
1
1
1
off
<6> CLK_ITP#
BCLKN
ITP_TDO
ITP_TCK
7
1
R485
2
<6> ITP_TDO
TDO
6
NC2
ITP_TCK
27.4_0603_1%
5
<6> ITP_TCK
TCK
4
NC1
ITP_TRST#
<6> ITP_TRST#
3
2 TRST#
ITP_TMS
<6> ITP_TMS
1 TMS
ITP_TDI
<6> ITP_TDI
TDI
1
1
D
D
C704
C705
@MOLEX_52435-2891
@2.2P_0402_16VCJ
@2.2P_0402_16VCJ
2
2
ITP DEBUG POINT
C
C
+5VS
1
C482
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C394
2
ITP Debug Connector
1
2
U25
U23
SMB_EC_DA2
SMB_EC_DA2
8
8
<6,32> SMB_EC_DA2
+5VS
1 2 SDA
VCC
2 1 SDA
VCC
SMB_EC_CK2
SMB_EC_CK2
7
7
1
2
<6,32> SMB_EC_CK2
SCL
A0
SCL
A0
R308
10K_0402_5%
6
6
3 OS#
A1
3 4 OS#
A1
B
5
1
2
5
B
4 GND
A2
GND
A2
R351
1K_0402_5%
LM75CIMMX-5_MSOP8
LM75CIMMX-5_MSOP8
R486
1K_0402_5%
Address:1001_000X
Address:1001_001X
Dell-Compal Confidential
Compal Electronics, Inc.
A
A
Title
CPU VID & ITP PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
Custom
Date:
Tuesday, February 25, 2003
Sheet
8
o f
44
10
9
8
7
6
5
4
3
2
1
30
29
GND7
GND6
12
5 4 3 2 1 HA#[3 31] HXSWING and HYSWING Ref. Voltage 1.Place R487 and
5
4
3
2
1
HA#[3 31]
HXSWING and HYSWING Ref. Voltage
1.Place R487 and R490 within 0.5" of U77 pin K28
HA#[3
31]
<5>
H_REQ#[0 4]
H_REQ#[0
4]
<5>
HD#[0 63]
+CPU_CORE
+CPU_CORE
2.Place R488 and R489 within 0.5" of U77 pin B18
3.+HYSWING, +HXSWING 10mil trace, 20mil space.
HD#[0
63]
<5>
U77A
R487
R488
301_0402_1%
301_0402_1%
D
Montara-GT
D
HA#3
HD#0
+HYSWING
+HXSWING
P23
K22
HA#3
HD#0
HA#4
HD#1
T25
H27
1
1
HA#4
HD#1
HA#5
HD#2
R490
R489
T28
K25
HA#5
HD#2
HA#6
HD#3
C706
C707
R27
L24
HA#6
HD#3
HA#7
HD#4
150_0402_1%
150_0402_1%
U23
J27
HA7#
HD#4
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
HA#8
HD#5
U24
G28
HA#8
HD#5
HA#9
HD#6
R24
L27
HA#9
HD#6
HA#10
HD#7
U28
L23
HA#10
HD#7
HA#11
HD#8
V28
L25
HA#11
HD#8
HA#12
HD#9
U27
J24
HA#12
HD#9
HA#13
HD#10
T27
H25
HA#13
HD#10
HA#14
HD#11
V27
K23
Host data Ref. Voltage
HA#14
HD#11
HA#15
HD#12
U25
G27
HA#15
HD#12
HA#16
HD#13
V26
K26
HA#16
HD#13
HA#17
HD#14
Y24
J23
HA#17
HD#14
+CPU_CORE
HA#18
HD#15
V25
H26
HA#18
HD#15
HA#19
HD#16
V23
F25
HA#19
HD#16
HA#20
HD#17
W25
F26
HA#20
HD#17
HA#21
HD#18
R491
Y25
B27
HA#21
HD#18
HA#22
HD#19
49.9_0603_1%
AA27
H23
1.Place R491 and R492 within 0.5" of U77 pin K21 J21 J17
2.Place C708 C709 C710 C711 in order from U77 to divider
3.+HVREF 10mil trace, 20mil space.
HA#22
HD#19
HA#23
HD#20
W24
E27
HA#23
HD#20
HA#24
HD#21
W23
G25
HA#24
HD#21
HA#25
HD#22
+HVREF
W27
F28
HA#25
HD#22
HA#26
HD#23
Y27
D27
1
1
1
1
HA#26
HD#23
HA#27
HD#24
R492
AA28
G24
HA#27
HD#24
HA#28
HD#25
100_0603_1%
C708
C709
C710
C711
W28
C28
HA#28
HD#25
HA#29
HD#26
1U_0402_6.3V4Z
0.1U_0402_10V6K
@0.1U_0402_10V6K
@0.1U_0402_10V6K
AB27
B26
HA#29
HD#26
2
2
2
2
C
HA#30
HD#27
Y26
G22
C
HA#30
HD#27
HA#31
HD#28
AB28
C26
HA#31
HD#28
HD#29
E26
HD#29
H_REQ#0
HD#30
R28
G23
HREQ#0
HD#30
H_REQ#1
HD#31
P25
B28
HREQ#1
HD#31
H_REQ#2
HD#32
R23
B21
HREQ#2
HD#32
H_REQ#3
HD#33
R25
G21
Host Address Ref. Voltage
HREQ#3
HD#33
H_REQ#4
HD#34
T23
HOST
C24
HREQ#4
HD#34
HD#35
T26
C23
<6> H_ADSTB#0
HADSTB#0
HD#35
HD#36
AA26
D22
<6> H_ADSTB#1
HADSTB#1
HD#36
+CPU_CORE
+CPU_CORE
HD#37
C25
HD#37
CLK_MCH_BCLK#
HD#38
AD29
E24
<16> CLK_MCH_BCLK#
BCLK#
HD#38
CLK_MCH_BCLK
HD#39
AE29
D24
<16> CLK_MCH_BCLK
BCLK
HD#39
+HYSWING
HD#40
R493
R494
K28
G20
HYSWING
HD#40
R495
27.4_0402_1% +HXSWING
HD#41
49.9_0603_1%
49.9_0603_1%
B18
E23
HXSWING
HD#41
+HYRCOMP
HD#42
1
2
H28
B22
HYRCOMP
HD#42
+HXRCOMP
HD#43
1
2
B20
B23
HXRCOMP
HD#43
R496
27.4_0402_1%
HD#44
+HAVREF
+HCCVREF
F23
HD#44
HD#45
K21
F21
1 1
1
1
HDVREF0
HD#45
HD#46
R497
R498
J21
C20
HDVREF1
HD#46
+HVREF
HD#47
100_0603_1%
100_0603_1%
J17
C21
HDVREF2
HD#47
+HCCVREF
HD#48
C713
C715
Y28
G18
HCCVREF
HD#48
2
2
2
+HAVREF
HD#49
2 C712
C714
Y22
E19
HAVREF
HD#49
HD#50
0.1U_0402_10V6K
0.1U_0402_10V6K
E20
HD#50
H_DSTBN#0
HD#51
J28
G17
HDSTBN#0
HD#51
H_DSTBN#1
HD#52
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C27
D20
HDSTBN#1
HD#52
H_DSTBN#2
HD#53
E22
F19
HDSTBN#2
HD#53
H_DSTBN#3
HD#54
D18
C19
HDSTBN#3
HD#54
H_DSTBP#0
HD#55
K27
C17
HDSTBP#0
HD#55
B
H_DSTBN#[0 3]
B
H_DSTBP#1
HD#56
D26
F17
<6> H_DSTBN#[0 3]
HDSTBP#1
HD#56
H_DSTBP#2
HD#57
E21
B19
HUBLink reference Voltage
HDSTBP#2
HD#57
H_DSTBP#3
HD#58
E18
G16
HDSTBP#3
HD#58
+1.5VS
H_DBI#0
HD#59
J25
E16
DINV0#
HD#59
H_DSTBP#[0 3]
H_DBI#1
HD#60
E25
C16
<6> H_DSTBP#[0 3]
DINV1#
HD#60
H_DBI#2
HD#61
B25
E17
DINV2#
HD#61
H_DBI#3
HD#62
G19
D16
DINV3#
HD#62
HD#63
R499
C18
HD#63
H_DBI#[0 3]
80.6_0402_1%
F15
<6> H_DBI#[0
3]
<6,8> H_RESET#
CPURST#
HI[0 10]
HI0
U7
<20> HI[0 10]
HL_0
HI1
U4
HL_1
HI2
+HUB_PSWING
U3
L28
HL_2
ADS#
H_ADS# <5>
HI3
V3
M25
1
1
HL_3
HTRDY#
H_TRDY# <6>
HI4
C716
C717
W2
N24
HL_4
DRDY#
H_DRDY#
<6>
HI5
0.01U_0402_25V7Z
0.1U_0402_10V6K
W6
M28
HL_5
DEFER#
H_DEFER# <5>
HI6
R500
V6
N28
HL_6
HITM#
H_HITM# <5>
2
2
HI7
51.1_0603_1%
W7
N27
HL_7
HIT#
H_HIT# <5>
HI8
T3
P27
HL_8
HLOCK#
H_LOCK# <5>
HI9
V5
M23
HL_9
BREQ0#
H_BREQ0# <5>
HI10
+HUB_VREF
V4
N25
HL_10
BNR#
H_BNR# <5>
W3
P28
H_BPRI# <5>
HLSTB
BPRI#
V2
M26
1
1
<20> HUB_PSTRB
HLSTB#
DBSY#
H_DBSY# <6>
H_RS#0
C718
R501
C719
T2
N23
<20> HUB_PSTRB#
HLRCOMP
RS#0
HLRCOMP
H_RS#1
0.01U_0402_25V7Z
0.1U_0402_10V6K
1
2
U2
P26
+1.5VS
PSWING
RS#1
+HUB_PSWING
H_RS#2
40.2_0603_1%
W1
M27
HLVREF
RS#2
2
2
R502
+HUB_VREF
48.7_0603+1%
H_RS#[0 2]
H_RS#[0
2]
<6>
RG82G4350MA1_uFCBGA732_MONTARA-GT
A
A
Dell-Compal Confidential
Compal Electronics, Inc.
Title
Montara-GT (1/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Abacus-MT LA-1682
0.2
Date:
Tuesday, February 25, 2003
Sheet
9
o f
44
5
4
3
2
1
HUB I/F
12
12
12
12
12
12
12
12
12
12
12
12
12
5 4 3 2 1 U77B Montara-GT AGP_AD[0 31] AGP_AD3 R3 C9 <17> AGP_AD[0 31]
5
4
3
2
1
U77B
Montara-GT
AGP_AD[0 31]
AGP_AD3
R3
C9
<17> AGP_AD[0 31]
DVOBD0/GAD3
BLUE
INTCRT_B <17>
AGP_AD2
R5
D9
DVOBD1/GAD2
BLUE#
AGP_AD14
AGP_AD5
R6
C8
DVOBD2/GAD5
GREEN
INTCRT_G <17>
AGP_AD13
AGP_AD4
R4
D8
DVOBD3/GAD4
GREEN#
AGP_AD31
AGP_AD7
P6
A7
DVOBD4/GAD7
RED
INTCRT_R <17>
AGP_AD6
P5
A8
DVOBD5/GAD6
RED#
AGP_AD8
R506
D
N5
H10
D
DVOBD6/GAD8
HSYNC
INT_HSYNC <17>
1@127_0603_1%
P2
J9
<17> AGP_CBE#0
DVOBD7/GCBE0#
VSYNC
INT_VSYNC <17>
AGP_AD10
N2
E8
1
2
DVOBD8/GAD10
REFSET
AGP_AD9
N3
B6
DVOBD9/GAD9
DDCACLK
INTDDCCK <17>
R503
AGP_AD12
+3VS
M1
G9
DVOBD10/GAD12
DDCADATA
INTDDCDA <17>
R505
AGP_AD11
M5
DVOBD11/GAD11
100K_0402_5%
1@100K_0402_5%
P3
<17> AGP_ADSTB0
DVOBCLK/GADSTB0
R507
P4
G14
<17> AGP_ADSTB0#
DVOBCLK#/GADSTB0#
IYAM0
LCD_A0- <18>
R504
AGP_AD0
LCD_DDCCLK
T6
E15
1
2
DVOBHSYNC/GAD0
IYAM1
LCD_A1- <18>
1@100K_0402_5%
AGP_AD1
T5
C15
DVOBVSYNC/GAD1
IYAM2
LCD_A2- <18>
2.2K_0402_5%
L2
C13
<17> AGP_CBE#1
DVOBBLANK#/GCBE1#
IYAM3
AGP_AD14
M2
F14
DVOBFLDSTL/GAD14
IYAP0
LCD_A0+ <18>
E14
IYAP1
LCD_A1+ <18>
AGP_AD30
R508
G2
C14
R509
DVOBCINTR#/GAD30
IYAP2
LCD_A2+ <18>
AGP_AD13
LCD_DDCDATA
M3
B13
1
2
DVOBCCLKINT/GAD13
IYAP3
AGP_AD30
1
2
H12
+1.5VS_DVO
IYBM0
LCD_B0- <18>
2.2K_0402_5%
J3
E12
<17> AGP_ADSTB1
DVOCCLK/GADSTB1
IYBM1
LCD_B1- <18>
1@100K_0402_5%
J2
C12
<17> AGP_ADSTB1#
DVOCCLK#/GADSTB1#
IYBM2
LCD_B2- <18>
AGP_AD17
K6
G11
DVOCHSYNC/GAD17
IYBM3
AGP_AD16
L5
G12
DVOCVSYNC/GAD16
IYBP0
LCD_B0+ <18>
AGP_AD18
+CPU_CORE
L3
E11
DVOCBLANK#/GAD18
IYBP1
LCD_B1+ <18>
R570
AGP_AD31
H5
C11
DVOCFLDSTL/GAD31
IYBP2
LCD_B2+ <18>
H_DPSLP#
G10
2
1
IYBP3
D14
ICLKAM
LCD_ACLK- <18>
K7
E13
<17> AGP_IRDY#
MI2CCLK/GIRDY#
ICLKAP
LCD_ACLK+ <18>
@56 _0402_1%
N6
E10
<17> AGP_DEVSEL#
MI2CDATA/GDEVSEL#
ICLKBM
LCD_BCLK- <18>
N7
F10
<17> AGP_TRDY#
MDVICLK/GTRDY#
ICLKBP
LCD_BCLK+ <18>
M6
<17> AGP_FRAME#
MDVIDATA/GFRAME#
C
LCD_DDCCLK
P7
B4
C
<17> AGP_STOP#
MDDCCLK/GSTOP#
DDCPCLK
LCD_DDCCLK <18>
AGP_AD15
LCD_DDCDATA
T7
C5
MDDCDATA/GAD15
DDCPDATA
LCD_DDCDATA <18>
R511
1@0_0402_5%
G8
PANELBKLTCTL
AGP_AD19
PANEL_BKEN
K5
F8
1
2
DVOCD0/GAD19
PANELBKLTEN
ENABKL <17,18,33>
AGP_AD20
K1
A5
DVOCD1/GAD20
PANELVDDEN
ENVDD <18>
+AGPREF
AGP_AD21
K3
DVOCD2/GAD21
AGP_AD22
R512
1@1.5K_0603_1%
K2
DVOCD3/GAD22
AGP_AD23
1
J6
A10
1
2
DVOCD4/GAD23
LIBG
J5
<17> AGP_CBE#3
DVOCD5/GCBE3#
AGP_AD25
H2
D12
DVOCD6/GAD25
RSVD3
AGP_AD24
H1
F12
2
DVOCD7/GAD24
RSVD4
AGP_AD27
H3
B12
DVOCD8/GAD27
RSVD5
C720
AGP_AD26
H4
DVOCD9/GAD26
AGP_AD29
H6
DVOCD10/GAD29
CLK_MCH_DISPLAY <16>
0.1U_0402_10V6K
AGP_AD28
CLK_MCH_DISPLAY
+3VS
G3
B7
DVOCD11/GAD28
DREFCLK
DREFSSCLK
R514
B17
DREFSSCLK
1K_0402_5%
H9
LCLKCTLA
AGP_SBA[0 7]
LCLKCTLB
C6
1
2
<17> AGP_SBA[0 7]
LCLKCTLB
LCLKCTLB H:1.2V
AGP_SBA0
E5
PSB Voltage Select
ADDID0/GSBA0
AGP_SBA1
F5
ADDID1/GSBA1
+1.5VS
AGP_SBA2
E3
AA22
ADDID2/GSBA2
DPWR#
AGP_SBA3
H_DPSLP#
L41
E2
Y23
ADDID3/GSBA3
DPSLP#
AGP_SBA4
ADDID4/GSBA4
RSTIN#
H_DPSLP# <6,20>
PCIRST# <6,17,20,24,25,27,28,32,35>
C722
G5
AD28
AGP_SBA5
FCM2012C-800_0805
F4
ADDID5/GSBA5
R515
AGP_SBA6
4.7U_0805_6.3V6K
G6
J11
1
2
PM_PWROK <21,32,34>
+SVDD
+3VS
ADDID6/GSBA6
PWROK
AGP_SBA7
F6
ADDID7/GSBA7
1@1K_0402_5%
R516
10K_0603_1%
C723
D6
1
2
+3VS
1
1
1
EXTTS0
B
B
C721
L7
<17> AGP_PAR
DVODETECT/GPAR
AGP_PIPE#
0.1U_0402_10V6K
0.1U_0402_10V6K
D5
<17> AGP_PIPE#
DPMS/GPIPE#
R517
1@0_0402_5%
F1
+AGPREF
GVREF
2
2
2
1
2
F7
D
<17,21>
AGP_BUSY#
AGPBUSY#
D1
B1
DVO_GRCOMP
NC0
CLK_MCH_66M
2
Y3
AH1
<21> RTCCLK
<16> CLK_MCH_66M
GCLKIN
NC1
G
R519
0_0402_5%
A2
NC2
Q69
S
R518
F2
AJ2
1
2
<17> AGP_SBSTB
GSBSTB
NC3
1@BSS138_SOT23
F3
A28
<17> AGP_SBSTB#
GSBSTB#
NC4
40.2_0603_1%
B2
AJ28
<17> AGP_GNT#
GGNT#
NC5
+SVDD
B3
A29
<17> AGP_REQ#
GREQ#
NC6
AGP_ST2
C2
B29
<17> AGP_ST2
GST2
NC7
AGP_ST1
C3
AH29
11/12 EMI change to W181-51
<17> AGP_ST1
GST1
NC8
AGP_ST0
U78
C4
AJ29
<17> AGP_ST0
GST0
NC9
D2
AA9
<17> AGP_WBF#
GWBF#
NC10
D3
AJ4
<17> AGP_RBF#
GRBF#
NC11
R520
@22_0402_5%
L4
<17> AGP_CBE#2
GCBE#2
CLK_VCH
SSVCH_OUT
DREFSSCLK
D7
1
5
1
2
RSVD1
<16> CLK_VCH
X1/CLK
CLKOUT
AA5
RSVD2
RG82G4350MA1_uFCBGA732_MONTARA-GT
R521
@1K_0402_5%
1 2
7
2
FS1
X2
R523
CLK_MCH_DISPLAY
CLK_MCH_66M
DREFSSCLK
R522
@1K_0402_5%
1 2
8
4
1
2
+SVDD
FS2
SS%
+1.5VS
R528
FS2 FS1
@1K_0402_5%
R524
R525
R526
@1K_0402_5%
R527
@33_0402_5%
@33_0402_5%
@33_0402_5%
AGP_ST0
@W181G_SOIC8
@1K_0402_5%
1
2
0
0
28<
<38
R529
0
1
38<
<48
A
1K_0402_5%
1
1 1
SS% L : -0.625%<
SS% H : -1.875%<
<0.625%
A
<1.875%
C724
C725
AGP_ST1
1
2
*
1
0
46<
<60
C726
@10P_0402_25V8K
@10P_0402_25V8K
@10P_0402_25V8K
R530
1
1
58<
<75
2
2 2
1K_0402_5%
AGP_ST2
1
2
Compal Electronics, Inc.
Title
Montara-GT (2/4)
Size
Document Number
Rev
Abacus-MT LA-1682
0.2
Date:
Tuesday, February 25, 2003
Sheet
10
o f
44
5
4
3
2
1
12
12
12
12
13
12
12
12
12
DVO
CLKSMISCNC
LVDS
DAC
3
6
GND
VDD
12

5

4

3

2

1

D

C

5 4 3 2 1 D C B A D C B A U77C DDR_SMA[0 12]

B

A

D

C

5 4 3 2 1 D C B A D C B A U77C DDR_SMA[0 12]

B

A

U77C

DDR_SMA[0 12] DDR_SDQ[0 63] Montara-GT DDR_SDQ[0 63] <13> DDR_SMA0 DDR_SDQ0 AC18 AF2 SMA0 SDQ0
DDR_SMA[0 12]
DDR_SDQ[0
63]
Montara-GT
DDR_SDQ[0
63]
<13>
DDR_SMA0
DDR_SDQ0
AC18
AF2
SMA0
SDQ0
DDR_SMA1
DDR_SDQ1
AD14
AE3
SMA1
SDQ1
DDR_SMA2
DDR_SDQ2
AD13
AF4
SMA2
SDQ2
DDR_SMA3
DDR_SDQ3
AD17
AH2
SMA3
SDQ3
DDR_SMA4
DDR_SDQ4
+2.5V
AD11
AD3
SMA4
SDQ4
DDR_SMA5
DDR_SDQ5
AC13
AE2
SMA5
SDQ5
DDR_SMA6
DDR_SDQ6
AD8
AG4
SMA6
SDQ6
DDR_SMA7
DDR_SDQ7
AD7
AH3
SMA7
SDQ7
DDR_SMA8
DDR_SDQ8
R531
AC6
AD6
SMA8
SDQ8
DDR_SMA9
DDR_SDQ9
604_0603_1%
AC5
AG5
SMA9
SDQ9
DDR_SMA10
DDR_SDQ10
AC19
AG7
SMA10
SDQ10
DDR_SMA11
DDR_SDQ11
AD5
AE8
SMA11
SDQ11
DDR_SMA12
DDR_SDQ12
+SMVSWINGL
AB5
AF5
SMA12
SDQ12
DDR_SDQ13
AH4
SDQ13
DDR_SDQS[0
7]
DDR_SDQ14
AF7
SDQ14
DDR_SDQ15
R532
AH6
SDQ15
DDR_SDQS0
MEMORY
DDR_SDQ16
150_0603_1%
AG2
AF8
SDQS0
SDQ16
DDR_SDQS1
DDR_SDQ17
AH5
AG8
SDQS1
SDQ17
DDR_SDQS2
DDR_SDQ18
AH8
AH9
SDQS2
SDQ18
DDR_SDQS3
DDR_SDQ19
AE12
AG10
SDQS3
SDQ19
DDR_SDQS4
DDR_SDQ20
AH17
AH7
SDQS4
SDQ20
DDR_SDQS5
DDR_SDQ21
AE21
AD9
SDQS5
SDQ21
DDR_SDQS6
DDR_SDQ22
AH24
AF10
SDQS6
SDQ22
DDR_SDQS7
DDR_SDQ23
AH27
AE11
SDQS7
SDQ23
DDR_SDQ24
AD15
AH10
SDQS8
SDQ24
DDR_SDQ25
AH11
SDQ25
DDR_SDQ26
AG13
SDQ26
DDR_SWE#
DDR_SDQ27
AD25
AF14
<13,14>
DDR_SWE#
SWE#
SDQ27
DDR_SRAS#
DDR_SDQ28
+2.5V
AC21
AG11
<13,14>
DDR_SRAS#
SRAS#
SDQ28
DDR_SCAS#
DDR_SDQ29
AC24
AD12
<13,14>
DDR_SCAS#
SCAS#
SDQ29
DDR_SDQ30
AF13
SDQ30
DDR_SDQ31
AH13
SDQ31
DDR_CLK0
DDR_SDQ32
R533
AB2
AH16
<13> DDR_CLK0
SCK0
SDQ32
DDR_CLK0#
DDR_SDQ33
60.4_0603_1%
AA2
AG17
<13> DDR_CLK0#
SCK0#
SDQ33
DDR_CLK1
DDR_SDQ34
AC26
AF19
<13> DDR_CLK1
SCK1
SDQ34
DDR_CLK1#
DDR_SDQ35
AB25
AE20
<13> DDR_CLK1#
SCK1#
SDQ35
DDR_CLK2
DDR_SDQ36
+SMRCOMP
AC3
AD18
<13> DDR_CLK2
SCK2
SDQ36
DDR_CLK2#
DDR_SDQ37
AD4
AE18
<13> DDR_CLK2#
SCK2#
SDQ37
DDR_CLK3
DDR_SDQ38
AC2
AH18
1
<14> DDR_CLK3
SCK3
SDQ38
DDR_CLK3#
DDR_SDQ39
R534
C727
AD2
AG19
<14> DDR_CLK3#
SCK3#
SDQ39
DDR_CLK4
DDR_SDQ40
60.4_0603_1%
AB23
AH20
<14> DDR_CLK4
SCK4
SDQ40
DDR_CLK4#
DDR_SDQ41
0.1U_0402_10V6K
AB24
AG20
<14> DDR_CLK4#
SCK4#
SDQ41
2
DDR_CLK5
DDR_SDQ42
AA3
AF22
<14> DDR_CLK5
SCK5
SDQ42
DDR_CLK5#
DDR_SDQ43
AB4
AH22
<14> DDR_CLK5#
SCK5#
SDQ43
DDR_SDQ44
AF20
SDQ44
DDR_SDQ45
AH19
SDQ45
DDR_CKE0
DDR_SDQ46
AC7
AH21
<13> DDR_CKE0
SCKE0
SDQ46
DDR_CKE1
DDR_SDQ47
AB7
AG22
<13> DDR_CKE1
SCKE1
SDQ47
DDR_CKE2
DDR_SDQ48
AC9
AE23
<14> DDR_CKE2
SCKE2
SDQ48
DDR_CKE3
DDR_SDQ49
AC10
AH23
<14> DDR_CKE3
SCKE3
SDQ49
DDR_SCS#0
DDR_SDQ50
AD23
AE24
<13> DDR_SCS#0
SCS#0
SDQ50
DDR_SCS#1
DDR_SDQ51
AD26
AH25
<13> DDR_SCS#1
SCS#1
SDQ51
DDR_SCS#2
DDR_SDQ52
AC22
AG23
<14> DDR_SCS#2
SCS#2
SDQ52
DDR_SCS#3
DDR_SDQ53
+2.5V
AC25
AF23
<14> DDR_SCS#3
SCS#3
SDQ53
DDR_SDQ54
AF25
SDQ54
DDR_SDQ55
AG25
SDQ55
DDR_SBS0
DDR_SDQ56
AD22
AH26
<13,14>
DDR_SBS0
SBA0
SDQ56
DDR_SBS1
DDR_SDQ57
R535
AD20
AE26
<13,14>
DDR_SBS1
SBA1
SDQ57
DDR_SDQ58
150_0603_1%
AG28
SDQ58
DDR_SDQ59
AF28
SDQ59
DDR_SDM0
DDR_SDQ60
AE5
AG26
SDM0
SDQ60
DDR_SDM1
DDR_SDQ61
+SMVSWINGH
AE6
AF26
SDM1
SDQ61
DDR_SDM2
DDR_SDQ62
AE9
AE27
SDM2
SDQ62
DDR_SDM3
DDR_SDQ63
AH12
AD27
SDM3
SDQ63
DDR_SDM4
R536
AD19
SDM4
DDR_SDM5
604_0603_1%
AD21
SDM5
DDR_SDM6
AD24
SDM6
DDR_SDM[0 7]
DDR_SDM7
AH28
AG14
SDM7
SDQ64
AH15
AE14
SDM8
SDQ65
+2.5V
AE17
SDQ66
AG16
SDQ67
DDR_SMAB1
AD16
AH14
<14> DDR_SMAB1
SMAB1
SDQ68
DDR_SMAB2
AC12
AE15
<14> DDR_SMAB2
SMAB2
SDQ69
DDR_SMAB4
AF11
AF16
<14> DDR_SMAB4
SMAB4
SDQ70
DDR_SMAB5
R537
AD10
AF17
<14> DDR_SMAB5
SMAB5
SDQ71
@10K_0603_1%
AC15
RCVENOUT#
Need place Via as closed as pin.
AC16
RCVENIN#
R539
+SMRCOMP
SMVREF0
AB1
AJ24
1
2
SDREF
SMRCOMP
SMVREF0
0_0603_5%
+SMVSWINGL
R540
AJ22
1
SMVSWINGL
+SMVSWINGH
C728
@10K_0603_1%
AJ19
SMVSWINGH
RG82G4350MA1_uFCBGA732_MONTARA-GT
0.1U_0402_10V6K
2
12
12
12
12
12
12
12
12

<13,14>

DDR_SMA[0 12]

<13> DDR_SDQS[0 7]

<13> DDR_SDM[0 7]

TOPOLOGY 2 FOR DDR SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#

Dell-Compal Confidential

Compal Electronics, Inc.

Title

Montara-GT (3/4)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Document Number

Abacus-MT LA-1682

Rev

0.2

Date:

Tuesday, February 25, 2003

Sheet

11

o f

44

5

4

3

2

1

5 4 3 2 1 U77D C1 R17 VSS0 VSS91 G1 U17 1.5V for GT
5
4
3
2
1
U77D
C1
R17
VSS0
VSS91
G1
U17
1.5V for GT
VSS1
VSS92
+CPU_CORE
L1
AB17
VSS2
VSS93
+1.5VS
U1
AC17
VSS3
VSS94
U77E
AA1
F18
VSS4
VSS95
C738
AE1
J18
CLOSE TO VCC
VSS5
VSS96
0.1U_0402_10V6K
R2
AA18
Montara-GT
1
VSS6
VSS97
C732
C734
D
AG3
AG18
J15
G15
1
1
1
D
VSS7
VSS98
VCC0
VTTLF0
+
C730
0.1U_0402_10V6K
0.1U_0402_10V6K
C736
AJ3
A19
1
1
P13
H16
VSS8
VSS99
VCC1
VTTLF1
C807
150U_D2_6.3VM
150U_D2_4VM
D4
D19
1
1
1
1
1
1
1
T13
H18
VSS9
VSS100
VCC2
VTTLF2
+
+
0.1U_0402_10V6K
G4
H19
N14
J19
VSS10
VSS101
VCC3
VTTLF3
2
2
2
2
C735
K4
AB19
R14
H20
VSS11
VSS102
VCC4
VTTLF4
C737
C739
N4
AE19
U14
L21
VSS12
VSS103
2
2
2
2
2
2
2
2
2
VCC5
VTTLF5
C729
C731
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_1206_6.3V7K
T4
F20
P15
N21
VSS13
VSS105
VCC6
VTTLF6
C808
150U_D2_6.3VM
10U_1206_6.3V7K
C733
W4
J20
T15
R21
VSS14
VSS106
VCC7
VTTLF7
0.1U_0402_10V6K
0.1U_0402_10V6K
AA4
AA20
AA15
U21
VSS15
VSS107
VCC8
VTTLF8
0.1U_0402_10V6K
AC4
AC20
N16
H22
VSS16
VSS108
VCC9
VTTLF9
AE4
A21
R16
M22
1
1
VSS17
VSS109
VCC10
VTTLF10
+1.5VS
C809
C810
B5
D21
1.5V for GT
U16
P22
VSS18
VSS110
VCC11
VTTLF11
L42
U5
H21
P17
T22
VSS19
VSS111
VCC12
VTTLF12
KC FBM-L11-201209-221LMAT_0805
Y5
M21
CLOSE TO VCCHL
T17
V22
VSS20
VSS112
VCC13
VTTLF13
2
2
+VCCADPLLA
Y6
P21
1
2
1.5V for GT
AA17
Y29
VSS21
VSS113
VCC14
VTTLF14
C745
0.1U_0402_10V6K
AG6
T21
1
AA19
K29
VSS22
VSS114
VCC15
VTTLF15
CLOSE TO PIN
C744
0.1U_0402_10V6K
C7
V21
1
W21
F29
+1.5VS
VSS23
VSS115
VCC16
VTTLF16
+
0.1U_0402_10V6K
E7
Y21
H14
AB29
VSS24
VSS116
VCC17
VTTLF17
C740
C741
C742
0.1U_0402_16V4Z
G7
AA21
1
1
1
1
A26
1
2
VSS25
VSS117
VTTLF18
220U_D2_4VM
0.1U_0402_10V6K
J7
AB21
A20
VSS26
VSS118
2
2
VTTLF19
C746
0.1U_0402_16V4Z
M7
AG21
V1
A18
1
2
VSS27
VSS119
VCCHL0
VTTLF20
R7
B24
Y1
VSS28
VSS120
2
2
2
2
VCCHL1
+VCCADPLLB
C743
C747
0.1U_0402_16V4Z
AA7
F22
1
2
W5
A22
1 2
VSS29
VSS121
VCCHL2
VTTHF0
L43
10U_1206_6.3V7K
C811
AE7
J22
1
1
U6
A24
VSS30
VSS122
VCCHL3
VTTHF1
KC FBM-L11-201209-221LMAT_0805
0.1U_0402_10V6K
C748
0.1U_0402_16V4Z
AJ7
L22
U8
H29
1 2
VSS31
VSS123
VCCHL4
VTTHF2
+
H8
N22
W8
M29
VSS32
VSS124
VCCHL5
VTTHF3
C751
0.1U_0402_16V4Z
K8
R22
V7
V29
1
2
VSS33
VSS125
2
VCCHL6
VTTHF4
C750
P8
U22
V9
VSS34
VSS126
2
VCCHL7
C749
0.1U_0402_10V6K
+1.5VS
C757
T8
W22
AC1
+2.5V
VSS35
VSS127
VCCSM0
C
C752
C755
V8
AE22
D29
AG1
C
VSS36
VSS128
VCCAHPLL
VCCSM1
220U_D2_4VM
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
Y8
A23
Y2
AB3
VSS37
VSS129
VCCAGPLL
VCCSM2
AC8
D23
AF3
VSS38
VSS130
VCCSM3
+1.5VS
+VCCADPLLA
0.1U_0402_10V6K
E9
AA23
1
1
A6
Y4
1
1
1
1
1
1
VSS39
VSS131
VCCADPLLA
VCCSM4
+1.5VS
C753
+VCCADPLLB
C812
C813
L9
AC23
B16
AJ5
VSS40
VSS132
VCCADPLLB
VCCSM5
N9
AJ23
AA6
VSS41
VSS133
VCCSM6
0.1U_0402_10V6K
R9
F24
AB6
VSS42
VSS134
2
2
VCCSM7
2
2
2
2
2
2
L44
U9
H24
E1
AF6
+1.5VS_DVO
VSS43
VSS135
VCCDVO_0
VCCSM8
FLM1608081R8K_0603
W9
K24
J1
Y7
VSS44
VSS136
VCCDVO_1
VCCSM9
L45
C754
C756
0.1U_0402_10V6K
AB9
M24
N1
AA8
VSS45
VSS137
VCCDVO_2
VCCSM10
+1.5VS_DAC
0.1U_0402_10V6K
0.1U_0402_10V6K
AG9
P24
E4
AB8
VSS46
VSS138
BLM21A601SPT_0805
VCCDVO_3
VCCSM11
C10
T24
J4
Y9
VSS47
VSS139
VCCDVO_4
VCCSM12
J10
V24
M4
AF9
VSS48
VSS140
VCCDVO_5
VCCSM13
C760
C766
C768
AA10
AA24
1
1
E6
AJ9
VSS49
VSS141
VCCDVO_6
VCCSM14
C758
0.01U_0402_25V7Z
C763
0.1U_0402_10V6K
0.1U_0402_10V6K
AE10
AG24
1
1
H7
AB10
VSS50
VSS142
VCCDVO_7
VCCSM15
+
+
0.1U_0402_10V6K
D11
A25
1
1
1
1
J8
AA11
1
1
1
1
1
1
VSS51
VSS143
VCCDVO_8
VCCSM16
C761
0.1U_0402_10V6K
C815
C816
F11
D25
L8
AB12
VSS52
VSS144
VCCDVO_9
VCCSM17
@220U_D2_4VM
C814
150U_D2_6.3VM
H11
AA25
M8
AF12
VSS53
VSS145
2
2
2
2
VCCDVO_10
VCCSM18
0.1U_0402_10V6K
AB11
AE25
N8
AA13
VSS54
VSS146
2
2
2
2
VCCDVO_11
VCCSM19
2
2
2
2
2
2
C759
C762
C764
AC11
G26
R8
AJ13
VSS55
VSS147
VCCDVO_12
VCCSM20
0.1U_0402_10V6K
10U_1206_6.3V7K
0.1U_0402_10V6K
C765
C767
AJ11
J26
K9
AB14
VSS56
VSS148
VCCDVO_13
VCCSM21
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
J12
L26
M9
AF15
VSS57
VSS149
VCCDVO_14
VCCSM22
+1.5VS_DLVDS
AA12
N26
1
1
1
P9
AB16
VSS58
VSS150
VCCDVO_15
VCCSM23
AG12
R26
AJ17
VSS59
VSS151
VCCSM24
C817
A13
U26
AB18
VSS60
VSS152
VCCSM25
0.1U_0402_10V6K
C818
C819
C771 & C772 change to 100u
next Reversion
D13
W26
1
1
A9
AF18
+1.5VS_DAC
VSS61
VSS153
2
2
2
VCCADAC0
VCCSM26
C769
F13
AB26
B9
AB20
VSS62
VSS154
VCCADAC1
VCCSM27
C770
0.1U_0402_10V6K 0.1U_0402_10V6K
0.1U_0402_10V6K
H13
A27
B8
AF21
1
1
1
1
1
1
VSS63
VSS155
VSSADAC
VCCSM28
1@47U_1210_6.3V4Z
1@22U_1210_6.3V6M
C771
C772
C773
C774
C820
C821
N13
F27
AJ21
VSS64
VSS156
B
2
2
VCCSM29
+
+
B
R13
AC27
AB22
+1.5VS_ALVDS
VSS65
VSS157
VCCSM30
0.1U_0402_10V6K
U13
AG27
A11
AF24
VSS66
VSS158
VCCALVDS
VCCSM31
2
2
2
2
+1.5VS
+1.5VS_ALVDS
+1.5VS
+1.5VS_DLVDS
150U_D2_4VM
AB13
AJ27
B11
AJ25
VSS67
VSS159
VSSALVDS
VCCSM32
2
2
AE13
AC28
AF27
VSS68
VSS160
L46
L47
VCCSM33
150U_D2_4VM
0.1U_0402_10V6K
0.1U_0402_10V6K
J14
AE28
AC29
VSS69
VSS161
VCCSM34
P14
C29
1
2
1
2
G13
AF29
+1.5VS_DLVDS
VSS70
VSS162
VCCDLVDS0
VCCSM35
FLM1608081R8K_0603
FLM1608081R8K_0603
T14
E29
1
1
1
B14
AG29
VSS71
VSS163
VCCDLVDS1
VCCSM36
C776
AA14
G29
J13
VSS72
VSS164
VCCDLVDS2
C775
C777
+2.5V_QSM
+2.5V
AC14
J29
B15
VSS73
VSS165
VCCDLVDS3
0.1U_0402_10V6K
0.01U_0402_25V7Z
0.1U_0402_10V6K
C778
R16
D15
L29
L48
VSS74
VSS166
2
2
2
0.1U_0402_10V6K
0_0805_5%
H15
N29
VSS75
VSS167
N15
U29
F9
1
2
1
2
+2.5V_TXLVDS
VSS76
VSS168
VCCTXLVDS0
R15
W29
B10
AJ6
1
1
VSS77
VSS169
VCCTXLVDS1
VCCQSM0
KC FBM-L11-201209-221LMAT_0805
U15
AA29
D10
AJ8
VSS78
VSS170
VCCTXLVDS2
VCCQSM1
C779
AB15
AJ10
A12
VSS79
VSS171
AG15
AJ12
VSS80
VSS172
F16
AJ18
VSS81
VSS173
J16
AJ20
1@22U_1206_16V4Z_V1
VCCTXLVDS3
R541
+VCC_GPIO
VCC_ASM
4.7U_1206_10V7K
2
2
C783
C785
0_0603_5%
+1.5VS
AD1
VCCASM0
0.1U_0402_10V6K
1
2
A3
AF1
L50
+3VS
VSS82
VSS174
VCCGPIO_0
VCCASM1
P16
C22
1
A4
+2.5V
+2.5V_TXLVDS
VSS83
VSS176
VCCGPIO_1
FLM1608081R8K_0603
T16
D28
1
1
1
2
VSS84
VSS177
C780
KC FBM-L11-201209-221LMAT_0805
AA16
E28
1
1
1
1
1
1
VSS85
VSS178
@10U_1206_6.3V7K
C781
RG82G4350MA1_uFCBGA732_MONTARA-GT
AE16
L6
VSS86
VSS179
+
0.1U_0402_10V6K
C787
C788
A17
T9
VSS87
VSS180
2
2
1@47U_1210_6.3V4Z
100U_D_16VM
D17
AJ26
VSS88
VSS181
2
2
2
2
2