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VLSI LAB MANUAL

Study of synthesis tools


Expt.No.1

Aim:
To study the tools available in xilinx software manuals

Design entry manuals:

Beginning

Verilog was invented by Phil Moorby and Prabhu Goel during the winter of
1983/1984 at Automated Integrated Design Systems (later renamed to Gateway
Design Automation) in 1985 as a hardware modeling language. Gateway Design
Automation was later purchased by Cadence Design Systems in 1990. Cadence now
has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic
simulators.

Verilog-95

With the increasing success of VHDL at the time, Cadence decided to make the
language available for open standardization. Cadence transferred Verilog into the
public domain under the Open Verilog International (OVI) (now known as Accellera)
organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-
1995, commonly referred to as Verilog-95.
Verilog 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that
users had found in the original Verilog standard. These extensions became IEEE
Standard 1364-2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support


for (2's complement) signed nets and variables. Previously, code authors had to
perform signed-operations using awkward bit-level manipulations (for example, the
carry-out bit of a simple 8-bit addition required an explicit description of the boolean-
algebra to determine its correct value.) The same function under Verilog-2001 can be
more succinctly described by one of the built-in operators: +, -, /, *, >>>. A
generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows
Verilog-2001 to control instance and statement instantiation through normal decision-
operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an
array of instances, with control over the connectivity of the individual instances. File
I/O has been improved by several new system-tasks. And finally, a few syntax
additions were introduced to improve code-readability (eg. always @*, named-
parameter override, C-style function/task/module header declaration.)

Verilog-2001 is the dominant flavor of Verilog supported by the majority of


commercial EDA software packages.

Verilog 2005

Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005)


consists of minor corrections, spec clarifications, and a few new language features
(such as the uwire keyword.)

A separate part of the Verilog standard , Verilog-AMS, attempts to integrate analog


and mixed signal modelling with traditional Verilog.

SystemVerilog

Main article: SystemVerilog

Systemverilog is a superset of Verilog-2005, with many new features and capabilities


to aid design-verification and design-modeling.

The advent of High Level Verification languages such as OpenVera, and Verisity's E
language encouraged the development of Superlog by Co-Design Automation Inc.
Co-Design Automation Inc was later purchased by Synopsys. The foundations of
Superlog and Vera were donated to Accellera, which later became the IEEE standard
P1800-2005: SystemVerilog.

Result:
Thus, the tools which is used for synthesis and simulation was studied.
HALF ADDER

Exp.No.2

Aim:
To write a HDL code for the half adder using Verilog

Algorithm:

1. start the program


2. create a verilog module for half adder
3. give inputs A and B to XOR gate to generate sum
4. give inputs A and B to AND gate to generate carry
5. end of the program

PROGRAM:
Module ha (a,b,s,c);
Input a;
Input b;
Output s;
Output c;
XOR x1(s,a,b);
And x2(c,a,b);
End module;

Result:
Thus the HDLcode for half adder was implemented and verified.
FULL ADDER

Exp.No.3

Aim:
To write a HDL code for full adder using verilog

Algorithm:

1. start the program


2. initialize two half adders inside the full adder module
3. give the carry of two half adders to OR gate to generate carry full adder
4. end of the program

PROGRAM:

Module fa(a,b,d,s2,carry);
Input a,b,d;
Output s2,carry;
Wire s1,c1,c2;
Ha ha1(a,b,s1,c1);
Ha ha2(s1,d,s2,c2);
Or g1(carry,c1,c2);
End module;

Result:
Thus the HDL code for full adder was implemented and verified.
4-BIT FULL ADDER

Expt.No.4
AIM:
To write a HDL code for 4-bit full adder using verilog

Algorithm:

1. start the program


2. create a 4bit full adder module
3. inislize four full adders inside the 4bit full adder module
4. end of the program

PROGRAM:

Module rcc (a,b,carry0,s2,c4);


Input[3:0] a;
Input [3:0] b;
Input carry0;
Output [3:0] s2;
Output c4;
Wire c1,c2,c3;
Fa fa1(a[0],b[0],c1,s2[0]c1);
Fa fa2(a[1],b[1],c1,s2[1],c2);
Fa fa3(a[2],b[2],c2,s2[2],c3);
Fa fa4(a[3],b[3],c3,s2[3],c4);
End module;

Result:
Thus the HDL code for 4bit full adder was implemented and verified.
EQUALITY DETECTOR

Expt.No:5

Aim:
To write a HDL code for equality detector using verilog

Algorithm:

1. start the program


2. using XNOR gate, give the inputs such that the output is 1,if both the inputs
are same.
3. the output of XNOR gates is given to the AND gate to check for equality
condition
4. end of the program.

PROGRAM:

Module eqd(a,b,y);
Input [3:0] a;
Output [3:0] b;
Output y;
Wire p,q,r,s;
XNOR x1(p,a[0],b[0]);
XNOR x2(r,a[1],b[1]);
XNOR x3(r,a[2],b[2]);
XNOR x4(s,a[3],b[3]);
AND x5(y,p,q,r,s);
End module;

Result:
Thus HDL code for equality detector was implemented and verified.
PRIORITY ENCODER

Expt.No.6

AIM:
To write a HDL code for priority encoder using verilog

Algorithm:

1. start the program


2. create the verilog module for priority encoder
3. check if two or more inputs are equal to at the same time, then the input
having highest priority will take precedence
4. end of the program

Program:

Module penc(d,x,y,v);
Input (3:0)d;
output x;
output y;
output v;
wire s,r;
not g1(s,d[2]);
or g2(x,d[3],d[2]);
and g3(r,s,d[1]);
or g4(y,v,d[3]);
or g5(v,x,d[1],d[0]);
end module

Result:
Thus HDL code for priority encoder was implemented and verified.
MAGNITUDE COMPARATOR
Ex.No.7

Aim:
To write a HDL code for magnitude comparator using verilog

Algorithm:

1. Start the program


2. Create module for the magnitude comparator.
3. Compare the inputs x and y using XNOR and AND gates to gets outputs x=y,
x<y & x>y.
4. End the program

Program:

Module mgc(x,y,a,b,c);
Input x,y;
Output a,b,c;
Wire p,q;
Not g1(p,x);
Not g2(q,y);
And g3(a,y,p);
And g4(b,x,q);
Xnor g5(c,x,y);
End module

Result:

Thus HDL code for magnitude comparator was implemented and verified.
3X8 DECODER

Expt.No.8

AIM:
To write a HDL code for 3X8 decoder using verilog

Algorithm:

1. Start the program


2. create verilog module for 3X8 decoder
3. the three inputs are decoded into eight output each representing one of the min
terms of the three input variables and ouput is generated using AND gate.
4. end of the program

Program:

Module dec(x,y,z,d);
Input x,y,z;
Output [7:0] d;
Wire p,q,r;
Not g1(p,x);
Not g2(q,y);
And g3(d[0],p,q,r);
And g4(d[1],p,q,z);
And g5(d[2],p,q,r);
And g6(d[3],p,y,z);
And g7(d[4],x,q,z);
And g8(d[5],x,q,z);
And g9(d[6],x,y,r);
And g10(d[7],x,y,z);
End module

Result:

Thus HDL code for 3X8 decoder was implemented and verified.
4X1 MULTIPLXER

Expt.No.9

AIM:
To write a HDL code for 4X1 MUX using verilog

Algorithm:

1. start the program


2. depending on combination of select lines, the corresponding input is
multiplexed
3. end of the program

Program:

Module mux( a,b,c,d,s0,s1,y);


Input a,b,c,d,s0,s1;
Output y;
Wire p,q,a1,b1,c1,d1;
Not x1(p,s0);
Not x2(q,s1);
And x3(a1,a,p,q);
And x4( b1,b,p,s1);
And x5(c1,c,s0,q);
And x6(d1,d,s0,s1);
Or x7(y,a1,b1,c1,d1);
End module;

Result:

Thus the HDL code for multiplexer was implemented and verified.
D-FLIP FLOP

Expt.No.10

AIM:

To write a HDL code for D-flip flop using verilog

Algorithm:

1. start the program


2. always at negative edge of clock and reset=1 output q=0 else the output given
obtained as output
3. end of the program

Program:

module flop (clk, d, q);


input clk, d;
output q;
reg q;

always @(posedge clk)


begin
q <= d;
end
End module

Result:
Thus HDL code for d-Flip flop was implemented and verified.
T-FLIP FLOP

Expt.No.11

AIM:
To write a HDL code for T-flip flop using verilog.

Algorithm:

1. Start the program


2. create verilog module for T-flip flo[p
3. instantiate the D-flip flop inside T-flip flop module
4. using not gate, output of D-flip flop is inverted
5. end of the program

Program:

Module tff(q,clk,rst);
Output q;
Input clk,rest;
Wire d;
Dff dff0(q,d,clk,rst);
Not n1(d,q);
End module

Result

Thus the HDL code for T-flip flop was implemented and verified.
4-BIT SHIFT REGISTER

Expt.No.12

AIM:

To write a HDL code for 4-bit shift register using verilog

Algorithm:

1. start the program


2. instantiate the D-flip flop in 4-bit shift register module
3. Provide a common clock for all four D-flip flop in order to get required
output.

Program:
module flop (clk, d, ce, pre, q);
input clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(posedge clk or posedge pre)
begin
if (pre)
q <= 4’b1111;
else if (ce)
q <= d;
end
end module

Result:
Thus HDL code for shift register was implemented and verified.
JK-FLIP FLOP

Expt.No.13

AIM:
To write a HDL code for JK flip flop using verilog.

Algorithm:

1. Start the program


2. instantiate D-flip flop in JK flip flop using verilog
3. using assign statement, perform the JK characteristics equation
4. end of the program

Program:

Module jkff (j,k,clk,rst,q);


Input j,k,clk,rst;
Output q;
Wire jk;
Assign jk=(j&~q)|(~k&q);
Diff diff(q,j,k,clk,rst,q);
Emd module

Result:

Thus the HDL code for JK flip flop using D-flip flop was implemented and verified.
SEQUENCE DETECTOR

Expt.No.14

AIM:
To write a HDL code for sequence detector using verilog

Algorithm:

1. Start the program


2. Create a verilog module for a sequence detects the sequence 1101.
3. define state transition when input is either 1 or 0. if rst is low, the number of
times sequence occurs is detected, else state is assigned as 0.
4. end of the program.

Program:

Module reg 1101(in,clk,rst,out);


Input in,clk,rst;
Output out;
Reg[2:0] state;
Reg[2:0]nxt _state;
Parameter s0=3`b000;
Parameter s1=3`b001;
Parameter s2=3`b010;
Parameter s3=3`b011;
Parameter s4=3`b100;
Assign out =(state==s4);
Always @(posedge clk)
If (rst)
State<=0;
Else
State <=nxt_state;
Always @(in or state)
Case(state)
S0:nxt_state=in?s1:s0;
S1:nxt_state=in?s2:s0;
S2:nxt_state=in?s2:s3;
S3:nxt_state=in?s4:s0;
S4:nxt_state=in?s2:s0;
End case
End module

Result:

Thus HDL code for sequence detector was implemented and verified.
COUNTER
Expt.No.15

AIM:
To write a program for counter using verilog

Algorithm:
1. Start the program
2. create verilog module for counter
3. when reset is high, count is zero,when its goes high,count is incremented
4. stop the program

Program:

Module counter(clk,ce,rst,count);
Input rst,clk,ce;
Reg [3:0]count;
Output[3:0] cont;
Always @(posedge clk)
If (rst)
Count= 4`b0000;
Else
If (ce)
Count<=count+1;
Else
Count=count;
End module

Result:

Thus HDL code for counter was implemented and verified.


CLOCK DIVIDER

Expt.No.16

AIM:
To write a HDL code for clock divider using verilog.

Algorithm:

1. Start the program


2. create verilog module for clock divider
3. clock signal is generated for the posedge of every fourth clock pulse, the new
clock will be inverted
4. end of the program

Program:

module clkdiv(inclk, outclk);


input inclk;
output outclk;
reg outclk;

reg [5:0]cnt;

always @ (posedge inclk)


if (cnt == 0)
begin
outclk <= ~ outclk;
cnt <= 40;
end
else
cnt <= cnt - 1;
endmodule

Result:
Thus HDL code for clock divider was implemented and verified.