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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity dcmotor is
generic(bits : integer := 8 ); -- number of bits used for duty cycle.
-- Also determines pwm period.
port ( CLK: in STD_LOGIC; -- 4 MHz clock
RESET,DIR: in STD_LOGIC; -- dircntr
pwm : out std_logic_VECTOR(2 DOWNTO 0);
begin
-- select the appropriate lines for setting frequency
CLK_DIV: process (CLK, DIV_REG) -- clock divider
begin
if (CLK'event and CLK='1') then
DIV_REG <= DIV_REG + 1;
end if;
end process;
DDCLK<=DIV_REG(12);
---------------------------- END OF CLOCK DIVIDER
-------------------------------------------------
tick <= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
else
end if;
end if;
end process;
end dcmotor1;