ECS 401 – COMPUTER ORGANIZATION

UNIT - I

Unit-I Introduction
• Number representation DIGITAL
– Fixed and floating point number representation LOGIC
DESIGN
– IEEE standard for floating point
representation.
– Error detection and correction codes:
Hamming code.
• Digital computer
– Generation
– Computer types and classifications,
COMPUTER
– Functional units and their interconnections CONCEPTS
– Buses, bus architecture, types of buses and &C
bus arbitration. PROGRAMMING
• Register, bus and memory transfer.

Unit-II Central Processing Unit Unit-III Control Unit

• Arithmetic & Logic Operations
– Addition and subtraction of signed numbers,
look ahead carry adders.
– Multiplication: Signed operand multiplication,
Booths algorithm and array multiplier.
– Division and logic operations.
– Floating point arithmetic operation
• Processor organization
– General register organization
– Stack organization
– Addressing modes.
• Instructions
– Instruction types, formats,
– Instruction cycles and subcycles ( fetch and execute
etc),
– Micro-operations, execution of a complete instruction.
• Hardwire and microprogrammed control:
– Microprogramme sequencing,
– Wide branch addressing,
– Microinstruction with next address field, pre-fetching
microinstructions,
– Concept of horizontal and vertical microprogramming.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Unit-IV Memory Unit-V Input / Output

• Memories
– Basic concept and hierarchy, • Peripheral devices
– Semiconductor RAM memories, – I/O interface, I/O ports
– 2D & 2 1/2D memory organization.
– Rom memories. • Interrupts
– Interrupt hardware, types of interrupts and
• Cache memories: exceptions.
– Concept • Modes of data transfer
– Design issues - performance, address mapping and – Programmed I/O
replacement
– Interrupt initiated I/O
• Auxiliary memories – Direct memory access
– Magnetic disk, magnetic tape and optical disks – I/O channels and processors.
• Virtual memory • Serial communication
– Concept – Synchronous & asynchronous communication
– Implementation. – Standard communication interfaces.

Books Why Study CO

1. Mano,” Computer System Architecture”, PHI • To understand why an algorithm is infeasible, or to
2. Vravice,Hamacher & Zaky, “Computer Organization”, understand why the implementation of a feasible
TMH
3. John P Hayes, “ Computer Organization”, McGraw Hill algorithm is running too slowly.
• REFERENCE • if you want to write compilers, you must understand the
1. P Pal Chaudhry, ‘ Computer Organization & Design’, hardware environment within which the compiler will
PHI function.
2. William Stalling, “ Computer Organization”, PHI
• To design peripheral equipment or the software that
3. Patterson, Computer Organisation and Design,
Elsevier Pub. 2009 drives peripheral equipment, you must know every detail
of how a particular computer deals with its input/output
(I/O)
• To model large, complex, real-world systems

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I
Computer Organization
• Computer organization addresses issues
such as control signals (how the computer
is controlled), signaling methods, and
memory types.
• It encompasses all physical aspects of
computer systems. It helps us to answer
the question: How does a computer work?
Architecture & Organization
• Architecture is those attributes visible to the programmer
– Instruction set, number of bits used for data representation, I/O
mechanisms, addressing techniques.
– e.g. Is there a multiply instruction?
• Organization is how features are implemented.
– Refers to the operational units and their interconnections that
realize the architectural specifications
– Control signals, interfaces, memory technology.
– e.g. Is there a hardware multiply unit or is it done by repeated
addition?
© MANISH MAHAJAN
Computer Architecture
• Structure and behavior of the computer system
• Logical aspects of system implementation as seen by
the programmer.
• Computer architecture includes many elements such as
instruction sets and formats, operation codes, data
types, the number and types of registers, addressing
modes, main memory access methods, and various I/O
mechanisms.
• The architecture of a system directly affects the logical
execution of programs.
• Studying computer architecture helps us to answer the
question: How do I design a computer?
History of Computer
• First Generation (1945 - 1955)
– Programs and data located in same memory
– Assembly language was used to write programs
– Vacuum Tube Technology for performing basic
processing
– Mercury delay line memory was used
– Type writers as I/O devices
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

History of Computers History of Computer

• Second Generation (1955 – 1965)
Central Processing – Transistor replaced vacuum tubes
Unit (CPU)

Main Memory Instruction Program

Input-output
equipment – Magnetic core memories and magnetic
Control
Programs, data,
storage devices were more widely used
(Programs and
operator
data for
execution)
commands Secondary
memory,
– High level language such as FORTRAN was
Data
Data
Processing
keyboard,
printer etc. developed
– Compilers were developed
Organization of a first-generation computer – Separate I/O processors were developed
along with CPU
– IBM became major manufacturer

History of Computer A Typical Computer System

• Third Generation ( 1965-1975)
– Many transistors on a single chip (IC) enabled lower cost , faster Microprocessor Secondary Video Commu
Keyboard nication IO Devices
processors and memory elements Memory Monitor
Network
– IC memories replaced magnetic core memories M
CPU a IO
– Introduction of micro-programming , parallelism , pipelining i
Hard
expansion
n Keyboard Network slots
– Effective time sharing in operating system Disk Video
Control Control
Control Control
– Development of Cache & Virtual memory M
e
Cache m
o
• Fourth Generation (1975-1996) r
y
– Still advancement in IC technology (VLSI) that is Very Large Scale Bus Interface IO (local) Bus
Integration Unit

– Microprocessor concept - Motorola, Texas Instruments were the major Peripheral (IO) interface control unit
companies
– Parallelism, Pipelining , Cache , Virtual Memories evolved to produce
high performance
– Computing systems of today
System Bus

A typical computer system

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

What is “Computer Architecture” Organization vs. Architecture

Computer Architecture =
Instruction Set Architecture +
Machine Organization
• Architecture ≅ Specification
– Attributes visible to the programmer
– Attributes:
• Instruction set
• Number of bits representing data
• I/O mechanism
• Addressing modes used
– Has direct impact on logical program execution

Organization vs. Architecture

• Organization ≅ Implementation
– Operational units and their interconnection that
realizes the architecture
– Attributes:
• HW details
• Control signals
• I/O interfaces
• Memory technology used

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Function Functional View

• All computer functions are:
– Data processing
– Data storage
– Data movement
– Control

Operations (a) Data movement Operations (b) Storage

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Operation (c) Processing from/to storage Operation (d) Processing from storage to I/O

Structure - Top Level Structure - The CPU

Peripherals Computer CPU

Central Main Computer Arithmetic

Processing Registers and
Memory
Unit I/O Login Unit
System CPU
Computer Bus
Systems Internal CPU
Interconnection Memory Interconnection

Input Control
Output Unit
Communication
lines

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Structure - The Control Unit

The Von Neumann Model
The Input Unit provides
instructions and data to the
system, which are subsequently
stored in the Memory Unit . The
Control Unit
instructions and data are
processed by the Arithmetic and
CPU Logic Unit (ALU) under the
Sequencing
ALU Logic
direction of the Control Unit . The
Control
results are sent to the Output
Internal
Bus
Unit Unit . The ALU and control unit
Control Unit are frequently referred to
Registers Registers and collectively as the central
Decoders
processing unit (CPU)

The stored program is the most important aspect of the Von

Control
Neumann model. A program is stored in the computer’s memory along
Memory
with the data to be processed.

Level of System Design

The System Bus Model
This model partitions a
computer system into three
subunits: CPU, Memory, and
Input/Output (I/O). This
refinement of the von
Neumann model combines the
ALU and the control unit into
one functional unit, the CPU.
The input and output units are
also combined into a single
I/O unit.

Most important to the system bus model, the communications among the
components are by means of a shared pathway called the system bus , which
is made up of the data bus (which carries the information being transmitted),
the address bus (which identifies where the information is being sent), and
the control bus (which describes aspects of how the information is being
sent, and in what manner).

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Levels, abstractions and virtual

machines Levels, abstractions and virtual
machines

Application
Application
High-level language
High-level language
Assembly language
Assembly language
Operating System machine
Operating System machine
Conventional machine level
Conventional machine level
Microarchitecture
Microarchitecture
Digital Logic
Digital Logic

Levels, abstractions and virtual machines Levels, abstractions and virtual machines

Add A=2 and B=3 Application Add 2 and 3 Application C, C++, BASIC,
C:=A+B; High-level language PASCAL, Java,
etc..

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Levels, abstractions and virtual machines Levels, abstractions and virtual machines

Add 2 and 3 Application ldc num1 Add A=2 and B=3 Application
C:=A+B; ldc num2 C:=A+B;
High-level language add
High-level language Pentium MMX,
ldc num1 ldc num1 SPARC, etc…
ldc num2
add Assembly language ldc 100 ldc num2
add Assembly language
stnl 0
… system calls Operating System machine

Levels, abstractions and virtual machines Levels, abstractions and virtual machines

Add A=2 and B=3 Application Add A=2 and B=3 Application
C:=A+B; High-level language C:=A+B; High-level language
ldc num1 ldc num1
ldc num2
add Assembly language ldc num2
add Assembly language
system calls Operating System machine system calls Operating System machine
1s and 0s Conventional machine level 1s and 0s Conventional machine level
Arrays & flow Microarchitecture

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Levels, abstractions and virtual machines

REGISTER TRANSFER AND MICROOPERATIONS

• Register Transfer Language

Add A=2 and B=3 Application
• Register Transfer
C:=A+B; High-level language
ldc num1
ldc num2
Assembly language • Bus and Memory Transfers
add

system calls Operating System machine • Arithmetic Microoperations

1s and 0s Conventional machine level • Logic Microoperations
Arrays & flow Microarchitecture
• Shift Microoperations
Logic gates Digital Logic
• Arithmetic Logic Shift Unit

Register Transfer Language

SIMPLE DIGITAL SYSTEMS MICROOPERATIONS (1)

• Combinational and sequential circuits can be used to create simple digital • The operations on the data in registers are called
systems. microoperations.
• These are the low-level building blocks of a digital computer. • The functions built into registers are examples of
• Registers + Operations performed on the data stored in them = Digital Module microoperations
• Modules are interconnected with common data and control paths to form a digital – Shift
computer system – Load
• Simple digital systems are frequently characterized in terms of – Clear
– the registers they contain, and – Increment
– the operations that they perform. – …
• Typically, • The result of the operation may replace the previous binary
– What operations are performed on the data in the registers information of a register or may be transferred to another
– What information is passed between registers register.
Shift Right Operation
101101110011 010110111001

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Microoperation MICROOPERATION

An elementary operation performed (during

one clock pulse), on the information stored
in one or more registers
• Micro-operations are the basis for microprocessors. An
instruction is fetched from memory, decoded and
executed by performing a sequence of
microoperations.

Registers ALU 1 clock cycle

(R) (f)
• A microprocessor performs the micro-operations in
order to realize the instruction.
R ← f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …

Register Transfer Language Register Transfer Language

ORGANIZATION OF A DIGITAL SYSTEM ORGANIZATION OF A DIGITAL SYSTEM

• Definition of the (internal) organization of a computer
-Set of registers and their functions
-Information stored in these registers
-Can be binary, BCD, Alphanumeric characters or control info
- Microoperations set
•Set of allowable microoperations provided by the organization of the
computer
•Depend on the type of information encountered
- Control signals that initiate the sequence of microoperations
(to perform the functions)
The microoperations performed on the information stored in
registers depend on the type of data that reside in the
registers. The binary information commonly found in registers
of digital computers can be classified into three categories:
1. Numerical data such as binary numbers or binary-coded
decimal numbers used in arithmetic computations.
2. Nonnumerical data such as alphanumeric characters or other
binary-coded symbols used for special applications.
3. Instruction codes, addresses, and other control information
used to specify the data-processing requirements in the
system.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Register Transfer Language Register Transfer Language

REGISTER TRANSFER LEVEL REGISTER TRANSFER LANGUAGE

• Viewing a computer, or any digital system,
in this way is called the register transfer
level
• Rather than specifying a digital system in words, a specific notation
is used, register transfer language
• For any function of the computer, the register transfer language
can be used to describe the (sequence of) microoperations

• This is because we’re focusing on • Register transfer language

– The system’s registers – A symbolic language
– A convenient tool for describing the internal organization of digital
– The data transformations in them, and
computers
– The data transfers between them. – Can also be used to facilitate the design process of digital systems.

Arithmetic Microoperations Register Transfer Language

MICROOPERATIONS DESIGNATION OF REGISTERS

• Computer system microoperations are of four types:

• Registers are designated by capital letters,
sometimes followed by numbers (e.g., A, R13,
- Register transfer microoperations IR)
- Arithmetic microoperations • Often the names indicate function:
- Logic microoperations
– MAR - memory address register
- Shift microoperations
– PC - program counter
– IR - instruction register
MAR

• Registers and their contents can be viewed and

represented in various ways
– A register can be viewed as a single entity:

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Register Transfer Language Register Transfer

DESIGNATION OF REGISTERS REGISTER TRANSFER

• Designation of a register
- a register • Copying the contents of one register to another is a register
- portion of a register transfer
- a bit of a register
• A register transfer is indicated as

R2 ← R1
• Common ways of drawing the block diagram of a register

Register Showing individual bits

– In this case the contents of register R2 are copied (loaded) into
R1 7 6 5 4 3 2 1 0 register R1
15 0 15 8 7 0 – A simultaneous transfer of all bits from the source R1 to the
R2 PC(H) PC(L)
Numbering of bits Subfields
destination register R2, during one clock pulse
– Note that this is a non-destructive; i.e. the contents of R1 are
not altered by copying (loading) them to R2

Register Transfer Register Transfer

REGISTER TRANSFER CONTROL FUNCTIONS

• Often actions need to only occur if a certain condition is true
• A register transfer such as • This is similar to an “if” statement in a programming language
• In digital systems, this is often done via a control signal, called a
control function
R3 ← R5 – If the signal is 1, the action takes place
• This is represented as:
P: R2 ← R1
Implies that the digital system has Which means “if P = 1, then load the contents of register R1 into
register R2”, i.e., if (P = 1) then (R2 ← R1)

– the data lines from the source register (R5) to

the destination register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Register Transfer

HARDWARE IMPLEMENTATION OF CONTROLLED Simultaneous Register Transfers

TRANSFERS
Implementation of controlled transfer
P: R2 ← R1 • 1- When signal P is asserted, the contents of B are copied into
both registers A and C. Note that the order in which the
statement is written does not matter. If the transfer from B to C
was written first, the result would be the same
Block diagram Control P Load
R2 Clock
Circuit • 2 - two registers are loaded simultaneously from different
n
R1 sources.

Timing diagram t t+1

Clock

Load
Transfer occurs here

• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops

1 2

Register Transfer
Illegal Simultaneous Transfers BASIC SYMBOLS FOR REGISTER
TRANSFERS
• Example of an illegal operation, since A must be
loaded with two different values simultaneously.
Symbols Description Examples
Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)

Arrow ← Denotes transfer of information R2 ← R1

Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A ← B, B ← A

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Register Transfer Register Transfer

CONNECTING REGISTRS CONNECTING REGISTRS

There are occasions when a destination register receives
information from two sources, but evidently not at the same time.
Consider the two statements:
T1: C
A
T5 : C
B
The connection of two source registers to the same destination
register cannot be done directly, but requires a multiplexer circuit
to select between two possible paths.
For registers with four bits each, we need a quadruple 2-to-1 line
multiplex, in order to select either register A or register B. When T5
= 1, register B is selected, but when T1 = 1, register A is selected
(because T5 must be O when T1 is 1).
The multiplexer and the load input of register C are enabled every
time T1 or T5 occurs. This causes a transfer of information from the
selected source register into the destination register.

Register Transfer
Connecting Registers with Multiplexers CONNECTING REGISTRS

• In a digital system with many registers, it is impractical to have

P: A
B data and control lines to directly allow each register to be
Q: A
C loaded with the contents of every possible other registers
R: B
D
S: C
A
T: D
C • To completely connect n registers  n(n-1) lines
U: D
B • O(n2) cost
– This is not a realistic approach to use in a large digital system
The multiplexer selects one of the four registers as the source
register. Control lines for the mux are driven by external • Instead, take a different approach
circuitry. The data is made available to all registers, but only one
actually loads the data. Again, external hardware generates load • Have one centralized set of circuits for data transfer – the bus
signals for the four registers such that no more than one is • Have control circuits to select which register is the source, and
active at any given time.
which is the destination

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Bus Transfers Bus System

• The number of wires will be excessive if separate lines are used • A more efficient scheme for transferring information between
between each register and all other registers in the system ! registers in a multiple-register configuration is a common bus
system
P1 P2 P1 P2

P6 P3 P6 P3

P5 P4 P5 P4

To connect n items with direct connections, you To connect n items with bus connections, you need
need n(n-1)/2 connections. only n connections.

Bus System Bus and Memory Transfer

• A bus structure consists of a set of common lines, 4-line Common

one for each bit of register, through which binary bus
information is transferred one at a time S1
• Control signals determine which register is selected S0
4X1 4X1 4X1 4X1
by the bus during each particular transfer MUX3 MUX2 MUX1 MUX0
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

8 D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0
bus
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Register D Register C Register B Register A

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Bus transfers Tri State Bus Buffers

• The transfer of information from a bus into one of • A three-state gate is a digital circuit that exhibits three states.
many destination registers can be accomplished by Two of the states are signals equivalent to logic 1 and 0 as in a
conventional gate.
connecting the bus lines to the inputs of all
• The third state is called high impedance state
destination registers and activating the load control of
• The high impedance state behaves like an open circuit which
the particular destination register selected. means that the output is disconnected and does not have a logic
• The symbolic statement for a bus transfer may significance.
mention the bus or its presence may be implied in the
statement. When bus is included in the statement we
write:
Output Y=A if C=1
BUS
C, R1
BUS (however it is R1
C) Normal Input A
High-impedance if C=0
Control Input C

Bus and Memory Transfers: Three-State Bus Buffers cont. Connecting registers with 3-state buffers

• To construct a common bus for 4 registers of n bits each using

3-state buffers, we need n circuits with four buffers in each, as
C=1 follows:
Buffer Bus line for bit 0
A0
A B A B
B0
C0
C=0
D0
Open Circuit
A B A B
s1 0
Select s0 2x4 1
decoder 2
Enable E 3

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Bus and Memory Transfers

Connecting registers with 3-state buffers BUS TRANSFER IN RTL

• External circuitry enables at most one of the tri-state buffers to pass its
data through to the inputs of the registers. The data is made available • Depending on whether the bus is to be mentioned explicitly or
to all registers, but only one actually loads the data. The load signals not, register transfer can be indicated as either
for the four registers are exactly the same as in the previous example.
This makes sense since the registers only know that they are to read in
data from the bus. They don’t care how the data got onto the bus in the R2 ← R1
first place. or

BUS ← R1, R2 ← BUS

• In the former case the bus is implicit, but in the latter, it is
explicitly indicated

• The primary advantage of using buffers rather than multiplexers is the

reduced current load on the circuit.

Bus and Memory Transfers Bus and Memory Transfers

MEMORY (RAM) MEMORY TRANSFER

• Memory (RAM) can be thought as a sequential circuits • Collectively, the memory is viewed at the register level as a
containing some number of registers device, M.
• These registers hold the words of memory • Since it contains multiple locations, we must specify which
• Each of the r registers is indicated by an address address in memory we will be using
• These addresses range from 0 to r-1 • This is done by indexing memory references
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the following • Memory is usually accessed in computer systems by putting
– n data input lines the desired address in a special register, the Memory Address
– n data output lines data input lines Register (MAR, or AR)
– k address lines n
• When memory is accessed, the contents of the MAR get sent
– A Read control line to the memory unit’s address lines
address lines
– A Write control line k M
RAM Read
Read Memory
unit AR
unit Write
Write
n
Data out Data in
data output lines

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Bus and Memory Transfers

Memory Transfer
MEMORY READ

• Memory read : Transfer from memory • To read a value from a location in memory and load it into a
register, the register transfer language notation looks like this:
• Memory write : Transfer to memory
• Data being read or wrote is called a memory word R1 ← M[MAR]
(called M) • This causes the following to occur
• It is necessary to specify the address of M when writing – The contents of the MAR get sent to the memory address lines
/reading memory – A Read (= 1) gets sent to the memory unit
• This is done by enclosing the address in square brackets – The contents of the specified address are put on the memory’s
output data lines
following the letter M – These get sent over the bus to be loaded into register R1
• Example: M[0016] : the memory contents at address
0x0016

Bus and Memory Transfers

MEMORY WRITE Memory Transfer

• To write a value from a register to a location in memory looks

like this in register transfer language:
AR
x0C 19
x12 x0E 34
M[MAR] ← R1 x10 45
R1
• This causes the following to occur 100 x12 66
– The contents of the MAR get sent to the memory address lines x14 0
– A Write (= 1) gets sent to the memory unit x16 13
– The values in register R1 get sent over the bus to the data input R1 M[AR] x18 22
lines of the memory
– The values get loaded into the specified address in the memory RAM

R1 R1
100 66

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Bus and Memory Transfers

SUMMARY OF R. TRANSFER MICROOPERATIONS Arithmetic Microoperations

A← B Transfer content of reg. B into reg. A
AR ← DR(AD) Transfer content of AD portion of reg. DR into reg. AR
• There are 4 types of microoperations:
– Register transfer microoperations transfer binarı information
A ← constant Transfer a binary constant into reg. A
from one register to another
ABUS ← R1, Transfer content of R1 into bus A and, at the same time,
– Arithmetic microoperations perform arithmetic operations on
R2 ← ABUS transfer content of bus A into R2 numeric data stored in registers
AR Address register
– Logic microoperations perform bit manipulation operations
DR Data register
M[R] Memory word specified by reg. R on non-numeric data stored in registers
M Equivalent to M[AR] – Shift microoperations perform shift operations on data stored
DR ← M Memory read operation: transfers content of in registers
memory word specified by AR into DR
M ← DR Memory write operation: transfers content of – Last three changes the data !
DR into memory word specified by AR

ARITHMETIC MICROOPERATIONS ARITHMETIC MICROOPERATIONS

• The basic arithmetic microoperations are: addition, • One’s Complement Microoperation:

subtraction, increment, decrement, and shift R2 ←R2
• Addition Microoperation: • Two’s Complement Microoperation:
R3
R1+R2 R2 ←R2+1
• Subtraction Microoperation: • Increment Microoperation:
R3 ←R1-R2 or : R2 ←R2+1
R3 ←R1+R2+1 • Decrement Microoperation:
1’s complement
R2 ←R2-1

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Example HALF ADDER/FULL ADDER

Half Adder x y c s x
0 0 0 0 c = xy s = xy’ + x’y c
=x ⊕ y y
0 1 0 1
• For R1 = 1001 1100 and R2 = 01010110, the results 1 0 0 1 s
1 1 1 0
of the operations are:
Full Adder
y y
ADD: 1111 0010 x y cn-1 cn s
0 0 0 0 0 0 0 0 1
SUBTRACT: 0100 0110 0 0 1 0 1 0 1 c 1 0 c
n-1 n-1
0 1 0 0 1
COMP: 1010 1001 0 1 1 1 0
x 1 1 x 0 1
0 1 1 0
2’S COMP: 1010 1010 1 0 0 0 1 cn s
1 0 1 1 0
SUB (2C): 0100 0110 1 1 0 1 0 cn = xy + xcn-1+ ycn-1
1 1 1 1 1 = xy + (x ⊕ y)cn-1
INCR: 1001 1101
x s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
DECR: 1001 1011 y = x ⊕ y ⊕ cn-1 = (x ⊕ y) ⊕ cn-1
S
cn-1
cn

Binary Adder Binary Adder Subtractor

• The binary adder is constructed with full-adder circuits • Operations can be combined into one common circuit by including an
connected in cascade, with the output carry from one full-adder EXOR gate with each full adder. If M=0 B⊕0=B adds, If M=1 B⊕1=B’
connected to the input carry of the next full-adder and C0=1 subtracts
• n-bit binary adder requires n full adders
B3 A3 B2 A2 B1 A1 B0 A0
M

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
Full adder Full adder Full adder Full adder C3 C2 C1 C0
Full adder Full adder Full adder Full adder

C4 S3 S2 S1 S0
C4 S3 S2 S1 S0

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

BINARY ADDER-SUBTRACTOR Binary Incrementer

• Input is the number that will be incremented

• The output carry from one half-adder is connected to one of the
• For unsigned numbers, this gives A – B if A≥B or the 2’s inputs of the next-higher-order half-adder.
complement of (B – A) if A < B • The circuit can be extended to have n bits
(example: 3 – 5 = -2= 1110)
• For signed numbers, the result is A – B provided that there is no A3 A2 A1 A0 1
overflow. (example : -3 – 5= -8)
1101
1011 + x y x y x y x y
‫ـــــــــــــــــــــــــــ‬

1000 Half Half Half Half

adder adder adder adder
C S C S C S C S

C3 1, if overflow
V= C4 S3 S2 S1 S0
C4 0, if no overflow
• Binary Incrementer can also be implemented using a
Overflow detector for signed numbers counter
• A binary decrementer can be implemented by adding
1111 to the desired register each time!

Arithmetic Microoperations

BINARY ADDER / SUBTRACTOR / INCREMENTER ARITHMETIC CIRCUIT

B3 A3 B2 A2 B1 A1 B0 A0
Binary Adder • Arithmetic operations can be implemented in one
C3 C2 C1 C0
FA FA FA FA composite arithmetic circuit
C4 S3 S2 S1 S0 • The basic component of an arithmetic circuit is the
Binary Adder-Subtractor parallel adder
B3 A3 B2 A2 B1 A1 B0 A0

M
• By controlling the data inputs of the adder, it is
possible to obtain different types of arithmetic
operations
C3 C2 C1 C0
FA FA FA FA
• This circuit performs seven distinct arithmetic
C4 S3 S2 S1 S0 operations and the basic component of it is the
Binary Incrementer A3 A2 A1 A0 1 parallel adder
x y x y x y x y
• The output of the binary adder is calculated from the
C
HA
S C
HA
S C
HA
S C
HA
S
following arithmetic sum:
• D = A + Y + Cin
C4 S3 S2 S1 S0

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Arithmetic Circuit Function Table Arithmetic Circuit

Cin
S1
S0
A0 X0 C0
S1
Select Input Output S0
FA D0
B0 0 4x1
S Ci 1 mux Y0 C1
S1 Y D=A+Y+Cin Microoperation 2
0 n 3
A1 X1 C1
0 0 0 B D=A+B Add S0
S1
FA D1
B1 0 4x1
0 0 1 B D=A+B+1 Add with carry 1 mux Y1 C2
2
Subtract with 3
0 1 0 B’ D=A+B’ A2 X2 C2
borrow
S0
S1 FA D2
0 1 1 B’ D=A+B’+1 Subtract B2 0 4x1
1 mux Y2 C3
2
1 0 0 0 D=A Transfer A 3
A3 X3 C3
1 0 1 0 D=A+1 Increment A S0
S1
FA D3
1 1 0 1 D=A-1 Decrement A B3 0 4x1
1 mux Y3 C4
0 2
1 1 1 1 D=A Transfer A 3 C out

Logic Microoperations

Logic Microoperations LOGIC MICROOPERATIONS

• Specify binary operations on the strings of bits in registers
– Logic microoperations are bit-wise operations, i.e., they work on the
• These operations consider each bit separately and individual bits of data
treat them as binary variables – useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value
• Example: Exclusive or • There are, in principle, 16 different logic functions that can be defined
P: R1
R1 ⊕ R2 over two binary input variables
• Special symbols will be adopted for the logic A B F0 F1 F2 … F13 F14 F15
microoperations OR, AND and COMPLEMENT, to 0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
distinguish them from the corresponding symbols to 1 0 0 0 1 … 0 1 1
express boolean functions 1 1 0 1 0 … 1 0 1
V is used for OR • However, most systems only implement four of these
Λ is used for AND – AND (∧), OR (∨), XOR (⊕), Complement/NOT
• The others can be created from combination of these

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Example List of Logic Microoperations

BOOLEAN FUNCTION MICROOPERATION NAME
F0 = 0 F
0 Clear
F1 = xy F
AΛ B AND
• For R1 = 1001 1100 and R2 = 01010110, the results of the
F2 = xy’ F
AΛ B
operations are:
F3 = x F
A Transfer A
F4 = x’y F
A Λ B
R1 1001 1100 F5 = y F
B Transfer B
R2 0101 0110 F6 = x ⊕ y F
A⊕ B Exclusive-OR
AND: 0001 0100 F7 = x+y F
AVB OR
OR: 1101 1110 F8 = (x+y)’ F
AVB NOR
XOR: 1100 1010 F9 = (x ⊕ y)’ F
A⊕ B Exclusive-NOR
COMP: 1010 1001 F10 = y’ F
B Complement B
F11 = x+y’ F
AVB
F12 = x’ F
A Complement A
F13 = x’+y F
AVB
F14 = (xy)’ F
AΛ B NAND
F15 = 1 F
all 1’s Set to all 1’s

THE FOUR BASIC MICROOPERATIONS

THE FOUR BASIC MICROOPERATIONS cont.

OR Microoperation
AND Microoperation
• Symbol: ∨, +

• Gate: • Symbol: ∧

• Gate:
• Example: 1001102 ∨ 10101102 = 11101102
OR OR
• Example: 1001102 ∧ 10101102 = 00001102
P+Q: R1←R2+R3, R4←R5 ∨R6
ADD

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

THE FOUR BASIC MICROOPERATIONS cont. THE FOUR BASIC MICROOPERATIONS cont.

Complement (NOT) Microoperation XOR (Exclusive-OR) Microoperation

− • Symbol: ⊕
• Symbol:

• Gate:
• Gate:

• Example: 01001102 ⊕ 10101102 = 11100002

• Example: 10101102 = 01010012

OTHER LOGIC MICROOPERATIONS OTHER LOGIC MICROOPERATIONS cont.

NOR Microoperation
NAND Microoperation

• Symbols: ∧ and
−
• Symbols: ∨ and
−

• Gate:
• Gate:
• Example: 1001102 ∧ 10101102 = 11110012
• Example: 1001102 ∨ 10101102 = 00010012

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

OTHER LOGIC MICROOPERATIONS cont.

Selective Set

Set (Preset) Microoperation • Sets to 1 the bits in register A where there are
• Force all bits into 1’s by ORing them with a value in corresponding 1’s in register B
which all its bits are being assigned to logic-1 • It does not affect bit positions that have 0’s in B
• Example: 1001102 ∨ 1111112 = 1111112 • OR microoperation can be used to implement
Clear (Reset) Microoperation
• Force all bits into 0’s by ANDing them with a value in A 1010 (Register)
which all its bits are being assigned to logic-0 B 1100 (Logic operand)
• Example: 1001102 ∧ 0000002 = 0000002 --------------------
A 1110 (Result)

Selective Complement (Toggling) Selective Clear

• Complements bits in A where there are • Clears to 0 the bits in register A only where there are
corresponding 1’s in B corresponding 1’s in register B
• It does not affect bit positions that have 0’s in B • It does not affect bit positions that have 0’s in B
• EXOR microoperation can be used to implement • AND microoperation can be used to implement

A 1010 (Register) A 1010 (Register)

B 1100 (Logic operand) B 1100 (Logic operand)
-------------------- --------------------
A 0110 (Result) (A ← A ⊕ B) A 0010 (Result) (A ← A ⋅ B)

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Logic Microoperations

Mask, Insert, Clear MASK OPERATION

• In a mask operation, the bit pattern in B is used to clear certain

• Mask operation is similar to the selective-clear bits in A
operation except that the bits of A are cleared only
where there are corresponding 0’s in B (AND) 1 1 0 0 At
• Insert operation inserts a new value şnto a group of 1010 B
bits. This is done by first masking the bits then ORing 1 0 0 0 At+1 (A ← A ⋅ B)
them with the required value (OR)
• If a bit in B is set to 0, that same position in A gets set to 0,
• Clear operation compares the words in A and B and otherwise it is unchanged
produces an all 0’s result if the two numbers are
equal (EXOR)

Logic Microoperations Logic Microoperations

CLEAR OPERATION INSERT OPERATION

• An insert operation is used to introduce a specific bit pattern into

• In a clear operation, if the bits in the same position in A and B are A register, leaving the other bit positions unchanged
the same, they are cleared in A, otherwise they are set in A • This is done as
– A mask operation to clear the desired bit positions, followed
1 1 0 0 At by
1010 B – An OR operation to introduce the new bits into the desired
positions
0 1 1 0 At+1 (A ← A ⊕ B)
– Example
• Suppose you wanted to introduce 1010 into the low order four
bits of A: 1101 1000 1011 0001 A (Original)
101 1000 1011 1010 A (Desired)

• 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Logic Microoperations

Hardware Implementations APPLICATIONS OF LOGIC MICROOPERATIONS

• Logic microoperations can be used to manipulate individual bits

or a portions of a word in a register
S1 S0 Output Operation
0 0 E=AΛB AND
• Consider the data in a register A. In another register, B, is bit
0 1 E=AVB OR data that will be used to modify the contents of A
1 0 E = A⊕ B XOR
S1
1 1 E=A Complement
S2
– Selective-set A←A+B
– Selective-complement A←A⊕B
Ai
0
– Selective-clear A ← A • B’
Bi
4x1 Ei – Mask (Delete) A←A•B
1 MUX – Clear A←A⊕B
– Insert A ← (A • B) + C
2
– Compare A←A⊕B
– ...
3

SHIFT MICROOPERATIONS SHIFT MICROOPERATIONS

• Used for serial transfer of data

• Also used in conjunction with arithmetic, logic, and other data-
processing operations
• The contents of the register can be shifted to the left or to the right Serial Input r2 Serial Output
rn-1 r3 r1 r0
• As being shifted, the first flip-flop receives its binary information from
the serial input Determines Shift Right
• There are three types of shifts the “shift”
– Logical shift type
– Circular shift
Serial Output Serial Input
– Arithmetic shift rn-1 r3 r2 r1 r0
• What differentiates them is the information that goes into the serial
input Shift Left

**Note that the bit ri is the bit at position (i) of the register

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Shift Microoperations Shift Microoperations

LOGICAL SHIFT CIRCULAR SHIFT

• In a logical shift the serial input to the shift is a 0. • In a circular shift the serial input is the bit that is shifted out of the
other end of the register.

• A right logical shift operation: • A right circular shift operation:

0

• A left circular shift operation:

• A left logical shift operation:
0

• In a RTL, the following notation is used

– cil for a circular shift left
• In a Register Transfer Language, the following notation is used
– cir for a circular shift right
– shl for a logical shift left – Examples:
– shr for a logical shift right • R2 ← cir R2
– Examples: • R3 ← cil R3
• R2 ← shr R2
• R3 ← shl R3

Shift Microoperations

ARITHMETIC SHIFT ARITHMETIC SHIFT

• An arithmetic shift is meant for signed binary numbers (integer)

• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• The main distinction of an arithmetic shift is that it must keep the
sign of the number the same as it performs the multiplication or
division
• An overflow may occur in arithmetic shift-left, and
occurs when the sign bit is changed (sign reversal)
• An overflow flip-flop Vs can be used to detect an arithmetic shift-left
overflow

Vs = Rn-1 ⊕ Rn-2
• A right arithmetic shift operation:

sign
bit

Rn-1 1  overflow
• A left arithmetic shift operation: Vs =
Rn-2 0  no overflow
0
sign
bit

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Shift Microoperations

ARITHMETIC SHIFT SHIFT MICROOPERATIONS

• An left arithmetic shift operation must be checked for the overflow

• Example: Assume R1=11001110, then:
0
sign
bit
– Arithmetic shift right once : R1 = 11100111

Before the shift, if the leftmost two – Arithmetic shift right twice : R1 = 11110011
V bits differ, the shift will result in an
overflow
– Arithmetic shift left once : R1 = 10011100
– Arithmetic shift left twice : R1 = 00111000
• In a RTL, the following notation is used
– ashl for an arithmetic shift left – Logical shift right once : R1 = 01100111
– ashr for an arithmetic shift right
– Examples:
• R2 ← ashr R2 – Logical shift left once : R1 = 10011100
• R3 ← ashl R3
– Circular shift right once : R1 = 01100111
– Circular shift left once : R1 = 10011101

Shift Microoperations

HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS

ARITHMETIC LOGIC SHIFT UNIT

0 for shift right (down)

Serial Select 1 for shift left (up)
input (IR)
• Instead of having individual registers
S
0 MUX H0 performing the microoperations directly,
1
A0
computer systems employ a number of
A1 S
0 MUX H1 storage registers connected to a
A2 1

A3
common operational unit called an
S
0
1
MUX H2 Arithmetic Logic Unit (ALU)
S
MUX H3
0
1

Serial
input (IL)

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Shift Microoperations

ARITHMETIC LOGIC SHIFT UNIT

S3
S2 Ci
S1
S0

Arithmetic D i
Circuit
Select

Ci+1
0 4x1 Fi
1 MUX
2

Bi
Logic
Circuit
Ei
3
BUSES
Ai
Ai-1 shr
Ai+1 shl

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F= A+ 1 Increment A
0 0 0 1 0 F= A+ B Addition
0 0 0 1 1 F= A+ B+ 1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F=A-1 Decrement A
0 0 1 1 1 F=A TransferA
0 1 0 0 X F= A∧ B AND
0 1 0 1 X F= A∨ B OR
0 1 1 0 X F= A⊕ B XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F

Computer Buses The System Bus

– A bus is a common electrical pathway between multiple devices.
• Can be internal to the CPU to transport data to and from the ALU.
• Can be external to the CPU, to connect it to memory or to I/O
devices.
– Early PCs had a single external bus or system bus.
– Modern PCs have a special-purpose bus between the CPU and
memory and (at least) one other bus for the I/O devices.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Physical Implementations Physical Implementations (continued)

• Strip connectors on
• Parallel lines on circuit mother boards (PC104)
boards (ISA or PCI) • External cabling (USB or
• Ribbon cables (IDE) Firewire)

Buses – Structure
Buses – Common Characteristics
• Multiple devices communicating over a single set of • Serial versus parallel
wires • Around 50-100 lines although it's possible
• Only one device can talk at a time or the message to have as few as 3 or 4
is garbled • Lines can be classified into one of four
• Each line or wire of a bus can at any one time groups
contain a single binary digit. Over time, however, a – Data lines
sequence of binary digits may be transferred – Address Lines
• These lines may and often do send information in – Control Lines
parallel – Power
• A computer system may contain a number of
different buses

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

134
Buses – Structure (continued) Data Bus
• Bus lines (parallel) • Carries data
– Data – Remember that there is no difference between
– Address “data” and “instruction” at this level
– Control
– Power
• Width is a key determinant of performance
• Bus lines (serial) – 8, 16, 32, 64 bit
– Data, address, and control are sequentially sent down
single wire
– There may be additional control lines
– Power

135 136
Address bus Control Bus
• Identify the source or destination of data
• Control and timing information
• e.g. CPU needs to read an instruction – Memory read/write signal
(data) from a given location in memory – I/O read/write signal
• Bus width determines maximum memory – Transfer ACK
capacity of system – Bus Request
– e.g. 8080 has 16 bit address bus giving 64k – Bus Grant
address space – Interrupt request
– Interrupt Acknowledge
– Clock signals
– Reset

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Bus Interconnection Scheme Operation – Sending Data

• Obtain the use of the bus
• Transfer the data via the bus
• Possible acknowledgement

Operation – Requesting Data Single Bus Problems

• Obtain the use of the bus
• Transfer the data request via the bus
• Wait for other module to send data
• Possible acknowledgement
Lots of devices on one bus leads to:
• Physically long buses
– Propagation delays – Long data paths mean that co-
ordination of bus use can adversely affect
performance
– Reflections/termination problems
• Aggregate data transfer approaches bus
capacity
• Slower devices dictate the maximum bus speed

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Multiple Buses Multiple Buses – Benefits

• Most systems use multiple buses to overcome
these problems
• Requires bridge to buffer (FIFO) data due to
differences in bus speeds
• Sometimes I/O devices also contain buffering
(FIFO)
• Isolate processor-to-memory traffic from
I/O traffic
• Support wider variety of interfaces
• Processor has bus that connects as direct
interface to chip, then an expansion bus
interface interfaces it to external devices
(ISA)
• Cache (if it exists) may act as the interface
to system bus

144
Computer Buses Traditional (ISA) - (with cache)
– Some devices that attach to a bus are active
and can initiate bus transfers. They are called
masters.
– Some devices are passive and wait for
requests. They are called slaves.
– Some devices may act as slaves at some
times and masters at others.
– Memory can never be a master device.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

145 146
Elements of Bus Design
High Performance Bus

Bus Types Bus Width

Dedicated vs. Time Multiplexed
• Bus width refers to the data and address bus widths.
System performance improves with a wider data bus as
• Dedicated we can move more bytes in parallel. We increase the
– Separate data & address lines addressing capacity of the system by adding more
address lines.
• Time multiplexed
• Wider the bus the better the data transfer rate or the
– Shared lines wider the addressable memory space
– Address valid or data valid control line • The address bus determines the system memory
– Advantage - fewer lines addressing capacity. A system with n address lines can
directly address 2n memory words. In byte-addressable
– Disadvantages memories, that means 2n bytes
• More complex control
• Degradation of performance

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I
Bus Timing
• Co-ordination of events on bus
• Synchronous – a bus clock provides
synchronization of all bus operations
• Asynchronous – donot use a common bus
clock signal; instead, these buses use
handshaking to complete an operation by
using additional synchronization signals
Synchronous Bus Timing
Memory Read Operation
© MANISH MAHAJAN
Synchronous Bus Timing
• Events determined by clock signals
• Control Bus includes clock line
• A single 1-0 cycle is a bus cycle
• All devices can read clock line
• Usually sync on leading/rising edge
• Usually a single cycle for an event
• Analogy – Orchestra conductor with baton
• Usually stricter in terms of its timing
requirements
Synchronous Bus Timing
Memory Write Operation
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I
Asynchronous Timing
• Devices must have certain tolerances to
provide responses to signal stimuli
• More flexible allowing slower devices to
communicate on same bus with faster
devices.
• Performance of faster devices, however, is
limited to speed of bus
Asynchronous Timing – Read
• The master places the address and
command information on the bus.
• Then it indicates to all devices that it
has done so by activating the Master-
ready line.
• This causes all devices on the bus to
decode the address.
• The selected slave performs the
required operation and informs the
processor it has done so by activating
the Slave-ready line.
• The master waits for Slave-ready to
become asserted before it removes its
signals from the bus.
• In the case of a read operation, it also
strobes the data into its input buffer.
© MANISH MAHAJAN
Asynchronous Bus Operation
• In asynchronous buses, there is no clock signal.
Instead, they use four-way handshaking to perform a
bus transaction. This handshaking is facilitated by two
synchronization signals: master synchronization
(MSYN) and slave synchronization (SSYN). We can
summarize the operation as follows:
1. Typically, the master places all the required data to initiate a
bus transaction and asserts the master synchronization signal
MSYN.
2. Asserting MSYN indicates that the slave can receive the data
and initiate the necessary actions on its part. When the slave is
ready with its reply, it asserts SSYN.
3. The master receives the reply and then removes the MSYN
signal to indicate receipt. For example, in a memory read
transaction, the CPU reads the data supplied by the memory.
4. Finally, in response to the master deasserting MSYN, the slave
removes its own synchronization signal SSYN to terminate the
bus transaction.
Asynchronous Timing – Read
• The master places the address and
command information on the bus.
• Then it indicates to all devices that it
has done so by activating the Master-
ready line.
• This causes all devices on the bus to
decode the address.
• The selected slave performs the
required operation and informs the
processor it has done so by activating
the Slave-ready line.
• The master waits for Slave-ready to
become asserted before it removes its
signals from the bus.
• In the case of a read operation, it also
strobes the data into its input buffer.
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I
Asynchronous Timing - Write
• In this case, the master places
the output data on the data
lines at the same time that it
transmits the address and
command information.
• The selected slave strobes the
data into its output buffer when
it receives the Master-ready
signal and indicates that it has
done so by setting the S1ave-
ready signal to 1.
• The remainder of the cycle is
identical to the input operation.
Bus Arbitration
– I/O chips have to become bus master to read
and write memory and to cause interrupts.
– If two or more devices want to become bus
master at the same time, a bus arbitration
mechanism is needed.
– Arbitration mechanisms can be centralized or
decentralized.
© MANISH MAHAJAN
Synchronous OR Asynchronous?
• Asynchronous buses allow more flexibility in
timing.
• In synchronous buses, all timing must be a
multiple of the bus clock. For example, if
memory requires slightly more time than the
default amount, we have to add a complete bus
cycle
• The main advantage of asynchronous buses is
that they eliminate this dependence on the bus
clock.
• However, synchronous buses are easier to
implement, as they donot use handshaking.
Static Vs Dynamic Arbitration
• In static bus arbitration, bus allocation among the masters is done in a
predetermined way. For example, we might use a roundrobin allocation that
rotates the bus among the masters. The main advantage of a static
mechanism is that it is easy to implement. However, since bus allocation
follows a predetermined pattern rather than the actual need, a master may
be given the bus even if it does not need it. This kind of allocation leads to
inefficient use of the bus.
• In dynamic bus arbitration, bus allocation is done in response to a request
from a bus master. To implement dynamic arbitration, each master should
have a bus request and grant lines. A bus master uses the bus request line
to let others know that it needs the bus to perform a bus transaction. Before
it can initiate the bus transaction, it should receive permission to use the
bus via the bus grant line. Dynamic arbitration consists of bus allocation and
release policies.
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Bus Arbitration
Centralized Vs Decentralized Arbitration

• In the centralized scheme, a central arbiter receives bus

requests from all masters. The arbiter, using the bus
allocation policy in effect, determines which bus request
should be granted. This decision is conveyed through
the bus grant lines. Once the transaction is over, the
master holding the bus would release the bus; the
release policy determines the actual release mechanism.

• In the distributed implementation, arbitration hardware is

distributed among the masters. A distributed algorithm is
used to determine the master that should get the bus.

Bus Allocation Policies Bus Release Policies

• Fixed Priority Policies • Non-Preemptive
– Each master is assigned a unique fixed priority. When multiple masters – In these policies, the current bus master voluntarily releases the bus
request the bus, the highest priority master will get to use the bus • Transaction-Based Release : A bus master holding the bus releases the
• Rotating Priority Policies bus when its current transaction is finished
– Priority of a master is not fixed. For example, priority of a master can be • Demand Based Release : the current master releases the bus only if there
a function of the time waiting to get the bus. Thus, the longer a master is a request from another bus master; otherwise, it continues to use the bus.
waits, the higher the priority Typically, this check is done at the completion of each transaction
• Fair Policies – A potential disadvantage of the non-preemptive policies is that a bus
– Does not allow starvation master may hold the bus for a longtime, depending on the transaction
– Some examples of fairness are : type. For example, long block transfers can hold the bus for extended
• All bus requests in a predefined window must be satisfied before granting periods of time.
requests from the next window
• A bus request should not be pending for more than M milliseconds
• Preemptive
• Hybrid Policies
– Preemptive policies force the current master to release the bus without
– Combination of Priority and Fairness
completing its current bus transaction.
– Also called Combined Policies
– E.g. – PCI Bus

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Centralized Bus Arbitration – Daisy Chaining Daisy Chain Method

• When the central arbiter receives a bus request, it sends out a bus grant
signal to the first master in the chain.

• The bus grant signals are chained through the masters Each master can
pass the incoming bus grant signal to its neighbor in the chain if it does not
want to use the bus.

• If a master wants to use the bus, it grabs the bus grant signal and will not
pass it on to its neighbor. This master can then use the bus for its bus
transaction.

• Bus release is done by the release policy in effect.

• Daisy chaining is simple to implement and requires only three control lines
independent of the number of hosts.

• Disadvantages
– It implements a fixed priority policy
– The bus arbitration time varies and is proportional to the number of masters
– This scheme is not fault tolerant

Centralized Arbitration - Polling Polling

• In response to the bus request from one or more
devices, the controller polls them (in a predesigned
priority order) and selects the highest priority device
among them and grants the bus to it. Only one bus grant
line is shown. But, only the selected device will be
activated as bus master (i.e., accepts the bus grant). All
the other devices will ignore it.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Centralized Arbitration – Independent Independent Requests

Request
• The arbiter is connected to each master by separate bus request and grant
lines

• When a master wants the bus, it sends its request through its own bus
request line. Once the arbiter receives the bus requests from the masters, it
uses the allocation policy to determine which master should get the bus
next.

• Since the bus requests are received on separate lines, the arbiter can
implement a variety of allocation policies: a rotating priority policy, a fair
policy, or even a hybrid policy.

• It provides short, constant arbitration times and allows flexible priority

assignment so that fairness can be ensured. In addition, it provides good
fault tolerance. If a master fails, the arbiter can ignore it and continue to
serve the other masters

• This implementation is complex. The number of control signals is

proportional to the number of masters.

Decentralized Arbitration Bus Arbitration

– Decentralized bus arbitration is also possible.
• A computer could have 16 prioritized bus request
lines. When a device wants to use the bus, it
assert its request line.
• All devices monitor all request lines, so at the end
of each bus cycle, each device knows whether it
was the highest priority requester.
• This method avoids the necessity of an arbiter, but
requires more bus lines.
• Another decentralized scheme equivalent to the
daisy chain arbitration minus the arbiter is shown
on the following slide.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

173
Data Transfer Types Problem 4.1
Show the Block Diagram of the H/w that
implements the following register
transfer statement

yT2 : R2
R1 , R1
R2

Problem 4.2 Solution

The o/p of 4 registers R0, R1, R2 and R3 are connected

through 4-to-1 line multiplexers to I/p of a fifth register R5.
All the registers are 8 bit long. The required transfers are
dictated by 4 timing variables To through T3 as follows

R0
T0: R5
T1: R5

R1

R2
T2: R5
T3: R5

R3
The timing variables are mutually exclusive, I.e., only one
variable is equal to 1 at a time. Give a block diagram for the
h/w implementation of the register transfers. Include the
connections necessary from the four timing variables to the
selection I/p of the multiplexers and to the load I/p of
register R5

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Problem 4.3 Problem 4.4

• Change the bus system in shown to be able to

Represent the following conditional
control statement by two register
transfer statements with control
functions
transfer information from any register to any other
register? Specifically show the connections needed
to provide a path from the o/p of register C to the I/p
of register A
4-line Common
bus

S1
S0
4X1 4X1 4X1 4X1

If (P=1) then (R1
R2) else if (Q=1) then MUX3

3 2 1 0
MUX3
3 2 1 0
MUX3
3 2 1 0
MUX3
3 2 1 0

(R1
R3) D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

R2
P : R1

D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0

R3
P’Q : R1
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Register D Register C Register B Register A

Solution Problem 4.5

• In this question • Draw a bus system similar to that
we use S1 S0 to
select the source shown but use three state buffers and a
register (With S1
being HSB), and
decoder instead of the multiplexers.
4-line Common
use S3 S2 to bus
select among the S1
four registers S0
4X1 4X1 4X1 4X1
available (with S3 MUX3 MUX3 MUX3 MUX3
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
being the HSB).
D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Register D Register C Register B Register A

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Solution Problem 4.6

• A digital computer has a common bus system for 16

registers of 32 bit each. The bus is constructed with
multiplexers.
a) How many selection I/p are there in each multiplexer?
b) What size of multiplexers are needed?
c) How many multiplexers are there in the bus?

Solution
a) 4 Selection lines to select one of the 16 registers
b) 16 x 1 Multiplexers
c) 32 Multiplexers, one for each bit of the registers.

Problem 4.7 Solution

a) R2
M[AR]
The following transfer statements specify – This statement would transfer the contents of Memory
word that has the address specified by AR into R2
a memory. Explain the memory register.
operation in each case? b) M[AR]
R3
a) R2
M[AR] – WRITE the value in register R3 into the Memory Word
that has the address specified in AR.
b) M[AR]
R3
M[R5]
c) R5

– It will firstly READ the Memory Word specified by R5
c) R5
M[R5] and then transfer the value into the same register R5,
this is mostly used in Indirect Addressing.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Problem 4.8 Solution

Draw the block diagram for the h/w that

implements the following statement
X + YZ: AR
AR + BR
Where AR and BR are two n bit registers
and X,Y and Z are control variables.

Problem 4.9 Solution

Show the hardware to implement the

following statement

xyT0 + T1 + y’T2 : AR
AR + 1

Include the logic gates for the control

functions and a block diagram for the
binary counter with a count enable
function.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Problem 4.10 Solution

Consider the following register transfer statements for
two 4 bit registers R1 and R2
xT : R1
R1 + R2
x’T : R1
R2

Draw BD for the h/w implementation. Use BD for the the

two 4 bit registers, a 4-bit adder and a quadruple 2-
to-1 line mux that selects the I/p to R1. Show how the
control variables x and T select the I/p of the mux and
the load I/p of the register.

Problem 4.11 Solution

• Using a 4 bit counter with parallel load

and a 4 bit adder, draw a BD to
implement the following

x: R1
R1 + R2
x’y : R1
R1 + 1

Where R1 is a counter with parallel load and

R2 is a 4 bit register

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

PROBLEM 4.12 SOLUTION

B3 A3 B2 A2 B1 A1 B0 A0
M A B
For the adder subtractor ckt find the M

A 0 0111 0110
values of S3, S2, S1, S0 AND C4 for the B 0 1000 1001 C3 C2 C1 C0

given values of M, A and B

FA FA FA FA

C 1 1100 1000
C4 S3 S2 S1 S0

M A B D 1 0101 1010 4-bit adder-subtractor

0 0111 0110
A E 1 0000 0001

B 0 1000 1001 B3 A3 B2 A2 B1 A1 B0 A0

C 1 1100 1000

D 1 0101 1010
C3 C2 C1 C0
FA FA FA FA

E 1 0000 0001
C4 S3 S2 S1 S0

4-bit adder-subtractor

PROBLEM 4.13 Problem 4-14

• Design a 4-bit combinational ckt Assuming that the 4 bit arithmetic ckt is
decrementer using four full adder ckts build on an IC. Show the connections
A – 1 = A + 2’s Complement of 1 = A + 1111
among two such Ics to form an 8 bit ckt
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 D3
S0 FA
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Solution Problem 4-15

Design an arithmetic ckt with one selection var S and

two n-bit data I/p A and B. the ckt generates the
following 4 arith operations in conjunction with the I/p
carry Cin. Draw the logic diagram for the first two
stages.
S Cin = 0 Cin = 1
0 D = A + B (Add) D = A + 1 (Increment)
1 D = A – 1 (Decrement) D = A + B + 1 (Subtract)

Solution Problem 4-16

Derive a Combinational ckt that selects

and generates any of the 16 logic
functions

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Solution Problem 4-17

Draw a digital ckt that performs the 4 logic

operations of EX-OR, EX-NOR, NOR
and NAND. Use two selection var. show
the logic diag of one typical stage.

Problem 4-18 Problem 4-19

The 8-bit registers AR, BR, CR and DR initially have the values
Register A holds the value 11011001, determine the B
11110010, 11111111, 10111001 and 11101010 respectively.
operand and the logic microperation to be performed
Determine the 8-bit values in each register after the execution of
in order to change the value in A to the following microoperations.
(a) 01101101 (b) 11111101 AR
AR + BR
CR
CR Λ DR, BR
BR + 1
AR
AR – CR

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Problem 4-20 Problem 4-21

• An 8-bit register holds the value 10011100. What is the register Starting from an initial value of R=11011101, determine the
value after an arithmetic shift right? Starting from the initial no. sequence of binary values in R after a logical shift left, followed
10011100 determine the register value after an arithmetic shift by a circular shift right followed by a logical shift right and a
left, and state whether there is an overflow. circular shift left.

Problem 4-22 Problem 4-23

Serial 0 for shift right (down)
Select
input (IR) 1 for shift left (up) What is wrong with the following Microoperations
What is the value S
0 MUX
H0 1. xT: AR
AR, AR
0
1
of o/p H if I/p A A0
A1 S
H1
0 MUX
= 1001, S=1, IR A2 1

A3 2. yT: R1
R2, R1
R3
= 1 and IL = 0? S
0 MUX
1
H2

S
H3
0 MUX
1
Serial
input (IL)
3. zT: PC
AR, PC
PC + 1

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Floating-Point
• What can be represented in N bits?
FLOATING POINT –Example(8-bits)
• Unsigned
0 to 2N
0 t0 255
• 2’s Complement
- 2N-1 to 2N-1 - 1

IEEE 754 -128

• 1’s Complement:
t0 127

- 2N-1+1 to 2N-1 -1
-127 t0 127
• BCD:
0N/4 to 10 – 1
0 t0 9

Floating-Point Floating-Point

• What about? • Examples of real numbers:

– Very large numbers?
9,349,398,989,787,762,244,859,087,678
–π = 3.14159265…
– Very small number? –ε = 2.71828…
0.0000000000000000000000045691
– Rational numbers –...
2/3
– ...
• We need a system to represent numbers in which the
range of expressible numbers is independent of the
number of significant digits

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Floating Point Representation Principal of Floating Point

• In the scientific notation n = f × 10e

• 2 parts where f is called the fraction, or mantissa, or significand and e is a
positive or negative integer called the exponent.
– Signed, fixed point number  MANTISSA • The computer version of this notation is called floating point.
– Position of the decimal (or binary) point  EXPONENT • Examples
• Fixed point mantissa may be a fraction or an – 3.14 = 0.314 × 101 = 3.1410 × 100
integer. – 0.000001 = 0.1 × 10−5 = 1.0 × 10−6
– 1941 = 0.1941 × 104 = 1.941 × 103
• Example: Decimal number +6132.789 can be • The range is effectively determined by the number of digits in the
represented as Scientific Notation exponent.
Fraction Exponent • The precision is determined by the number of digits in the
+0.61322789E+04 fraction.
+0.6132789 +04
The value of the exponent indicates the actual position of – More bits for significand gives more accuracy
the decimal point. 4 positions to the right. – More bits for exponent increases range

• For Binary (–1)sign x significand x 2exponent

Modeling the Real Number System Real Numbers 7 Regions

• Floating-point numbers can be used to model the real-
number system of mathematics, although there are
some important differences. 1. -ve
4. Zero 7. +ve
Overflow
Overflow
• The real line is divided up into seven regions:
1. Large negative numbers less than −0.999 × 1099.
2. Negative numbers between −0.999 × 1099 and −0.100 × 10−99. 6. Expressible
2. Expressible +ve Numbers
3. Small negative numbers with magnitudes less than −0.100 × 10−99. -ve Numbers

4. Zero. 5. +ve
3. -ve
5. Small positive numbers with magnitudes less than 0.100 × 10−99. Underflow Underflow
6. Positive numbers between 0.100×10−99 and 0.999 × 1099.
7. Large positive numbers greater than 0.999 × 1099.

-∞ 0 ∞
+∞

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Overflow / Underflow Rounding

• Overflow regions:
– Due to finite nature of representation in computers, overflow
(Region 1&7) and Underflow (Regions 3 & 5) cannot be
expressed
• Underflow:
– Underflow errors are less serious than overflow errors
– Underflow can be approximated to zero
• It is quite possible for the result of a calculation to
be one of the other numbers, even though it is in
region 2 or 6.
– For example, +0.100 × 103 divided by 3 cannot be expressed
exactly.
• The obvious thing to do is to use the nearest number
that can be expressed.
• This process is called rounding.

Relative Error
Effects of Changes in the System
• The “space” between adjacent expressible numbers in regions 2
and 6 is not constant. • Changing the number of digits in the fraction or exponent shifts the
boundaries of regions 2 and 6 and changes the number of
expressible points in them.
• The separation between +0.998 × 1099 and +0.999×1099 is very
different than that between +0.998 × 100 and +0.999 × 100
• Increasing the number of digits in the fraction increases the
density of points and therefore improves the accuracy of
• However, when separation between a number and its successor is approximations.
expressed as a percentage of that number, there is no systematic
variation throughout region 2 or 6.
• Increasing the number of digits in the exponent increases the size
of regions 2 and 6 by shrinking regions 1, 3, 5, and 7.
• The relative error introduced by rounding is approximately the
same for small numbers as large numbers.

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Normalization Floating-Point for Binary Numbers

• A floating point number is said to be normalized if the most • Floating point:
significant digit of the mantissa is nonzero – Computer arithmetic that represents numbers in which
• For example the decimal number 350 is normalized but 00035 is binary point is not fixed
not. • Example: (1.0) x 2 -1
• Regardless of where the position of the radix point is assumed – Opposite of fixed-point notation:
to be in the mantissa, the number is normalized only if its • Example: 123.456
leftmost digit is nonzero.
• Computers support floating-point arithmetic
• Example:
• The fractional point is called the “binary point”
(2.0) x 10-9 Normalized
(0.2) x 10-8 Not-normalized
(20.0) x 10-10 Not-normalized

Binary Normalized Form Floating Point Number Representation

• Why Normalized form?
Decimal Value:
– Simplifies exchange of data
V=M*RE
– Simplifies floating-point algorithms
Where: M= Mantissa
– Increase accuracy of numbers
E= Exponent
• Format: R= Radix (10)
(1.xxxxxx) x 2yyyyy
Example (decimal):
• How can we convert to normalized form
1234.5678
– need a base that can exactly be decreased or increased
by the number of bits to be shifted
Exponent Mantissa
• Normalized numbers are generally preferable to Sign Value Sign Value
unnormalized numbers, because there is only one 0 4 0 0.12345678
normalized form, whereas there are many
unnormalized forms. ==> 0.12345678 x 10 +4

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Floating Point Number Representation Single Precision Floating Point (FP) Numbers

• Current computer systems dictate that FP numbers must fit in 32-

Example (binary): or 64-bit registers.
+ 1001.11 (= 9.75) • 32-bit or single precision FP numbers are organized as follows:
(-1)s x Fraction x 2E
Make a fractional number, counting the number of shifts:
+ .100111 ==> 4 shifts seee eeee emmm mmmm mmmm mmmm mmmm mmmm

Exponent Mantissa • where s is the sign of the number, e represents the biased
exponent (8 bits) and m represents the mantissa or significand (23
Sign Value Sign Value
bits)
0 100 0 1001111
• 32-bit values range in magnitude from 10-38 to 1038.

Or for a 16-bit number with a sign, 5-bit exponent, 10-bit mantissa:

31 30 . . . 23 22 ... 0
s exponent Significand (Mantissa/Fraction)
0 00100 1001111000

Double Precision Floating Point Numbers Biased Exponent

• 64 bit double precision floating point numbers
(Value represented in two 32-bit words) are
organized as follows:
– The MSB is the sign bit
– The next 11 bits are the exponent
– The remaining 20+32=52 bits are the significand
• The range in magnitude is from 10-308 to 10308
• The growth of significand and exponent is a
compromise between accuracy and range.
• Exponents can be both positive ad negative giving rise to a
need of sign bit in exponents.
– eg. Exponents ranging from – 50 to 49 need 2 digits for the
value and one bit for the sign.
• Biased Exponent eliminates the need for sign by adding a
positive quantity to the exponent so that it is always
positive
– Adding 50 to our example exponent makes the range as 0 to
99, value requiring 2 digits and no sign bit needed.

31 30 . . . 20 19 ... 0
s exponent Significand (Mantissa/Fraction)

Significand (Mantissa/Fraction) Continued

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

IEEE FP-754 Standard IEEE FP-754 Standard

• 1985 by William Kahan (Berkley) • Uses normalized form
– Binary point
• Found virtually in every computer since 1980 – Followed by a ‘1’ bit
• Until 1980, every computer manufacturer had their own FP format – the rest of the fraction
• Some of the format did incorrect arithmetic • Hidden bit:
• IEEE Standard permits FP data to be exchanged among different – The leading ‘1’ bit doesn’t have to be stored (assumed to be
computers present)
• Three Formats: • Fractions (Significand) are defined as
– Implied 1 bit
– Single-precision (32-bits)
– Implied binary point
– Double-precision (64-bits)
– Either 32 or 52 bits
– Extended precision (80-bits): • If all bits = ‘0’s => value = 1.0
• Used primarily in ALU to reduce round off errors • If all bits are ‘1’s => value < 2.0
• Use excess-127 (single-precision) and Excess-1023 (double-precision) code for
exponent to prevent using sign bit

IEEE FP-754 Standard IEEE FP-754 Standard

• Greatly improved portability and quality of • Biased notation
computer arithmetic – Represent the most negative exponent as 000 … 00 two
• Makes the leading 1 bit of normalized binary – IEEE 754 uses a bias of 127 for single precision
numbers implicit • Formula for biased notation
– => Numbers are expanded by 1 bit (-1)s x (1 + Fraction) x 2(Exponent – Bias)
• Numbers 24 bits long for single precision(1 implied + 23 • Examples:
fraction) – Unbiased representation:
• Numbers are 53 bits long for double-precision (1 implied + • -1 will be represented as (-1 + 127) = 126ten = 0111 1110two
52 fraction) • -0.75 ten = - 0.11two = - 1.1two x 2-1
– Zero is represented as 00 … 00two – Biased single precision representation
– Has a symbol (NaN = Not a number) for invalid • For -0.75 ten
– (-1)1 x ( 1+ .1000 0000 0000 0000 0000 000two) x 2(126-127)
operations (e.g. 0/0 or subtracting infinity from infinity)
• What will change for double precision?
• Allows programmers to postpone some tests and
decisions to a later time in the program
– All other numbers are represented using the following
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
formula: 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

(-1)s x (1 + Fraction) x 2E 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Special Numbers in IEEE Floating

IEEE FP-754 Standard
Point
• Example:
– Converting the following binary representation into
decimal floating point • An all zero number is a normalized 0
• Other numbers with biased exponent e = 0 are
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0 called denormalized
1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • Denorm numbers have a hidden bit of 0 and an
– (-1)s x (1 + Fraction) x 2(Exponent – Bias) exponent of -126; they may have leading 0s
– = (-1)1 x (1 + 0.25) x 2(129 – 127) • Numbers with biased exponent of 255 are used
– = -1 x 1.25 x 22 for ±∞ and other special values, called NaN (not
– = -1.25 x 4 a number)
– = -5.0
• For example, one NaN represents 0/0

Fig 6.16 IEEE Standard Double

Floating Point Registers
Precision Floating Point

si g n exponent f r a c t io n
s ê f1f2 . . . f52
0 1 11 12 63

• Exponent bias for normalized #s is 1023

• The denorm biased exponent of 0 corresponds to an

unbiased exponent of -1022

• Infinity and NaNs have a biased exponent of 2047

• Range increases from about 10-38≤|x|≤1038 to about 10-

308≤|x|≤10308

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Floating Point Addition and

Subtraction
• Registers :
– AC AC + BR
– AC AC - BR
• Algorithms
1. Check for zeros
2. Align the mantissas
3. Add or subtract the mantissas
4. Normalize the result

Floating-Point Addition Decimal Floating Point Add and

Subtract Examples
• Steps
1. Compare exponent Operands Alignment Normalize & round
6.144 ×102 0.06144 ×104 1.003644 ×105
2. Shift smaller number right until its exponent
+9.975 ×104 +9.975 ×104 + .0005 ×105
matches the larger number 10.03644 ×104 1.004 ×105
3. Add the significands
4. Normalize the sum Operands Alignment Normalize & round
5. Round the sum if needed 1.076 ×10-7 1.076 ×10-7 7.7300 ×10-9
-9.987 ×10-8 -0.9987 ×10-7 + .0005 ×10-9
6. Renormalize, if necessary 0.0773 ×10-7 7.730 ×10-9

© MANISH MAHAJAN
 ECS 401 – COMPUTER ORGANIZATION
UNIT - I

Floating-Point Addition
• Example: 0.5 + -0.4375
1. Binary normalized versions of the two numbers
• 0.5 = 1.000 x 2–1
• -0.4375 = -1.110 x 2–2
2. Shift the number with less exponent right until its exponent
matches the larger number
• -1.110 x 2–2 = -0.111 x 2–1
3. Add the significands
• (1.000 x 2–1) + (-0.111 x 2–1) = -0.001 x 2–1
4. Normalize the sum
• -0.001 x 2–1 = -1.000 x 2–4
• Biased exponent = (-4 + 127) = 123
5. Round the sum if needed
• Number is already fits in the given bits
6. Result in decimal
• -1.000 x 2–4 = 0.0625

© MANISH MAHAJAN