Signetics

Logic Products

FEATURES

• Provides 16 arithmetic operations: ADD, SUBTRACT, COMPARE, DOUBLE, plus 12 other arithmetic operations

• Provides all 16 logic operations of two variables: Exclusive-OR, Compare, AND, NAND, NOR, OR, plus 10 other logic operations

• Full lookahead carry for highspeed arithmetic operation on long words

DESCRIPTION

The '181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (So - S3) and the Mode Control Input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function Table lists these operations.

PIN CONFIGURATION

December 4, 1985

74181, L5181, 5181 Arithmetic Logic Units

4-Blt Arithmetic Logic Unit Product Specification

TYPE TYPICAL PROPAGATION TYPICAL SUPPLY CURRENT
DELAY (TOTAL)
74181 22ns 91mA
74LS181 22ns 21mA
74S181 llns 120mA ORDERING CODE

PACKAGES

COMMERCIAL RANGE

Vce = SV ±S%; TA = DOC to +7DoC

Plastic DIP

N74181N. N74LS181N, N74S181N

NOTE:

For information regarding devices processed to Military Specifications, see the Signetics Military Products Data Manual.

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74 74S 74LS
Mode Input lui lSul 1 LSul
A or B Inputs 3ul 3Sul 3LSui
S Inputs 4ul 4Sul 4LSui
Carry Input Sui SSul SLSul
Fa - F3. = B. Cn + 4 Outputs 10ul 10Sul 10LSui
G Output 10ul 10Sul 40LSui
P Output 10ul 10Sul 20LSui NOTE:

Where a 74 unit load (ul) is understood to be 401lA I'H and -1.6mA I,L, a 745 unit load (Sui) is 501lA I'H and -2.0mA I,L, and 74LS unit load (LSul) is 201lA I'H and -0.4mA I,L.

LOGIC SYMBOL

LOGIC SYMBOL (IEEE/IEC)

2 1 2322 2120 "'8

"

I.

" IS

10 11 13

Vee "" Pin 24 GNO = Pin 12

5-350

8S3-0S40 81S02

Signetics Logic Products

Product Specification

Arithmetic Logic Units

74181, L5181, 5181

When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control Input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4- bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and ~ (Carry Generate). P and ~ are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (Cn + 4) Signal to the Carry input (Cn) of the next unit. For high-speed operation the device is used in conjunction with the

LOGIC DIAGRAM

'182 carry lookahead circuit. One carry lookahead package is required for each group of four '181 devices. Carry lookahead can be provided at various levels and offers highspeed capability over extremely long word lengths.

The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over 4 bits when the unit is in the subtract mode. The A = B output is open collector and can be wired-AND with other A = B outputs to give a comparison for more than 4 bits. The A = B signal can also be used with the Cn + 4 signal to indicate A > B and A < B.

The Function Table lists the arithmetic operations that are performed without a carry in. An

incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied.

Because subtraction is actually performed by complementary addition (1 s complement), a carry out means borrow; thus, a carry is generated when there is no underflow and no carry is generated when there is underflow.

As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol.

c. M Ao

(7) (a) (2)

10 (1)

(15) (18)

; Cn+4

(17) ii

I

Vex; .. Pin 24 GND .. Pin 12

() .. Pin Numbers

December 4, 1985

5-351

Signetics Logic Products

Product Specification

Arithmetic logic Units

74181, l5181, 5181

MODE SELECT - FUNCTION TABLE

MODE SELECT INPUTS ACTIVE HIGH INPUTS
& OUTPUTS
S3 S2 s, So Logic Arithmetic"
(M=H) (M=L) (Cn=H)
L L L L A A
L L L H A+B A+B
L L H L AB A+S
L L H H Logical 0 minus 1
L H L L AS A plus AS
L H L H S (A + Bl plus AS
L H H L A.B A minus B minus 1
L H H H AS AB minus 1
H L L L A+B A plus AB
H L L H A.B A plus B
H L H L B (A + Sl plus AB
H L H H AB AB minus 1
H H L L Logical 1 A plus A'
H H L H A+S (A + B) plus A
H H H L A+B (A+ Sl plus A
H H H H A A minus 1 MODE SELECT INPUTS ACTIVE LOW INPUTS
& OUTPUTS
S3 S2 s, So Logic Arithmetic"
(M=H) (M=Ll (Cn=L)
L L L L A A minus 1
L L L H AS AB minus 1
L L H L A+B AS minus 1
L L H H Logical 1 minus 1
L H L L A+13 A plus (A+ S)
L H L H B AB plus (A + Sl
L H H L A.B A minus B minus 1
L H H H A+S A+S
H L L L AB A plus (A + B)
H L L H A.B A plus B
H L H L B AB (A + B)
H L H H A+B A+B
H H L L Logical 0 A plus A'
H H L H AS AB plus A
H H H L AB AS plus A
H H H H A A L - LOW vol18ge

H - HIGH vol18ge level

*Each bit is shifted to the next more significant position .

•• Arithmetjc operations expressed in 25 complement notation.

te

2 1 2322 21 20 11 18

,.

,. " 17

2 1 23 22 21 20 " 18

" "

"

,.

"

13

Active High Operands

Active Low Operands

December 4, 1985

5-352

Signetics Logic Products

Product Specification

Arithmetic Logic Units

74181, L5181, 5181

ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range unless otherwise noted.)

PARAMETER 74 74LS 74S UNIT
Vce Supply voltage 7.0 7.0 7.0 V
VIN Input voltage -0.5 to +5.5 -0.5 to +5.5 -0.5 to +5.5 V
liN I nput current -30 to +5 -30 to +1 -30 to +5 rnA
VOUT Voltage applied to output in HIGH output state -0.5 to +vcc -0.5 to +vcc -0.5 to +vcc V
TA Operating free-air temperature range o to 70 ·C RECOMMENDED OPERATING CONDITIONS

74 74LS 74S
PARAMETER UNIT
Min Nom Max Min Nom Max Min Nom Max
Vce Supply voltage 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 V
VIH HIGH-level input voltage 2.0 2.0 2.0 V
VIL LOW-level input voltage +0.8 +0.8 +0.8 V
11K I nput clamp current -12 -18 -18 rnA
IOH HIGH-level output current -800 -400 -1000 ji.A
IOL LOW-level output current 16 8 20 rnA
TA Operating free-air temperature 0 70 0 70 0 70 ·C I

SUM MODE TEST TABLE I

FUNCTION INPUTS: SO = 53 = 4.5V, Sl = S2 = M = OV

OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT UNDER
PARAMETER INPUT UNDER TEST TEST
Apply 4,5V Apply GND Apply 4.5V Apply GND
tpLH Ai Bi None Remaining Cn Fi
tpHL A and B
tpLH Bi Ai None Remaining Cn Fi
tpHL A and B
tpLH AI Bi None None Remaining p
tpHL A and B, Cn
tpLH Bi Ai None None Remaining p
tpHL A and B, c,
tpLH Ai None Bi Remaining Remaining G
tpHL B A, c,
tpLH Bi None Ai Remaining Remaining A, G
tpHL B Cn
tpLH Ai None Bi Remaining Remaining Cn+4
tpHL B A, c,
tpLH Bi None Ai Remaining Remaining Cn+4
tpHL B A, c,
tpLH Cn None None All All Any F
tpHL A B or Cn + 4 December 4, 1985

5-353

Signetics Logic Products

Product Specification

Arithmetic logic Units

74181, l5181, 5181

DIFF MODE TEST TABLE II

FUNCTION INPUTS: 50 = 53 = 4.5V. 51 = S2 = M = OV

OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT UNDER
PARAMETER INPUT UNDER TEST
Apply 4.SV Apply GND Apply 4.SV Apply GND TEST
tpLH Ai None Eli Remaining Remaining Fi
tpHL A El. c,
tPLH Eli Ai None Remaining Remaining Fi
IpHL A El. c,
IpLH Ai None Eli None Remaining 15
tpHL A and El. c,
tpLH Eli Ai None None Remaining 15
IpHL A and El. c,
IpLH Ai Eli None None Remaining G
tpHL A and El. c,
IpLH Eli None Ai None Remaining G
tpHL A and 13. c,
IpLH Ai None Eli Remaining Remaining A=B
tpHL A El. c,
tpLH Eli Ai None Remaining Remaining A=B
tpHL A El. c,
tpLH Ai Eli None None Remaining Cn+4
tpHL A and El. c,
tpLH Eli None Ai None Remaining Cn+4
tpHL A and El. c,
tpLH Cn None None All None Any F
IpHL A and El or Cn + 4 LOGIC MODE TEST TABLE III

INPUT UNDER OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT FUNCTION
PARAMETER TEST UNDER INPUTS
Apply 4.SV Apply GND Apply 4.SV Apply GND TEST
tpLH Ai Bi None None Remaining Fi 51 = 52 = M = 4.5V
tpHL A and El. c, 50=53=OV
tpLH Eli Ai None None Remaining Fi 51 = 52 = M = 4.5V
IpHL A and El. c, 50=53=OV December 4. 1985

5-354

Signetics Logic Products

Product Specification

Arithmetic Logic Units

74181, L5181, 5181

DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.)

74181 74LS181 745181
PARAMETER TEST CONDITIONS1 UNIT
Min Typ2 Max Min Typ2 Max Min Typ2 Max
vee= MIN,
VOH HIGH-level VIH = MIN, Any output except 2.4 3.4 2.7 3.4 2.7 3.4 V
output voltage Vil = MAX, A=B
IOH = MAX
IOl = MAX 0.2 0.4 0.35 0.5 0.5 V
All outputs
Vcc= MIN, IOl =4mA 0.25 0.4 V
LOW-level
VOL output voltage VIH = MIN, iQl=ISmA 0.47 0.7 V
Vil = MAX G output
!Ql=8mA 0.35 0.5 V
P output
VIK Input clamp Vee = MIN, II = 11K -1.5 -1.5 -1.2 V
voltage
Mode input 1.0 0.1 1.0 rnA
Input current at A or B inputs 1.0 0.3 1.0 rnA
II maximum input Vcc = MAX S inputs 1.0 0.4 1.0 rnA
voltage
Carry input 1.0 0.5 1.0 rnA
Mode input 40 jiA
A or B 120 jiA
VI = 2.4V inputs
S inputs ISO jiA
HIGH-level input Carry input 200 jiA
IIH current vee= MAX Mode input 20 50 jiA
A or B SO 150 jiA
VI =2.7V inputs
S inputs 80 200 jiA
Carry input 100 250 jiA
Mode input -1.6 -0.4 rnA
A or B -4.8 -1.2 rnA
VI = O.4V inputs
S inputs -S.4 -1.6 rnA
LOW-level input Carry input -8 -2 rnA
III current Vee = MAX Mode input -2 rnA
A or B -S rnA
VI = 0.5V inputs
S inputs -8 rnA
Carry input -10 rnA
10H HIGH-level output VIH = MIN, Vu, = MAX, VOH = 5.5V 250 100 250 jiA
current A=B only
los Short-circuit Vee = MAX Any output except -18 -57 -15 -100 -40 -100 rnA
output current3 A=B
Supply current" Note 4a 88 140 20 34 120 220 rnA
Icc Vee = MAX
(total) Note 4b 94 150 21 37 120 220 rnA I

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at Vee = 5V, TA = 25·C.

3. los is tested with VOUT = + O.5V and Vee = Vee MAX + O.5V. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

4. Icc is measured with the following conditions: a. So through 53. M, and A inputs are at 4.5V, other inputs grounded, all outputs open. b. So through 53 and M inputs are at 4.5V, other inputs grounded, all outputs open.

December 4, 1985

5-355

Signetics Logic Products

Product Specification

Arithmetic Logic Units

74181, L5181, 5181

AC ELECTRICAL CHARACTERISTICS T A = 25°C, Vee = 5.0V

74 74LS 74S
PARAMETER TEST CONDITIONS CL = 15pF CL = 15pF CL = 15pF UNIT
RL=400n RL=2kn RL=280n
Min Max Min Max Min Max
tpLH Propagation delay M = OV, Sum or Diff Mode 18 27 10.5
tpHL Cn to Cn+4 see Waveform 2 and Tables I & II 19 20 10.5 ns
tpLH Propagation delay M = OV, Sum or Diff Mode 19 26 12
tpHL Cn to F outputs see Waveform 2 and Tables I & II 18 20 12 ns
tpLH Propagation delay M = Sl = S2 = OV, So = S3 = 4.5V 19 29 12
tpHL A or B inputs to G output Sum Mode, see Waveform 2 and 19 23 12 ns
Table I
tpLH Propagation delay M = So = S3 = OV, Sl = S2 = 4.5V 25 32 15
tpHL A or B inputs to G output Diff Mode, see Waveform 3 and 25 32 15 ns
Table II
tpLH Propagation delay M = Sl = S2 = OV, So = S3 = 4.5V 19 30 12
tpHL A or B inputs to j5 output Sum Mode, see Waveform 2 and 25 30 12 ns
Table I
tpLH Propagation delay M = So = S3 = OV, Sl = S2 = 4.5V 25 30 15
tpHL A or B inputs to 15 output Diff Mode, see Waveform 3 and 25 33 15 ns
Table II
tpLH Propagation delay M = Sl = S2 = OV, So = S3 = 4.5V 42 32 16.5
tpHL Ai or Bi inputs to Fi outputs Sum Mode, see Waveform 2 and 32 20 16.5 ns
Table I
tpLH Propagation delay M = So = S3 = OV, 81 = S2 = 4.5V 48 32 20
tpHL Ai or Bi inputs to Fi outputs Diff Mode, see Waveform 3 and 34 32 22 ns
Table II
tpLH Propagation delay M = 4.5V, Logic Mode 48 33 20
tpHL Ai or Bi inputs to Fi outputs see Waveform 2 and Table III 34 38 22 ns
tpLH Propagation delay M = OV, So = S3 = 4.5V, Sl = S2 = OV 43 38 18.5
tpHL A or B inputs to Cn + 4 Sum Mode, see Waveform 1 and 41 38 18.5 ns
output Table I
tpLH Propagation delay M = OV, So = S3 = OV, s, = S2 = 4.5V 50 41 23
tpHL A or B inputs to Cn + 4 Diff Mode, see Waveform 4 and 50 41 23 ns
outputs Table II
tpLH Propagation delay M = So = S3 = OV, Sl = S2 = 4.5V 50 50 23
tpHL A or B inputs to A=B Diff Mode, see Waveform 3 and 48 62 30 ns
output Table II December 4, 1985

5-356

Signetics Logic Products

Product Specification

Arithmetic Logic Units

74181, L5181, 5181

AC WAVEFORMS

VIN_i-VM ~VM
VIN~VM f,VM
LtPHLj ~PL1 ~tPHLJ ~PLH1
VOUT ~VM F VOUT ~VM F
WF07570S WF07580S
VM - 1.5V for 74 and 745; VM - 1.3V for 74LS VM -1.5V for 74 and 745; VM -1.3V for 74LS
Waveform 1 Waveform 2
vi __jVM ~VM
VA~VM tVM
I I I I
vi _j-VM ~VM Vi~VM tVM
L'_j I-'''HI ~'PHL~ ~"lH1
VOUT ~VM F:. VOUT ~VM r:;
WAlOS20S WF08530S
VM = 1.SV for 74 and 745; VM'"' 1.3V for 74LS VM - 1.SV for 74 and 745; VM" 1.3V for 74LS
Waveform 3 Waveform 4 II

TEST CIRCUITS AND WAVEFORMS

vee

vee r - OPEN-'" I COLLECTOR I Rl I OUTPUT I I A .. B ONLY I

: j:~C :

o I I

: I

IC'

I I

":" L __ -: J

..... -----IW------.j

ov

i------Iw------i

AMP (VI

VM'" 1.3V for 74LS; VM - , .SV for en other TIL families.

Test Circuit For 74 Totem-Pole Outputs

Input Pulse Definition

DEFINITIONS

RL = Load resistor to Vee; see AC CHARACTERISTICS for value CL - Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to ZOUT

of Pulse Generators.

D - Diodes are 1 N916. 1 N3064. or equivalent.

tTLH. tTHl Values should be less than or equal to the table entries.

INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate Pulse Width tTLH tTHL
74 3.0V lMHz 500ns 7ns 7ns
74LS 3.0V lMHz 500ns 15ns 6ns
74S 3.0V 1MHz 500ns 2.5ns 2.5ns December 4. 1985

5-357