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Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
The Digital CMOS Inverter
Dynamic Characteristics
Anurup Mitra
BITS Pilani
April 2007
Charging and Discharging The Digital CMOS
Inverter
Anurup Mitra
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Capacitance Estimation The Digital CMOS
Inverter
Anurup Mitra
Several (even non-linear) capacitances contribute to the load
capacitance of the inverter. To simplify the calculation of Introduction
Anurup Mitra
Several (even non-linear) capacitances contribute to the load
capacitance of the inverter. To simplify the calculation of Introduction
Anurup Mitra
Introduction
vice versa, the nMOS and the pMOS devices (respectively) Design Perspective
Anurup Mitra
Introduction
vice versa, the nMOS and the pMOS devices (respectively) Design Perspective
Anurup Mitra
Introduction
vice versa, the nMOS and the pMOS devices (respectively) Design Perspective
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
Formal Definitions The Digital CMOS
Inverter
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
tf Fall Time : Time taken to fall from 90% to
10%
Formal Definitions The Digital CMOS
Inverter
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
tf Fall Time : Time taken to fall from 90% to
10%
trf Edge Rate : (tr + tf )/2
Formal Definitions The Digital CMOS
Inverter
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
tf Fall Time : Time taken to fall from 90% to
10%
trf Edge Rate : (tr + tf )/2
tpHL H-to-L propagation delay : Time taken to fall
from VOH to 50%
Formal Definitions The Digital CMOS
Inverter
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
tf Fall Time : Time taken to fall from 90% to
10%
trf Edge Rate : (tr + tf )/2
tpHL H-to-L propagation delay : Time taken to fall
from VOH to 50%
tpLH L-to-H propagation delay : Time taken to rise
from 50% to VOL
Formal Definitions The Digital CMOS
Inverter
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
tf Fall Time : Time taken to fall from 90% to
10%
trf Edge Rate : (tr + tf )/2
tpHL H-to-L propagation delay : Time taken to fall
from VOH to 50%
tpLH L-to-H propagation delay : Time taken to rise
from 50% to VOL
tp Propagation Delay : (tpHL + tpLH )/2
Formal Definitions The Digital CMOS
Inverter
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
tf Fall Time : Time taken to fall from 90% to
10%
trf Edge Rate : (tr + tf )/2
tpHL H-to-L propagation delay : Time taken to fall
from VOH to 50%
tpLH L-to-H propagation delay : Time taken to rise
from 50% to VOL
tp Propagation Delay : (tpHL + tpLH )/2
tcd Contamination Delay : Minimum time from the
input crossing 50% to the output crossing 50%
Graphical Depiction The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Delay Estimation... The Digital CMOS
Inverter
Anurup Mitra
inverter, we can also estimate any of the defined delays by Design Perspective
Anurup Mitra
inverter, we can also estimate any of the defined delays by Design Perspective
Anurup Mitra
Design Perspective
Z VDD
1 VdV 3 VDD 7
Req = ≈ 1 − λVDD
0.5VDD 0.5VDD ID (1 + λV ) 4 IDSAT 9
where
V2
W
IDSAT = µCox (VDD − Vt )VDSAT − DSAT
L 2
...Contd. The Digital CMOS
Inverter
Anurup Mitra
Design Perspective
Z VDD
1 VdV 3 VDD 7
Req = ≈ 1 − λVDD
0.5VDD 0.5VDD ID (1 + λV ) 4 IDSAT 9
where
V2
W
IDSAT = µCox (VDD − Vt )VDSAT − DSAT
L 2
Usually, a normalised Req is provided as a technology
parameter.
...Contd. The Digital CMOS
Inverter
Anurup Mitra
Design Perspective
Z VDD
1 VdV 3 VDD 7
Req = ≈ 1 − λVDD
0.5VDD 0.5VDD ID (1 + λV ) 4 IDSAT 9
where
V2
W
IDSAT = µCox (VDD − Vt )VDSAT − DSAT
L 2
Usually, a normalised Req is provided as a technology
parameter.
A similar technology parameter can be calculated for tr and
tf as well.
Example The Digital CMOS
Inverter
Anurup Mitra
Introduction
Calculate the propagation delay of a CMOS inverter in
Delay Estimation
0.18µm technology. The Req ’s of the nMOS and the pMOS Design Perspective
are 7 kΩ and 20 kΩ respectively. Their aspect ratios are 1
and 3 respectively and the load cap is 5fF.
Example The Digital CMOS
Inverter
Anurup Mitra
Introduction
Calculate the propagation delay of a CMOS inverter in
Delay Estimation
0.18µm technology. The Req ’s of the nMOS and the pMOS Design Perspective
are 7 kΩ and 20 kΩ respectively. Their aspect ratios are 1
and 3 respectively and the load cap is 5fF.
Anurup Mitra
Introduction
Calculate the propagation delay of a CMOS inverter in
Delay Estimation
0.18µm technology. The Req ’s of the nMOS and the pMOS Design Perspective
are 7 kΩ and 20 kΩ respectively. Their aspect ratios are 1
and 3 respectively and the load cap is 5fF.
Anurup Mitra
Introduction
Calculate the propagation delay of a CMOS inverter in
Delay Estimation
0.18µm technology. The Req ’s of the nMOS and the pMOS Design Perspective
are 7 kΩ and 20 kΩ respectively. Their aspect ratios are 1
and 3 respectively and the load cap is 5fF.
Anurup Mitra
Introduction
Anurup Mitra
Introduction
Anurup Mitra
Introduction
All the components of the inverter load cap discussed so far
Delay Estimation
can be split into two broad categories - the intrinsic load
Design Perspective
Cint (diffusion and overlap caps), and the extrinsic load Cext
(wire and connecting gate caps).
A Word on Capacitive Loading... The Digital CMOS
Inverter
Anurup Mitra
Introduction
All the components of the inverter load cap discussed so far
Delay Estimation
can be split into two broad categories - the intrinsic load
Design Perspective
Cint (diffusion and overlap caps), and the extrinsic load Cext
(wire and connecting gate caps). The propagation delay can
be expressed as
Cext
tp = 0.69Req (Cint + Cext ) = tp0 1 +
Cint
A Word on Capacitive Loading... The Digital CMOS
Inverter
Anurup Mitra
Introduction
All the components of the inverter load cap discussed so far
Delay Estimation
can be split into two broad categories - the intrinsic load
Design Perspective
Cint (diffusion and overlap caps), and the extrinsic load Cext
(wire and connecting gate caps). The propagation delay can
be expressed as
Cext
tp = 0.69Req (Cint + Cext ) = tp0 1 +
Cint
Here tp0 represents the delay of the inverter loaded only by
its intrinsic capacitance and is hence called the the intrinsic
or unloaded delay.
A Word on Capacitive Loading... The Digital CMOS
Inverter
Anurup Mitra
Introduction
All the components of the inverter load cap discussed so far
Delay Estimation
can be split into two broad categories - the intrinsic load
Design Perspective
Cint (diffusion and overlap caps), and the extrinsic load Cext
(wire and connecting gate caps). The propagation delay can
be expressed as
Cext
tp = 0.69Req (Cint + Cext ) = tp0 1 +
Cint
Here tp0 represents the delay of the inverter loaded only by
its intrinsic capacitance and is hence called the the intrinsic
or unloaded delay.
It can be empirically established that
Cint = γCg (= Cox Wn Ln + Cox Wp Lp ) and γ is a correction
factor very close to unity.
...Contd. The Digital CMOS
Inverter
Introduction
Cext f
tp = tp0 1 + = tp0 1 + Delay Estimation
γCg γ Design Perspective
...Contd. The Digital CMOS
Inverter
Introduction
Cext f
tp = tp0 1 + = tp0 1 + Delay Estimation
γCg γ Design Perspective
Introduction
Cext f
tp = tp0 1 + = tp0 1 + Delay Estimation
γCg γ Design Perspective
Introduction
Cext f
tp = tp0 1 + = tp0 1 + Delay Estimation
γCg γ Design Perspective
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Cg ,j+1 Cg ,j
= ; j = 2...N
Cg ,j Cg ,j−1
p
Cg ,j = Cg ,j−1 Cg ,j+1
The optimum size of each inverter is the geometric mean
of its neighbour’s sizes.
Stage Ratio The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
This means that each inverter has a scale-up factor of f with
Design Perspective
respect to the preceding stage, the same effective fan-out
and hence the same delay.
Stage Ratio The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
This means that each inverter has a scale-up factor of f with
Design Perspective
respect to the preceding stage, the same effective fan-out
and hence the same delay.
Denoting the CL /Cg 1 ratio by F , we have
√
N
f = F
Stage Ratio The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
This means that each inverter has a scale-up factor of f with
Design Perspective
respect to the preceding stage, the same effective fan-out
and hence the same delay.
Denoting the CL /Cg 1 ratio by F , we have
√
N
f = F
The minimum delay is achieved as
√
N
!
F
tp = Ntp0 1+
γ
Stage Ratio The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
This means that each inverter has a scale-up factor of f with
Design Perspective
respect to the preceding stage, the same effective fan-out
and hence the same delay.
Denoting the CL /Cg 1 ratio by F , we have
√
N
f = F
The minimum delay is achieved as
√
N
!
F
tp = Ntp0 1+
γ
F is called the effective fan-out and f , the stage ratio.
Optimised Number of Stages The Digital CMOS
Inverter
Anurup Mitra
√
N
!
F Introduction
tp = Ntp0 1+ Delay Estimation
γ
Design Perspective
Anurup Mitra
√
N
!
F Introduction
tp = Ntp0 1+ Delay Estimation
γ
Design Perspective
Anurup Mitra
√
N
!
F Introduction
tp = Ntp0 1+ Delay Estimation
γ
Design Perspective
Anurup Mitra
√
N
!
F Introduction
tp = Ntp0 1+ Delay Estimation
γ
Design Perspective
Anurup Mitra
√
N
!
F Introduction
tp = Ntp0 1+ Delay Estimation
γ
Design Perspective
Anurup Mitra
All expressions for delay derived so far assumes zero rise and
Introduction
fall times for the input signal. When the actual rise and fall
Delay Estimation
times are considered the delay expressions also get modified
Design Perspective
accordingly.
Rise and Fall Times of the Input The Digital CMOS
Inverter
Anurup Mitra
All expressions for delay derived so far assumes zero rise and
Introduction
fall times for the input signal. When the actual rise and fall
Delay Estimation
times are considered the delay expressions also get modified
Design Perspective
accordingly.
For a single digital stage, the following correction is often
used.
r
t 2
2 r
tpHL,actual = tpHL,step +
2
r
t 2
2 f
tpLH,actual = tpLH,step +
2
Rise and Fall Times of the Input The Digital CMOS
Inverter
Anurup Mitra
All expressions for delay derived so far assumes zero rise and
Introduction
fall times for the input signal. When the actual rise and fall
Delay Estimation
times are considered the delay expressions also get modified
Design Perspective
accordingly.
For a single digital stage, the following correction is often
used.
r
t 2
2 r
tpHL,actual = tpHL,step +
2
r
t 2
2 f
tpLH,actual = tpLH,step +
2
For an inverter chain topology, we use
tpi = tp,step
i i−1
+ ηtp,step
where η is an empirical constant around 0.25.
Something The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective