High pressure oxidation has been applied to the oxide isolation of high speed bi

polar LSI, with fully ion-implanted shallow junctions and multilevel metallizati
on. A sorter oxidation time for the thick field oxide brought about a smaller re
distribution of impurities of a buried collector, which resulted in almost 30 %
higher breakdown voltage of devices and also a smaller base-collector capacitanc
e (CTC). A propagation delay time of an ECL gate was improved approximately 10%
at low power operation due to the small CTC. A minimum delay time of 0.6 nsec/ga
te with power consumpation of 1.3 mW(0.8 pJ) was obtained. Oxidation induced def
ects were greatly influenced with high pressure oxidation temperature, and the o
ptimum temperature was found to be around 1050°C. A master/slice ECL gate array in
cluding 900 internal gates was fabricated by utilizing high pressure oxidation t
echnology. The device performance was characterized by the average propagation d
elay time of 0.9 nsec/gate(1.2 pJ) and chip power consumption of 1.5 watts.