Real-time Embedded Systems- Lecture 07

Real-time Embedded Systems

Lecture 6
Embedded Communication
Part II
Prof. Dr. Amitava Gupta

Department of Power Engineering

Jadavpur University, India

Real-time Embedded Systems- Lecture 07

Asynchronous Serial Communication

Start bit Parity bit (optional)

5 to 8 data bits 1,1.5 or 2 stop bits

The device which does this is a UART

Converts bytes to sequence of bits while Tx
Converts sequence of bits to bytes while RX
Real-time Embedded Systems- Lecture 07

UART in operation

Start bit Parity bit (optional)

5 to 8 data bits 1,1.5 or 2 stop bits

Data from Data bytes to CPU

Ext. world RX

Data to UART
Ext. world Intel 8251 Data bytes from CPU
TX
Real-time Embedded Systems- Lecture 07

UART in operation: Overrun

To avoid overrun, the speed at which the CPU reads or write must be
matched. Rx and Tx buffers are I/O addressed.

Q. What is underrun?
Rx Buffer, data is stored here first

Data from Data bytes to CPU,

Ext. world RX
CPU does this explicitly

Data to UART
Ext. world Intel 8251 Data bytes from CPU,
CPU does this explicitly
TX

Tx Buffer
Real-time Embedded Systems- Lecture 07

UART in operation: Interrupt driven I/O

Rx Buffer, data is stored here first

Data bytes to CPU,

Data from CPU does this explicitly
Ext. world RX in a ISR

Connected to a IRQ
Data to UART of 8259, Rx ,Tx, Rx+Tx
Ext. world Intel 8251
TX Data bytes from CPU,
CPU does this explicitly
in a ISR

Tx Buffer
Real-time Embedded Systems- Lecture 07

Discussion on Interrupt driven I/O

(chalk and board)