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Nirma Institute of Technology

( Approved by All India Council for Technical Education – New Delhi


and Affiliated to Gujarat University, Ahmedabad )

Gandhinagar-Sarkhej
Highway Tragad Patia,
Post-Chandlodia,
Via-Gota, Chharodi,
Ahmedabad-382481.
Ph.: (079) 3741911-15
Fax : (079) 3741917
E-mail : nitahdad1@sancharnet.in

CERTIFICATE

This is to certify that the under mentioned students of B.E. IV, Semester VIII,
(Instrumentation and Control), Nirma Institute of Technology, have been
working on the project titled ‘Autonomous and Semi-autonomous Robots for
Coordinated Task Solving (Robocon 2004)’ at Nirma Institute of Technology
under my guidance for the fulfillment of their curriculum requirement, since
December, 2003.

They have been regular, sincere and hard working to try and successfully
completed their project assignment.

Abhijit Karnik
Harsh Satyapanthi

Prof. B. B. Kadam DATE:


Project Guide and Coordinator
Robocon 2004
Nirma Institute of Technology
CERTIFICATE
NIRMA INSTITUTE OF TECHNOLOGY

AHMEDABAD

I hereby certify that the following students of B.E. IV, Semester VIII,
Instrumentation and Control have satisfactorily completed their project on

‘AUTONOMOUS AND SEMI-AUTONOMOUS ROBOTS


FOR COORDINATED TASK SOLVING
(ROBOCON 2004)’
at
NIRMA INSTITUTE OF TECHNOLOGY

SR. NO. NAME ROLL NO.

1 ABHIJIT KARNIK 00IC28

2 HARSH SATYAPANTHI 00IC44

(Mr. Vaibhav Gandhi) (Dr. M.D. Desai)


INTERNAL GUIDE HEAD OF THE ELECTRICAL
ENGINEERING DEPARTMENT

DATE:
Project Report
8th Sem. I.C.

ACKNOWLEDGEMENT:

As students of the final year of engineering (Instrumentation & Control), we are


required to undertake a project as a part of our curriculum. Our project for 8th Semester is
titled “AUTONOMOUS AND SEMI-AUTONOMOUS ROBOTS FOR
COORDINATED TASK SOLVING”. Herewith is encapsulated a report of the same.
In our attempt, we have come to realize that robotics is a field which is not just an
isolated field on its own. It is the synthesis of a number of concepts from all the major
engineering fields. Hence our journey has had a number of guides, each one from a
different field. In submitting this report, we, the undersigned, would like to take the
opportunity to thank all these people, without whose help our modest endeavor would
never have seen the light of the day.
Thereby we take immense pleasure in thanking Prof. B. B. Kadam (Prof.
Electrical Dept.) who is our guide, Dr. M.D. Desai (HOD, Electrical Dept.), Mr. Vaibhav
Gandhi (Lecturer, IC Dept., & Internal Guide), Prof. D. M. Adhyaru (Asst. Prof., IC
Dept.), Ms. Gauri Mudaliar (Lecturer, Mechanical Dept.), Mr. Chintan Bhatt (Lecturer,
IC Dept.), Mr. Sachin Gajjar (Lecturer, EC Dept.), Mr. Dishang Trivedi (Lecturer,
Electrical Dept.), Mr. H.K. Patel (Lecturer, IC Dept.), Mr. Navinbhai Shah (Applications
Engineers).
We would also like to acknowledge the enthusiastic support that was given to us
by the management of college and faculty of I.C. Dept., who not only gave us moral
support but were actively interested in our project through all its ups and downs.
Last but not the least; we would like to acknowledge the unquestioning and
tireless support from our families.

Abhijit Karnik
Harsh Satyapanthi

Nirma Institute of Technology


Project Report
8th Sem. I.C.

FOREWORD:

The word robot was coined by the Czech writer Kapek in his play ‘Rossum's

Universal Robots’. Since then countless devices have been created and have been

associated with the word ‘Robot’. The works of Isaac Asimov have laid the foundation of

sociology pertaining to the use of robots instead of humans and the word ‘Robotics’ was

also coined by him. In today’s world, work on robots, that resemble and look almost

human, and others which don’t resemble humans in any way, progresses in leaps and

bounds. The world has forerunners in this technology like MIT, CMU, Sony, Honda etc.

In this world of ASIMO, AIBO, Packbot etc., we have made an attempt to create

machines which we dare call ‘Robots’.

In this era where organizations like ABU – Asia Pacific Broadcasting Union are

organizing robot contests like Robocon we have made an attempt to make robotic

systems which could send and receive communication signal amongst them and complete

the task assigned to them with coordinated efforts. Today when technology is developing

faster then a blink of an eye and the competition is tough to win at any stage may it be

national or international, we have put in tireless efforts to implement the technology in

simpler and effective form to compete against some of the best in field of robotics in the

country.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

INTRODUCTION:

This report is the documentation of all the efforts put into the making of
Autonomous and Semi-autonomous Robots by us as the Participating Team Members of
Robocon 2004 Team of Nirma Institute of Technology. The title of the project was
coined as:
‘Autonomous and Semi-autonomous Robots for Coordinated Task Solving’,
These robots are targeted to perform a coordinated task in the Game Arena of
Robocon ’04 where the task to be performed is common for all the participant teams from
all the institutions and nations. This report explains the technology and heuristics
involved in making of the robots and how the task is planned to be completed using the
same.

The report is divided into 6 sections. Each section deals with the project from a
different viewpoint. The first section deals with the explanation of the Contest Theme of
Robocon 2004 and pertaining details. The second section deals with the purpose of the
robots and the features included in the robots. The third section deals with the operational
description of the different modules of the robot which thereby allow the proper
functioning of the features that we have planned to implement on the robot. The fourth
section is the hardware and software section wherein the mind and the nerve control of
the robot is explained. The fifth section explains how the research and development as
well as heuristics and ideas have played a major role in shaping up this project. The last
section is the annexure containing the selected sections of the datasheets of the electronic
components used in our project, bibliography and the information about the sources of
the systems components.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

SECTION 1

ABU – Asia Pacific Robot Contest


Robocon 2004 Seoul

The ABU – Asia Pacific Broadcasting Union has been organizing the Asia Pacific
Robot Contest since 2002 which is better known as ‘Robocon’ in which the teams from
the member nations of the Asia Pacific Broadcasting Union participate.

This contest is being organized in order to create the awareness for the field of
Robotics amongst the students at undergraduate level. The undergraduate students are
encouraged to participate and finally take interest and contribute to the field of Robotics.
The contest is held first at the National level in all the participating countries. In
the national level contest the teams or undergraduate students from various colleges and
institutions participate and the winning team of the contest represents the country at the
international level.

For the contest a theme and rules are declared by the Robocon Committee and the
theme and ruler remain common for all the competitions at national levels in various
countries as well as for the international contest.

Robocon 2004 will be the third consecutive time this contest will take place.
Robocon 2004 is to be held in Seoul, Korea and the Theme and Rules of the contest are
mentioned next.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Theme and Rules – Robocon 2004 Seoul

The aim of this robot contest is to make machines by hand from design to
construction which will be most suitable to compete in the below contest
theme and rules.

Reunion of Separated Lovers, ‘Gyeonwoo and Jiknyeo’

The theme of this contest is based on a love story in Asian legend. A couple
called ‘Gyeonwoo & Jiknyeo’ are forced to be apart from each other with the
Milky Way between them due to their laziness. Magpies and crows which
feel sorry for the couple fly up to the sky and build a bridge with their bodies
to get the couple together. It is called ‘Ojak Bridge’ (Bridge of Crow and
Magpie). The couple get together by crossing ‘Ojak Bridge’ once a year, on
July 7th by lunar calendar. It always rains on this day and we say that it is the
tears of joy from Gyeonwoo and Jiknyeo for their reunion.

The aim of this contest is to compete for accomplishing “Reunion” by


completing the unfinished bridge and carrying Golden Gift by Automatic
Machine from “Gyeonwoo Zone (Zone A)” to “Jiknyeo Zone (Zone B)”.
The duration of each match is three minutes.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

1. THE GAME FIELD

The following three pages show and explain the layout and details of
the Game Field to on which the contest takes place.

2. OBJECTS (GIFT/GOLDEN GIFT/BRIDGE)

The details pertaining to the Gift, Golden Gift and the Bridge and
Bridge parts are also mentioned in the floor plan and layout of the game
field in the following three pages.

Nirma Institute of Technology


Smaller Bridge Part (EPS)
Game Field Big Bridge Part (EPS)
3.2 0.1 kg Small Bridge Part (EPS)
Big Bridge Part (EPS)
Big Bridge Part (EPS)

Jiknyeo's Hands Manual Machine Common Zone


Jiknyeo Zone
(Zone B) 2 Point Scoring Bin

Ojak Bridge

Red Milky Way Zone

Blue Milky Way Zone

1 Point Scoring Bin


Gyeonwoo Zone
(Zone A)

Golden Gift (EPS)


2.3 0.1 kg

Gift (EPS)
0.4 0.05 kg

Red Manual Machine Start Zone Blue Manual Machine Start Zone

Red Automatic Machine Start Zone Blue Automatic Machine Start Zone

Project Title
A3
ABU Asia-Pacific Robot Contest 2004 Seoul
"Reunion of Separated Lovers, Gyeonwoo & Jiknyeo "
SCALE: SHEET 1 OF 3
Game Field (Dimension)

896.25 1000 1000 100 100

2900
40
500 100
00
14

2000

30
10
100

°
.25
14
25°
14.

100

14000
1/5
14.25°

1000
3
1000

Inner Wall
500

600

400
Outer Wall
50

1200
1200
500

Inner Wall
100
1950 50 5000
Outer Wall
14000 150

Project Title
A3
ABU Asia-Pacific Robot Contest 2004 Seoul
"Reunion of Separated Lovers, Gyeonwoo & Jiknyeo "
SCALE: SHEET 2 OF 3
Gyeonwoo Zone 10000

500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 1000
485
500

485
500

1000

1000
500

Fixed Ojak Bridge


500

500
500
5000

200

1500
500

Gift

200
500

400
500

400
Golden Gift

1500
500

1200
500

800

1200 1200
Big Bridge Part

600

400
10000

415
385

Jiknyeo Zone 20
00
0
140
Small Bridge Part

600
4 0
0

385

2 Point Scoring Bin


Smaller Bridge Part

400
1000 100
10

500

3
1 Point Scoring Bin
100

Mark for Gift Position


10 mm wide non-shiny vinyl tape
in the same color as Gyeonwoo Zone (Zone A)ABU Asia-Pacific Robot Contest 2004 Seoul
Project Title
A3
30 mm wide white guideline "Reunion of Separated Lovers, Gyeonwoo & Jiknyeo "
SCALE: SHEET 3 OF 3
Project Report
8th Sem. I.C.

3. MACHINES

Each team must design and construct either or both handmade Manual
Machine and Automatic Machine(s) to compete in the contest. There is no
restriction in the number of Automatic Machine(s) but ONLY ONE Manual
Machine is allowed to each team.

(1) Manual Machine

a. Manual Machine has to be operated via remote control using cable


connected to the Manual Machine or remote control using infrared
rays, visible rays or sound waves. Radio waves are not allowed.
Operators are not allowed to ride on the machines.
b. When operating via cable, the connecting point between the Machine
and the control box must be placed at least 1000 mm above the
ground. Also the length of the cable from the Manual Machine to the
control box must not exceed 3000 mm.
c. The team members are not allowed to operate the machines or touch
the materials placed on the game field by using cable.
d. Manual Machine or its operator cannot touch “Gyeonwoo Zone (Zone
A)’s floor and extend over into “Jiknyeo Zone (Zone B)”.
e. Manual Machine cannot touch the boundary lines or extend over the
opponent’s “Milky Way Zone”.
f. Manual Machine cannot touch its own team’s Automatic Machines.
g. Manual Machine is allowed to send a signal to an Automatic Machine
only once for communication.

(2) Automatic Machine(s)

a. Automatic Machines have to be autonomous.


b. Everything separated from an automatic machine is considered to be
another automatic machine, so it must work as an automatic machine.
c. Automatic Machines are allowed to go into any zones except for the
opponent’s “Gyeonwoo Zone (Zone A)”.
d. There is no time restriction for the start of Automatic Machines. In
other words, each Automatic Machine can be started at a different
time after a game begins.
e. Once a machine starts, the team members are not allowed to touch the
machine. But, after a team calls for a “retry” and the referee grants it,

Nirma Institute of Technology


Project Report
8th Sem. I.C.

all the team are allowed to reset and restart any Automatic Machines
from the start zone.
f. “Retry” is permitted only once per game for each team.

(3) Method of Control

a. Only one operator for each team is allowed to control Manual


Machine in the game field.
b. The Automatic Machine operators are allowed to enter the game field
only when they start the machines including a “retry”.
c. Each Automatic Machine must be started by one operation.

(4) Power Supply

a. Each team shall prepare its own power source for all its machines
during the games.
b. Voltage of the machines’ electrical power source must be below
DC24 V.
c. Power source that is considered dangerous or unsuitable by the
committee shall not be permitted.

(5) Weight

a. The total sum of weight of all machines must not exceed 50 kg.
b. The total weight includes the weight of power sources, cables, remote
controller and other parts of the machines.

(6) Size

a. The total size of Automatic Machines has to fit in the size of 1200
mm x 1200 mm x 1500 mm at the Start Zone.
b. After the game begins, Automatic Machines can be separated and the
sizes can be changed freely.
c. The Manual Machine has to fit in the size of 1200 mm x 1200 mm x
1500 mm at the Start Zone.
d. After the game begins, the size of Manual Machine can be changed
freely, but it cannot be separated.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Apart from the mentioned technical details in the report there are other
numerous facts like scoring methodology, limitations of the robots,
violations in the game, decision of winner etc. that could matter during each
game to be played for 3 minutes.

The details pertaining to the same could be obtained from the following
sources.

ü QUESTIONS REGARDING THEME AND RULES

Questions regarding theme and rules should be addressed by e-mail to the


Committee in English.

E-mail: robocon2004@kbs.co.kr

‘ABU Robocon 2004 Seoul’


http://www.abu.org.my/programme/robocon/robocon.htm
http://www.kbs.co.kr/aburobocon2004

The Contest Rules designed by KBS Technical Advisor Group -


Prof. Chong Nam Chu, Seoul National University
Prof. Dong Sam Park, University of Incheon
Dr. Young Soo Lee, Seoul National University
Mr. Min Soo Park, Seoul National University

& ABU Contest Committee

Nirma Institute of Technology


Project Report
8th Sem. I.C.

SECTION 2
PROJECT OBJECTIVES:

As the title of the project along with the game theme suggests there are in total
four robots planned to be placed into the game field in order to complete the required
task. For the proper execution of the strategy for the game the robots are require to work
in coordination and thus the robots are made capable to communicate amongst
themselves as well.

The four robots could be classified into two categories as mentioned below:

1. Semi-autonomous (Manual) Robot - 1


2. Autonomous Robots - 3

Semi-autonomous (Manual) Robot – Viswakarma:

The manual robot is actually the semi-autonomous robot mentioned in the title
which is controlled using a control box attached to the system through cables. There are
various controls in the robot and the electronic system is designed to work in full manual
mode or semi-autonomous manual mode.

Various features of the manual robot are mentioned here:

ü Locomotion Module using Parallel H-Bridge Drive


ü Scissor Mechanism for Single or Half Bridge Part Gripping
ü Lead screw Mechanism for Gripping of two stacked Bridge Parts
ü Hoist Mechanism for Gripped Bridge Parts
ü Flap Mechanism for Reference and Bridge Completion
ü Signaling Mechanism for Intra robot Communication
ü Feedback Mechanisms using Limit Switches

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Autonomous Robots:

There are three fully autonomous robots planned to operate in the automatic
machine zone. These three autonomous robots and their features are mentioned here:

Kuber – The Golden Gift Career:

This autonomous robot is designed to grip the Golden Gift placed at the center of
the automatic zone and carry it over the bridge to the Jiknyeo’s hands and accomplish the
reunion.

Various features of the robot are:

ü Line Following and Turning


ü Rotary Switch Feedback in Sweeper Mechanism
ü Vacuum Gripper Mechanism
ü Serial Interface for Program Modification
ü Status Monitoring Module using Serial Interface and LCD

Natraj – The Point Scoring Robot:

This autonomous robot is designed to gather one after another 11 gifts from
various places in the automatic zone into its helical structure and finally deploy the gifts
into the 1 point scoring bin and 2 point scoring bin in order to score points.

Various features of the robot are:

ü Line Following and Turning


ü Rotary Switch Feedback Mechanism in the Rotating Center Shaft
ü Gift Intake and Gift Delivery Mechanism

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Project Report
8th Sem. I.C.

ü Serial Interface for Program Modification


ü Status Monitoring Module using Serial Interface and LCD

Ganesh – The Multipurpose Robot:

This autonomous robot is designed to be a multipurpose robot which could be


used as a test platform for testing of various programs as well as it could also be used to
perform tasks like gift pick n place and for defense against the attack from opponent’s
automatic robots.

Various features of the robot are:

ü Line Following and Turning


ü Mechanism for Defense
ü Serial Interface for Program Modification

Nirma Institute of Technology


Project Report
8th Sem. I.C.

SECTION 3
Function Description:

Various functions of the Semi-autonomous robot are described in the following part of
the section.

Locomotion Module Using Parallel H-Bridge Drive:

This is a very specific feature incorporated in the manual robot due to the high
current requirement of the motors. The Swiss make Faulhaber Motors used for the
locomotion module of the manual robot require high current of above 3 A per motor
where the limitation of the H-Bridge IC LMD18200 comes into picture. This IC could
withstand the maximum current of 3 A. Thus two such ICs have been paralleled in order
to provide the sufficient drive current to one motor without damaging the IC or the
circuitry. In this case the control signals and the supply signals to the IC are the same and
their outputs are connected so that the motors are supplied sufficient current for full high
speed drive.

Scissor Mechanism for Single or Half Bridge Part Gripping:

As per the game theme a total of six bridge parts are required by both the teams
for the completion of the bridge of both the teams but the available full bridge parts are
only five. Thus one of the team might have to use two half bridge parts for the
completion of the bridge gap.

Scissor Mechanism is specially designed for the same. It is capable to grip a


single bridge part or two half bridge parts individually. This mechanism is controlled
using rack n pinion motors used for the automatic door locks of the cars.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Lead screw Mechanism for Gripping of two stacked Bridge Parts:

The stacks of two bridge parts at the extremes of the manual machine common
zone would be used to fill up the remaining two gaps of the bridge. These two bridge
parts would be gripped using a gripper with lead screw mechanism that uses high torque
geared motors to rotate the lead screw and grip the stacked bridge parts.

Hoist Mechanism for Gripped Bridge Parts:

For hoisting the gripped single or half bridge parts thread and pulley are used
where the thread is attached with the high torque geared motor that pulls the thread and
the scissor mechanisms are hoisted along with the bridge part or parts.

Flap Mechanism for Reference and Bridge Completion:

The rotating flaps connected to the slow speed motors are provided on the rear
side of the robot in order to have the reference from the wall so that the bridge parts are
gripped at their centers of gravity as well as while the bridge parts are filled into the
bridge gaps they could be filled properly.

Signaling Mechanism for Intra robot Communication

The manual robot equipped with a signaling device so that when it completes the
bridge, it could signal the automatic robots to continue their tasks further. For the same
the a laser signaling device is mounted onto the robot which while signaling covers a
specific range of angle in order to send the signal to the automatic robot.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Feedback Mechanisms using Limit Switches

As mentioned the manual robot is planned to be semi-autonomous as well. For the


same purpose there are various limit switches mounted onto the robot at various places
which shall detect the positions of the moving parts of the robots such as hoist
mechanism, flaps etc. The on and off signals from the switches going to the
microcontroller shall automatically decide the next operation of the robot. In this case the
manual controller shall not have to control anything apart from the drive of the robot.

Various features of the autonomous robots are further discussed in the following part of
the section.

Line Following and Turning

The autonomous robots are required to perform their respective tasks without any
manual guidance. Thus the technique used to make the robots reach the desired locations
in order to perform their tasks is the white line following, cross detection and turning
technique using the optoelectronic sensors.

These optoelectronic sensors are actually developed during the project using light
to voltage converter IC – OPT101 and LED. These sensors work on the principle of
reflective light amplification. The IC – OPT101 comprised of a photodiode and amplifier.
The light of LED reflects from the surface and falls on to the OPT101 which is amplified
by the amplifier inbuilt the IC. The intensity of the light falling onto the photodiode of IC
depends upon the color of the surface. Thus while the sensor is on the white line it gives
the saturated output voltage where as while not on the white line it gives a low voltage.
This voltage is converted into a digital signal using an analog comparator IC TLC393

Nirma Institute of Technology


Project Report
8th Sem. I.C.

where the second input to the IC is a fixed voltage. Thus when the output voltage of the
sensor is below certain level i.e. when the sensor is not on white line it gives ‘0’ as the
output whereas if the output voltage of the sensor is above certain level i.e. when the
sensor is on the white line it gives ‘1’ as the output.

Using six such sensors divided into two rows on in front and one at the rear side
the white line following is achieved. To make the robot follow the white line various
sequences of the possible states of the sensors are considered and depending upon the
same, position of the robot and correction required in the proper direction is analyzed.
Finally on the basis of the required correction, PWM signal is applied to the H-Bridge
drive circuit which uses LMD18200T IC, and the straight line is followed by the robot.
For the motion of the robot high torque Maxon Motors are used with the gearbox having
1:18 ratio of gear reduction.

While the robot follows the white line it is also required for the robot to take 90
degree turn in certain direction. For the same the cross detection is used in which the
robot counts the number of crosses in the grid it passes and when this number matches
with the number of cross where it has to turn or stop, the robot stops the straight line
motion and the by rotating both the motors in the opposite directions it takes the turn in
the desired direction till the desired sensor in the front line of the sensors come onto the
white line.

Rotary Switch Feedback Mechanism

This is a very special feature introduced in the robots in order to reduce the
weight and complexity involved in implementing the stepper motors. This mechanism is
used wherever a part of the robot is desired to be rotated only till certain position is
achieved or only by certain angle.

In this mechanism the shaft of a 12 position rotary switch is coupled with the
rotating member of the robot so that the rotary switch also turns by the angle the rotating

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8th Sem. I.C.

member of the robot rotates. During the same process the position of the rotary switch is
read by the microcontroller and as per the program whenever the rotating element of the
robot reaches the desired position the pertaining position of the rotary switch is read and
the motor is stopped immediately.

Vacuum Gripper Mechanism

Vacuum Gripper is a unique feature incorporated in the golden gift carrying


autonomous robot. In this mechanism a vacuum gripper is used to pick up the golden gift
and this vacuum gripper is actuated using a lead screw mechanism. The prerequisite for
generating vacuum and gripping the gift is that the gripper tool should be in contact with
the surface to be gripped with sufficient pressure and to generate the same another lead
screw mechanism is used which brings the gripping surface of the gripper tool and the
surface of the gift to be gripped in contact with each other with sufficient pressure
required to generate vacuum and grip the gift.

Serial Interface for Program Modification and Status Monitoring

Serial Interface between the Microcontroller and the Computer is established in


order to update the microcontroller program as well as to monitor the status of various
sensors and switches etc. on the robot. This serial communication between the
microcontroller and the computer is done using the trial version of the Procomm
Software.

Serial communication allows the operator to monitor the status of various parts of
the robot especially sensors, limit switches etc. and accordingly verify the functioning of
the robot and its electronic circuitry. This also allows the operators to update the
microcontroller program very fast without detaching it from the circuit as the time
between the two games shall be very less and the program might be required to be
changed as per the change in the strategy for the game.

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Status Monitoring using LCD

For the status monitoring purpose apart from the serial interface LCD also is used.
When the computer is not available nearby the testing area of the robot to monitor the
status of various sensors and limit switches mounted on the robots, LCD interface is used.

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8th Sem. I.C.

SECTION 4

HARDWARE
&
SOFTWARE

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SOFTWARE

The software programs for the microcontroller have been developed


using Assembly Level Programming language. Microcontroller used in the
project is DS89C420 manufactured by Dallas Semiconductor which is 8052
based microcontroller. Thus for microcontroller software programming
Evaluation Version of Assembler – 8051IDE developed by AceBus has been
used to assemble, compile and simulate the software programs.

The benefit of using DS89C420 microcontroller is that it has a 16kb


of Flash Memory for programs, 1kb of RAM and 256 bytes of SRAM and
also for loading the program into the microcontroller flash memory self
developed serial programmer could be used and the programming is fast due
to flash memory. For loading the program from the computer to the
microcontroller through serial programmer the MTK – Microcontroller Tool
Kit developed by Dallas Semiconductors has been used.

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8th Sem. I.C.

LCD Interface

The LCD interface has been developed in order to monitor the status of various
components, sensors, switches on the robot as well as for microcontroller operation. The
test software for the 16x2 Matrix Intelligent LCD interface with microcontroller is shown
here.

;CONTROL LINES
RS EQU P1.0
RW EQU P1.1
EN EQU P1.2
;DATA PORT --> P3

ORG 0000

START:
MOV SP,#80H
LCALL PORTCONFIG
LCALL READY
MOV A,#'R'
LCALL DISP
MOV A,#'O'
LCALL DISP
MOV A,#'B'
LCALL DISP
MOV A,#'O'
LCALL DISP
MOV A,#'C'
LCALL DISP
MOV A,#'O'
LCALL DISP
MOV A,#'N'

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LCALL DISP
MOV A,#' '
LCALL DISP
MOV A,#'2'
LCALL DISP
MOV A,#'0'
LCALL DISP
MOV A,#'0'
LCALL DISP
MOV A,#'4'
LCALL DISP
MOV A,#0C0H
LCALL CMND
MOV A,#'N'
LCALL DISP
MOV A,#'I'
LCALL DISP
MOV A,#'T'
LCALL DISP

PORTCONFIG: ;Configure required Ports as Input or Output


MOV P1,#00H
MOV P3,#00H
RET

READY: ;Initialize LCD to be Ready to operate


CLR RS
CLR RW
LCALL CHK
MOV A,#80H
LCALL CMND
MOV A,#01H
LCALL CMND
MOV A,#03H
LCALL CMND
MOV A,#3CH
LCALL CMND
MOV A,#3CH
LCALL CMND
MOV A,#0FH
LCALL CMND
MOV A,#06H
LCALL CMND
SETB RW
SETB RS
RET

CMND: ;Send the Command


LCALL CHK
MOV P3,#00H
MOV P3,A

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CLR RS
CLR RW
SETB EN
CLR EN
RET

DISP: ;Display Character


LCALL CHK
MOV P3,#00H
MOV P3,A
SETB RS
CLR RW
SETB EN
CLR EN
RET

CHK: ;Check the Busy Flag


CLR RS
SETB RW
MOV P3,#0FFH
CNT: CLR EN
SETB EN
JB P3.7,CNT
CLR EN
MOV P3,#00H
RET

END

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Serial Interface

The Serial Interface is found easier and more suitable for status monitoring as it
could also be used for program modification. Thus compared to LCD Serial Interface is
much more used for program modification and status monitoring purpose.

MSG DECODE1 DECODE2 DECODE3 RESPONSE


HHH H H H 'THOR
COMMUNICATIONS.
LINK OK.'
PWx PAGE WRITE NEW PAGE SET PAGESEL=NEW
ADDR
PRH PAGE READ DON'T CARE SEND CONTENTS OF
PAGESEL
XAx XRAM LOB WRITE ADDR DATA WRITE x TO
PAGESEL+W.
RXA READ XRAM LOB OF ADDRESS SEND CONTENTS OF
PAGESEL+x
SAx SRAM LOB WRITE ADDR DATA WRITE X TO SRAM
LOCATION A
RSA READ SRAM LOB OF ADDRESS SEND CONTENTS OF
SRAM LOCATION A
ANY OTHER MESSAGE 'COMMAND
SYNTAX ERROR.
TRY AGAIN'

SAMPLE COMMUNICATION:
HHH
THOR COMMUNICATIONS. LINK OK
HOI
COMMAND SYNTAX ERROR. TRY AGAIN
PW2
PRF
Xa99
Sb88
RXa9
RSb8
HHH
THOR COMMUNICATIONS. LINK OK
HYU
COMMAND SYNTAX ERROR. TRY AGAIN

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Program

;DOCUMENTATION
;REGISTERS IN USE:
;R0 FOR COUNTING AND TRANSFERRING DATA
;T1 FOR TIMING THE 9600BPS COUNT
;ADDITIONAL ADDRESSES:
;CRITICAL ADDRESSES:
;#0160H, #0161H, #0162H FOR STORING COMMAND BEFORE PROCESSING
;#0163H, #0164H FOR STORING DPTR FOR ERR AND ACK MESSAGES
;NON-CRITICAL ADDRESSES:
;PAGESEL (41H), TEMP (42H)
;NON-CRITICAL BITS:
;ERR_ON (21H), ACK_ON (22H), P_WR (23H), VBCR (24H), VBLF (25H)
;START ADDRESS: 1000H
;END ADDRESS: 11FDH

;BYTES
PAGESEL EQU 41H
TEMP EQU 42H

;BITS
ERR_ON EQU 21H
ACK_ON EQU 22H
P_WR EQU 23H
VBCR EQU 24H
VBLF EQU 25H

ORG 0000H
LJMP INIT

ORG 0023H
LJMP SER_PROC

ORG 0100H

Nirma Institute of Technology


Project Report
8th Sem. I.C.

INIT: ;MASTER INIT ALGOL


MOV SP,#80H ;MASTER INIT DIRECTIVE
;>>>
LCALL SI_INIT ;CALL TO MODULE 'SERIAL INTERFACE'
;>>>
LJMP LOOPINF ;STANDARD IDLE LOOP

ORG 0120H
LOOPINF:
NOP
SJMP LOOPINF

ORG 1001H
MSG: DB 13,10,'THOR COMMUNICATIONS. LINK OK',13,10

ORG 1031H
MSG1: DB 13,10,'COMMAND SYNTAX ERROR. TRY AGAIN',13,10

ORG 1060H
SI_INIT: ;MODULE 'SERIAL INTERFACE'
ORL 0C4H, #03H ;ENABLE SRAM, LOCATION C4H BITS 0 AND 1
MOV PAGESEL,#00H
CLR ERR_ON
CLR ACK_ON
CLR VBCR
MOV R0, #60H
LCALL SER_INIT
RET

ORG 1078H
SER_INIT:
ANL SCON, #00H
SETB SCON.6 ;SCON.7,6=01 => MODE 1
SETB SCON.4 ;SCON.4=REN =>RECEIVER ENABLED

Nirma Institute of Technology


Project Report
8th Sem. I.C.

SETB SCON.3 ;SCON.3=1 =>STOP BIT =1


MOV TH1, #0FDH ;RELOAD SETTINGS FOR 9600BPS
ANL TMOD, #0FH ;CLEAR ALL BITS OF TMOD FOR TIMER1
ORL TMOD, #20H ;SET TIMER1 TO MODE 2 AUTORELOAD
SETB TR1 ;START TIMER1
ORL IE, #90H ;SET EA=1 AND ES0=1 TO ENABLE GLOBAL AND SERIAL0
INTERRUPTS
RET

ORG 1098H
SER_PROC:
JNB RI, TXINT
CLR RI
MOV A, SBUF ;LOAD RECEIVED DATA
MOV DPTR, #0160H;SAVE TO #0100H+[R0]
MOV DPL, R0
MOVX @DPTR, A ;SAVE TO XRAM
INC R0
MOV A, R0
CJNE A, #63H, KR ;SEE IF TOTAL 3 BYTE COMMAND HAS BEEN RECVD
LCALL PROC_CMD ;IF YES PROCESS COMMAND
KR: RETI ;ELSE OR THEN DO NOTHING
TXINT: CLR TI ;CLR THE TI INTERRUPT
JNB ERR_ON, TXT1
LCALL ERR_MSG
RETI
TXT1: JNB ACK_ON, TXT2
LCALL ACK_MSG
RETI
TXT2: JNB VBCR, TXT3
SETB VBLF
CLR VBCR
MOV SBUF, #0DH
RETI

Nirma Institute of Technology


Project Report
8th Sem. I.C.

TXT3: JNB VBLF, TXT4


CLR VBLF
MOV SBUF, #0AH
RETI
TXT4: MOV R0, #60H
RETI

ORG 10D8H
PROC_CMD:
MOV DPTR, #0160H
MOVX A, @DPTR
CJNE A, #48H, PCM1 ;'H'
INC DPTR
MOVX A, @DPTR
CJNE A, #48H, PCME ;'H'
INC DPTR
MOVX A, @DPTR
CJNE A, #48H, PCME ;'H'
SETB ACK_ON
CLR ERR_ON
MOV DPTR, #1001H
XRL A, A
MOVC A, @A+DPTR
MOV SBUF, A
LCALL SAV_DPTR
RET
PCM1: CJNE A, #50H, PCM2 ;'P'
INC DPTR
MOVX A, @DPTR
CJNE A, #57H, PCM1A ;'W'
SETB P_WR
LCALL PAGE_OPS
RET
PCM1A: CJNE A, #52H, PCME ;'R'

Nirma Institute of Technology


Project Report
8th Sem. I.C.

CLR P_WR
LCALL PAGE_OPS
RET
PCM2: CJNE A, #52H, PCM3 ;'R'
INC DPTR
MOVX A, @DPTR
CJNE A, #58H, PCM2A ;'X'
INC DPTR
MOVX A, @DPTR
MOV DPL, A
MOV DPH, PAGESEL
MOVX A, @DPTR
MOV SBUF, A
SETB VBCR
RET
PCM2A: CJNE A, #53H, PCME ;'S'
INC DPTR
MOVX A, @DPTR
MOV R0, A
MOV A, @R0
MOV SBUF, A
SETB VBCR
RET
PCM3: CJNE A, #58H, PCM4 ;'X' [WRITE XRAM]
INC DPTR
MOVX A, @DPTR
MOV TEMP, A
INC DPTR
MOVX A, @DPTR
MOV DPL, TEMP
MOV DPH, PAGESEL
MOVX @DPTR, A ;WRITE TO XRAM
MOVX A, @DPTR
MOV SBUF, A

Nirma Institute of Technology


Project Report
8th Sem. I.C.

SETB VBCR
RET
PCM4: CJNE A, #53H, PCME ;'S' [WRITE SRAM]
INC DPTR
MOVX A, @DPTR
MOV R0, A
INC DPTR
MOVX A, @DPTR
MOV @R0, A ;WRITE TO SRAM
MOV A, @R0
MOV SBUF, A
SETB VBCR
RET
PCME: CLR ACK_ON ;COMMAND SYNTAX ERROR SEQUENCE
SETB ERR_ON
MOV DPTR, #1031H ;ERR MSG LOCATION IS #1031H
XRL A, A
MOVC A, @A+DPTR
MOV SBUF, A
LCALL SAV_DPTR
RET

ORG 1168H
PAGE_OPS:
JNB P_WR, POP1 ;CHK IF IT IS PWRITE OR PREAD CMD
INC DPTR ;HERE IF PWRITE
MOVX A, @DPTR
CJNE A, #2FH, POP1A
LJMP POE
POP1A: JB CY, POP1B ;[A]>#2FH THEN NO BORROW=>PROCESS 30->33H
CJNE A, #34H, POP1C
LJMP POE
POP1C: JNB CY, POE ;[A]>#34H THEN NO BORROW=>ERROR
CLR CY

Nirma Institute of Technology


Project Report
8th Sem. I.C.

SUBB A, #30H ;HERE MEANS 2FH<[A]<34H


LJMP POP1E
POP1B: CJNE A, #04H, POP1D
LJMP POE
POP1D: JNB CY, POE ;[A]>#04H THEN NO BORROW=>ERROR
POP1E: MOV PAGESEL, A
POP1: MOV SBUF, PAGESEL
SETB VBCR
RET
POE: CLR ACK_ON
SETB ERR_ON
MOV DPTR, #1031H ;ERR MSG LOCATION IS #1031H
XRL A, A
MOVC A, @A+DPTR
MOV SBUF, A
RET

ORG 11A8H
ERR_MSG:
LCALL RD_DPTR
INC DPL
MOV A, DPL
CJNE A, #54H, EMX
CLR ERR_ON
MOV R0, #60H ;!!!REQUIRED FOR FUTURE COMM RECEPTION
RET
EMX: XRL A, A
MOVC A, @A+DPTR
MOV SBUF, A
LCALL SAV_DPTR
RET

ORG 11C4H
ACK_MSG:

Nirma Institute of Technology


Project Report
8th Sem. I.C.

LCALL RD_DPTR
INC DPL
MOV A, DPL
CJNE A, #21H, AMX
CLR ACK_ON
MOV R0, #60H ;!!!REQUIRED FOR FUTURE COMM RECEPTION
RET
AMX: XRL A, A
MOVC A, @A+DPTR
MOV SBUF, A
LCALL SAV_DPTR
RET

ORG 11E0H
SAV_DPTR:
MOV TEMP, DPH
MOV A, DPL
MOV DPTR, #0163H ;DPL IN #0163H AND DPH IN #0164H
MOVX @DPTR, A
INC DPTR
MOV A, TEMP
MOVX @DPTR, A
RET

ORG 11F0H
RD_DPTR:
MOV DPTR, #0163H
MOVX A, @DPTR ;RETRIEVE DPL
MOV TEMP, A ;SAVE TO TEMP
INC DPTR
MOVX A, @DPTR ;RETRIEVE DPH
MOV DPH, A ;LOAD DPH
MOV DPL, TEMP ;LOAD DPL
RET

Nirma Institute of Technology


Project Report
8th Sem. I.C.

White Line Following

As mentioned earlier in the report, straight line following for the white line has
been implemented for the autonomous robots in order to make them reach their desired
positions in the grid of automatic zone to perform their respective tasks automatically.
The test program for the same is included in the following part of the section. Here only
the test program is mentioned but the optimized version of the same with more features in
it also has been developed.

Program:

;BIT ALOCATIONS
LDIR EQU P1.0
LDRV EQU P1.1
RDIR EQU P1.2
RDRV EQU P1.3

ORG 0000H

LJMP START

ORG 0100H

START:
LCALL PORTCONFIG
SLF: MOV A,P2
CPL A
MOV P3,A
MOV A,P2
ANL A,#0FCH
MOV R0,A
MOV A,R0
CJNE A,#48H,NXT1
LJMP STRGHT
NXT1: MOV A,R0
CJNE A,#4CH,NXT2
LJMP RGHT1
NXT2: MOV A,R0
CJNE A,#58H,NXT3
LJMP LEFT1
NXT3: MOV A,R0
CJNE A,#0CCH,NXT4

Nirma Institute of Technology


Project Report
8th Sem. I.C.

LJMP RGHT2
NXT4: MOV A,R0
CJNE A,#78H,NXT5
LJMP LEFT2
NXT5: MOV A,R0
CJNE A,#8CH,NXT6
LJMP RGHT3
NXT6: MOV A,R0
CJNE A,#38H,NXT7
LJMP LEFT3
NXT7: MOV A,R0
CJNE A,#0D8H,NXT8
LJMP RGHT4
NXT8: MOV A,R0
CJNE A,#98H,NXT9
LJMP RGHT5
NXT9: MOV A,R0
CJNE A,#6CH,NXT10
LJMP LEFT4
NXT10: MOV A,R0
CJNE A,#2CH,NXT11
LJMP LEFT5
NXT11: MOV A,R0
CJNE A,#64H,NXT12
LJMP RGHT6
NXT12: MOV A,R0
CJNE A,#0D0H,NXT13
LJMP LEFT6
NXT13: MOV A,R0
CJNE A,#90H,NXT14
LJMP RGHT4
NXT14: MOV A,R0
CJNE A,#24H,NXT15
LJMP LEFT4
NXT15: MOV A,R0
CJNE A,#80H,NXT16
LJMP LEFT7
NXT16: MOV A,R0
CJNE A,#10H,NXT17
LJMP RGHT8
NXT17: MOV A,R0
CJNE A,#20H,NXT18
LJMP RGHT7
NXT18: MOV A,R0
CJNE A,#04H,NXT19
LJMP LEFT8
NXT19: MOV A,R0
CJNE A,#00H,NXT20
LJMP DEFAULT
NXT20: LJMP START

Nirma Institute of Technology


Project Report
8th Sem. I.C.

PORTCONFIG:
MOV P1,#00H
MOV P2,#0FFH
MOV P3,#0FFH
RET

STRGHT:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#40H
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

RGHT1:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#30H
LCALL DLY
SETB RDRV
CLR LDRV
MOV R1,#10H
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

LEFT1:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#30H
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#10H
LCALL DLY

Nirma Institute of Technology


Project Report
8th Sem. I.C.

CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

RGHT2:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#2BH
LCALL DLY
SETB RDRV
CLR LDRV
MOV R1,#15H
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

LEFT2:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#2BH
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#15H
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

RGHT3:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#26H
LCALL DLY
SETB RDRV

Nirma Institute of Technology


Project Report
8th Sem. I.C.

CLR LDRV
MOV R1,#1AH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

LEFT3:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#26H
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#1AH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

RGHT4:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#3AH
LCALL DLY
SETB RDRV
CLR LDRV
MOV R1,#06H
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

LEFT4:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV

Nirma Institute of Technology


Project Report
8th Sem. I.C.

MOV R1,#3AH
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#06H
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

RGHT5:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#33H
LCALL DLY
SETB RDRV
CLR LDRV
MOV R1,#0DH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

LEFT5:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#33H
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#0DH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

Nirma Institute of Technology


Project Report
8th Sem. I.C.

RGHT6:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#36H
LCALL DLY
SETB RDRV
CLR LDRV
MOV R1,#0AH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

LEFT6:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#36H
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#0AH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#20H
LCALL DLY
LJMP SLF

RGHT7:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#20H
LCALL DLY
SETB RDRV
CLR LDRV
MOV R1,#0DH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#33H

Nirma Institute of Technology


Project Report
8th Sem. I.C.

LCALL DLY
LJMP SLF

LEFT7:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#20H
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#0DH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#33H
LCALL DLY
LJMP SLF

RGHT8:
CLR RDIR
CLR LDIR
SETB RDRV
SETB LDRV
MOV R1,#23H
LCALL DLY
SETB RDRV
CLR LDRV
MOV R1,#0DH
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#30H
LCALL DLY
LJMP SLF

LEFT8:
CLR RDIR
CLR LDIR
SETB RDRV
SETB LDRV
MOV R1,#23H
LCALL DLY
CLR RDRV
SETB LDRV
MOV R1,#0DH
LCALL DLY

Nirma Institute of Technology


Project Report
8th Sem. I.C.

CLR RDRV
CLR LDRV
MOV R1,#30H
LCALL DLY
LJMP SLF

DEFAULT:
SETB RDIR
SETB LDIR
SETB RDRV
SETB LDRV
MOV R1,#20H
LCALL DLY
CLR RDRV
CLR LDRV
MOV R1,#40H
LCALL DLY
LJMP SLF

DLY:
MOV R2,#0FFH
DLYCNT: DJNZ R2,DLYCNT
DJNZ R1,DLYCNT

Nirma Institute of Technology


Project Report
8th Sem. I.C.

HARDWARE

The hardware implementation in this project is done in a unique way. As the


robots and their design are very complex and the number of inputs and outputs of the
system may vary according to the requirements and change in strategy or design the
PCBs made for the robots are designed to be multipurpose such that the same circuits and
PCBs could be used for all the robots just with minute change and increase or decrease in
the number of components mounted on the PCB.

The Schematics of various circuits are included in the following part of this
section.

Nirma Institute of Technology


5 D2 4
DIODE D1 DIODE 3 2 1
J7 TALKER DRVAX
J1 1
24 V EXT U3 7812/TO U4 7805/TO 2
1 1 3 1 3 VCC 3
+

GND

GND
VIN VOUT VIN VOUT VCC
2 4
C3 C4 C5 5
- D3 22uF D4 10uF 2.2uF D5 6

2
7
POWER SUPPLY 1 LED LED LED 8
D RED YELLOW GREEN SI.RXD 9 D
SI.TXD 10
R3 R4 R5 VCC 11
22K 10K 5K 12

J2 LISTENER DRVAX
1 J8 TALKER HB12V
2 1
3 2
4 3
5 4
6 C7 5
7 VCC 10nF 6
8 7
9 DRVAXL.LS2 8
10 DRVAXL.LS1 HB12VT.LS1 9
HB12VT.LS2 10
VCC 11
J3 LISTENER HB12V U1 U2 12
C 1
2
39
38
P0.0 P1.0/T2 1
2
3
4
D0 Q0 2
5
C
P0.1 P1.1/T2X D1 Q1
3 37 P0.2 P1.2 3 7 D2 Q2 6
4 36 P0.3 P1.3 4 8 D3 Q3 9
5 35 P0.4 P1.4 5 13 D4 Q4 12
6 34 P0.5 P1.5 6 14 D5 Q5 15
7 33 P0.6 P1.6 7 17 D6 Q6 16
8 32 P0.7 P1.7 8 18 D7 Q7 19
9 HB12VL.LS1
10 DRVAXL.LS2 21 10 SI.RXD VCC 11
DRVAXL.LS1 P2.0 P3.0 SI.TXD LE J10 TALKER AUX
22 P2.1 P3.1 11 1 OE
HB12VL.LS1 23 12 HB12VT.LS1 1
HMIL.LS1 P2.2 P3.2 HB12VT.LS2 74LS373
24 P2.3 P3.3 13 2
J4 LISTENER HMI HMIL.LS2 25 14 DRVAUXT.LS1 3
HMIL.LS3 P2.4 P3.4 DRVAUXT.LS2
1 26 P2.5 P3.5 15 4
2 LCDL.LS1 27 16 LCDT.LS1 5
AUXL.LS1 P2.6 P3.6 LCDT.LS2
3 28 P2.7 P3.7 17 6
4 7
5 19 X1 ALE/P 30 8
6 18 29 DRVAUXT.LS1 9
X2 PSEN DRVAUXT.LS2 10
7 VCC
B 8
HMIL.LS1
31 EA/VP
VCC 11 B
9 9 RST 12
10 HMIL.LS2
11 HMIL.LS3 DS89C420
12 VCC
13
14 J9 TALKER LCD
1
C6 2
10uF 3
VCC 4
5
R2 R1 6
10K 100E 7
8
J5 LISTENER LCD J6 LISTENER AUX PB LCDT.LS1 9
1 1 LCDT.LS2 10
2 2 DESIGNER'S NOTES: VCC 11
3 3 D1 OF LISTENER 12
4 4
5 5 LCD/AUX IS USED
A 6 6 FOR READING LCD A
7 7
8 8
BUSY FLAG. THE
LCDL.LS1 AUXL.LS1 REST CAN BE USED Title
9 9
C1 11.0592 Mhz C2 VISHWAKARMA MICROCONTROLLER CARD
10 10 TO READ 7 OTHER
VCC VCC 30pF Y1 30pF
INPUTS Size Document Number Rev
A4 VK.1 1.1

Date: Tuesday, April 06, 2004 Sheet 1 of 1


5 4 3 2 1
5 4 3 2 1
D1

VCC
LED R3
GREEN 5K1

D D
U1
3 D0 Q0 2
4 D1 Q1 5
7 D2 Q2 6
8 D3 Q3 9
J1 13 12
INTERFACE BUTTONS LANDER D4 Q4
14 D5 Q5 15
17 D6 Q6 16
1 MASTERON.TOGGLE 18 19
AUTOMODE.EN.TOGGLE D7 Q7
2
3 SPG1.PUSHBUTTON R2 11 1 HMIT.LS1
SPG2.PUSHBUTTON VCC LE OE J2
4
FLAP.TOGGLE 10K TALKER
5
6 DPG1.TOGGLE 74LS373
MASTER ON IS INPUT
7 DPG2.TOGGLE ON 1ST 74LS373'S D0
8 GG.PSHLOCKBUTTON U2
9 GAH.ON.TOGGLE 3 2 1
GAH.DR.TOGGLE D0 Q0
10 4 5 2
SPH.ON.TOGGLE D1 Q1 23 OTHER INPUTS CAN
C 11
SPH.DR.TOGGLE
7 D2 Q2 6 3 C
12
13 DPH.ON.TOGGLE
8
13
D3 Q3 9
12
4
5
BE THEN READ INTO
D4 Q4
14 DPH.DR.TOGGLE
SPEEDCONTROL.SLIDER1
14 D5 Q5 15 6 THE MICROCONTROLLER
15 17 16 7
16 SPEEDCONTROL.SLIDER2 18
D6
D7
Q6
Q7 19 8 USING THE 3
17 DIRNCONTROL.FWD.PB HMIT.LS1 9
18 DIRNCONTROL.REV.PB 11 1 HMIT.LS2 HMIT.LS2 10
SELECTION LINES
DIRNCONTROL.RGT.PB VCC LE OE HMIT.LS3
19 11
20 DIRNCONTROL.LFT.PB 12
21 SIGNAL.PUSHBUTTON 74LS373 VCC 13
22 14
23 U3
24 3 D0 Q0 2
4 D1 Q1 5
7 D2 Q2 6
8 D3 Q3 9
13 D4 Q4 12
14 D5 Q5 15
17 D6 Q6 16
18 D7 Q7 19
B HMIT.LS3
B
11 LE OE 1
VCC

74LS373
10
2
3
4
5
6
7
8
9

J3
POWER OUT VCC R1
RESISTOR SIP 10 [10K]
1
2
3
4
1

5
6
7
8
9
10

A A
Title
VISHWAKARMA HUMAN MACHINE INTERFACE CARD

Size Document Number Rev


A4 VK.4 1.1

Date: Tuesday, April 06, 2004 Sheet 1 of 1


5 4 3 2 1
5
DESIGNER NOTES: 4 3 24V 2 24V 1

6
Q4 IS INVERTED O/P OF Q5 U3 LMD18200T U7 LMD18200T
8 8

VCC

VCC
[MASTER ON] 9
CS OUT
TH OUT OUT1 2 RM.M1 9
CS OUT
TH OUT OUT1 2 LM.M1

RM.DR C1 LM.DR 3 C8
3 DIR BS1 1 DIR BS1 1
J1 RM.ON 5 10nF LM.ON 5 10nF
U14A PWM PWM
10nF 10nF
1 4 BRAKE BS2 11 4 BRAKE BS2 11
1 3 RM.DR C2 C7
24V
D 2 2
D

GND

GND
D2 74LS08 10 RM.M2 10 LM.M2
OUT2 OUT2
POWER HEADER LED C17
1000uF

7
U14B J2
4
R2 6 RM.ON
22K 5 RM.M1 1
74LS08 RM.M2 2
LM.M1 3
LM.M2 4
24V 24V
LAYOUT CAUTION NOTES: U14C DRV MOTORS
9

6
8 LM.DR U6 LMD18200T U8 LMD18200T
POWER HEADER , AUX MOTORS HEADER AND 10 8 8

VCC

VCC
74LS08 CS OUT RM.M1 CS OUT LM.M1
9 2 9 2
DRV MOTORS HEADER SHOULD BE RATED TO TH OUT OUT1 TH OUT OUT1

CARRY 10A [MAX] RM.DR 3 1


C3 LM.DR 3 1
C5
RM.ON DIR BS1 LM.ON 5 DIR BS1
5 PWM 10nF PWM 10nF
U14D
CHECK FOR CONNECTIONS OF 74LS08 AND 10nF 10nF
12 4 BRAKE BS2 11 4 BRAKE BS2 11
11 LM.ON C4 C6
74LS373 TO 5V AND NOT TO 24V 13

GND

GND
74LS08 10 RM.M2 10 LM.M2
U10 OUT2 OUT2
VCC
C R.DR D1 LED R1 C

7
1 3 D0 Q0 2
2 4 5 R.ON
D1 Q1 L.DR
3 7 D2 Q2 6
4 8 9 L.ON 10K
D3 Q3 MASTER.IND
5 13 D4 Q4 12
6 14 15 MASTER.ON
D5 Q5 R.BR
7 17 D6 Q6 16
8 18 19 L.BR
DRVAXL.LS1 D7 Q7
9
10 DRVAXL.LS2 DRVAXL.LS1 11 LE 24V 24V
11 VCC 1 OE
12 SINGLE PART HOIST DOUBLE PART HOIST
[SPH] [DPH]
74LS373

6
J4 U1 LMD18200T U5 LMD18200T
LISTENER U11 8 8

VCC

VCC
SPH.DR CS OUT SPH.M1 CS OUT DPH.M1
3 D0 Q0 2 9 TH OUT OUT1 2 9 TH OUT OUT1 2
4 5 SPH.ON
D1 Q1 DPH.DR
7 6 U13A
D2 Q2 DPH.ON SPH.ON SPH.DR DPH.DR
8 D3 Q3 9 1 3 DIR BS1 1 C9 3 DIR BS1 1 C11
13 12 GAH.DR 3 5 10nF 5 10nF
D4 Q4 GAH.ON MASTER.ON PWM PWM
14 D5 Q5 15 2 10nF 10nF
17 16 GG.DR 4 11 4 11
D6 Q6 GG.ON BRAKE BS2 C10 BRAKE BS2 C12
18 19 74LS08
D7 Q7

GND

GND
DRVAXL.LS2 11 U13B 10 SPH.M2 10 DPH.M2
LE DPH.ON OUT2 OUT2
1 OE 4
R3 6
MASTER.ON

7
5
B 1
RESISTOR SIP 10 74LS373
74LS08 J3 B
SPH.M1 1
SPH.M2 2
J7 DPH.M1 3
AUX MSW LANDER DPH.M2 4
10

U9 GAH.M1
2
3
4
5
6
7
8
9

5
1 RG1 3 2 GAH.M2 6
RG2 D0 Q0 GG.M1
2 4 D1 Q1 5 7
3 7 6 24V 24V GG.M2 8
D2 Q2 GIFT ARM HOIST GIFT GRIPPER
4 8 D3 Q3 9
5 13 D4 Q4 12 [GAH] [GG]
6 14 D5 Q5 15

6
7 17 16 U2 LMD18200T U4 LMD18200T AUX MOTORS
D6 Q6
8 18 19 8 8

VCC

VCC
D7 Q7 CS OUT GAH.M1 CS OUT GG.M1
9 9 TH OUT OUT1 2 9 TH OUT OUT1 2
10 11 LE OE 1
11 VCC
12 GAH.DR 3 1 C13 GG.DR 3 1 C15
VCC DIR BS1 DIR BS1
74LS373 5 10nF 5 10nF
PWM PWM
U13C
MASTER.ON 10nF 10nF
9 4 BRAKE BS2 11 4 BRAKE BS2 11
8 C14 C16
U12 GAH.ON 10
GND

GND
1 SPH.LOW 3 2 1 10 GAH.M2 10 GG.M2
SPH.HGH D0 Q0 OUT2 OUT2
2 4 5 2 74LS08
DPH.LOW D1 Q1
3 7 D2 Q2 6 3
DPH.HGH
7

7
4 8 9 4
A 5
6
GAH.LOW
GAH.HGH
13
14
D3
D4
D5
Q3
Q4
Q5
12
15
5
6
A
7 GG.OL 17 16 7
GG.CL D6 Q6
8 18 D7 Q7 19 8
DRVAXT.LS2 9
10

9 U13D
2
3
4
5
6
7
8
9

10 11 1 DRVAXT.LS1 10 MASTER.ON 12
VCC LE OE
11 11
12 GG.ON 13 Title
VCC
74LS373 J5 VISHWAKARMA DRIVE CONTROL & AUXILIARY MOTOR CARD
1 R4 TALKER 74LS08
J6 RESISTOR SIP 10 Size Document Number Rev
MSW LANDER A3 VK.2 1.0

Date: Tuesday, April 06, 2004 Sheet 1 of 1

5 4 3 2 1
5 4 3 2 1

J3
U10
F1.1 F1.1 3 2
1 F1.2 F1.2 D0 Q0 1
2 4 D1 Q1 5 2
F2.1 F2.1 7 6
3 F2.2 F2.2 D2 Q2 3
4 8 D3 Q3 9 4
G1.OL G1.OL 13 12
5 G2.OL G2.OL D4 Q4 5
6 14 D5 Q5 15 6
SG1.OL G1.STL 17 16
7 SG2.OL G2.STL D6 Q6 7
8 18 D7 Q7 19 8
HB12VT.LS1

10
9 9
2
3
4
5
6
7
8
9
11 1 HB12VT.LS1
10 R4 VCC VCC LE OE 10
11 VCC VCC
D 12 74LS373 TALKER D

C
R1
J2 RESISTOR SIP 10 [10K] VCC R R3
1

MSW LANDER 12V C6 U14A R


U12
3 +
3 2 G1.DR R9 1 G1.STL
D0 Q0 G1.ON 10uF R2 12V C8
4 D1 Q1 5 5K1 2 -
7 6 G2.DR F1 R D4
D2 Q2

6
8 9 G2.ON U1 LMD18200T TLC393
D3 Q3 MASTER.IND F1.M1 10uF
13 12 8 OUT1 2

VCC
D4 Q4 MASTER.ON D2 CS OUT LED
14 D5 Q5 15 9 TH OUT
G1

6
17 16 LSR.DRV LED 1 C9 U7 LMD18200T
D6 Q6 LSR.EN F1.DR BS1 G1.M1
18 19 3 10nF 8 OUT1 2

VCC
D7 Q7 F1.ON DIR CS OUT
5 PWM 9 TH OUT
11 LE OE 1 10nF BS1 1 C17
BS2 11 C10 G1.DR 3 DIR 10nF
4 G1.ON 5

GND
BRAKE F1.M2 PWM
OUT2 10 10nF
74LS373 11 C18
VCC BS2
4

GND
VCC BRAKE G1.M2

7
OUT2 10

R6
R R8

7
U14B R
5 +
7 G2.STL
12V C1 R7 6 -
R D3
TLC393 12V C4
10uF
C F2 LED C

6
U2 LMD18200T 10uF
8 F2.M1 G2
OUT1 2

VCC
CS OUT

6
9 U3 LMD18200T
TH OUT
1 C11 8 OUT1 2
G2.M1

VCC
J4 BS1 CS OUT
3 DIR 10nF 9 TH OUT
U11
5 PWM BS1 1 C19
3 2 F1.DR G2.DR 3 10nF
1 D0 Q0 F1.ON 10nF DIR
2 4 D1 Q1 5 BS2 11 C12 G2.ON 5 PWM
7 6 F2.DR F2.DR 4

GND
3 D2 Q2 F2.ON F2.ON BRAKE F2.M2 10nF
4 8 D3 Q3 9 OUT2 10 BS2 11 C20
13 12 SG2.DR 4

GND
5 D4 Q4 SG2.ON BRAKE G2.M2
6 14 D5 Q5 15 OUT2 10
SG1.DR

7
7 17 D6 Q6 16
18 19 SG1.ON
8 HB12VL.LS1 D7 Q7

7
9 HB12VL.LS2
10 11 LE OE 1
11 VCC
12
74LS373 12V C5 12V C26

LISTENER 12V C7
10uF 10uF
SG11 LSR

6
10uF U8 LMD18200T U9 LMD18200T
SG21 8 SG11.M1 LSR.M1
OUT1 2 8 OUT1 2

VCC

VCC
CS OUT CS OUT
6

U5 LMD18200T 9 9
SG21.M1 TH OUT TH OUT
8 OUT1 2 1 C21 1 C27
VCC

12V EXT 12V EXT CS OUT BS1 VCC BS1


9 TH OUT 3 DIR 10nF 3 DIR 10nF
BS1 1 C13 5 PWM
LSR.DRV 5 PWM
3 DIR 10nF 10nF 10nF
B SG2.ON 5 11 C22 11 C28 B
PWM BS2 BS2
4 4

GND

GND
K1 10nF BRAKE BRAKE
BS2 11 C14 OUT2 10 SG11.M2
OUT2 10 LSR.M2
4 4
GND

12V BRAKE SG21.M2


3 OUT2 10

7
5
R10
8
7

6 VCC
7 U13B
1 4
D5 12V C3 10E
2 6
DIODE SG1.DR 5 LSR.EN Q2
12V C2 2N2222
RELAY DPDT 74LS86 10uF J6
2N2222 Q1 SG12 MOTORS OUT

6
10uF U4 LMD18200T
U13A SG22 8 SG12.M1 G1.M1
OUT1 2 1

VCC
CS OUT
6

1 U6 LMD18200T 9 G1.M2 2
SG22.M1 TH OUT G2.M1
3 8 OUT1 2 1 C23 3
VCC

SG2.DR 2 CS OUT BS1 G2.M2


9 TH OUT 3 DIR 10nF 4
1 C15 SG1.ON 5 LSR.M1 5
BS1 PWM LSR.M2
74LS86 3 10nF 6
DIR 10nF LSR.AN
5 PWM BS2 11 C24 7
J1 DESIGNER NOTES: 4
GND LSR.CT 8
12V EXT 10nF BRAKE F1.M1
BS2 11 C16 OUT2 10 SG12.M2 9
1 4 F1.M2 10
GND

BRAKE SG22.M2 F2.M1


2 Q4 IS INVERTED O/P OF Q5 OUT2 10
F2.M2
11
D1
7

12
[MASTER ON] [U12] SG11.M1 13
12V POWER LED C25 SG11.M2
7

14
100uF SG21.M1 15
LAYOUT CAUTION NOTES: SG21.M2 16
A SG12.M1 17 A
R5
1.) RELAY [K1] SHOULD BE 5AMP/CONTACT TYPE SG12.M2 18
22K 2.) THE 12V POWER HEADER [J1] SHOULD BE ABLE TO SOURCE 10AMP [MAX VALUE] SG22.M1 19
3.) MOTORS OUT HEADER [J6] SHOULD BE ABLE TO SUPPLY 1A/PIN [MAX VALUE] SG22.M2 20
4.) ALL BYPASS CAPACITORS SHOULD BE AS CLOSE TO THEIR RESPECTIVE LMD18200s
AS POSSIBLE.
5.) ALL ELECTROLYTIC CAPS ARE RATED AT 16/25V
Title
VISHWAKARMA 12V H-BRIDGE BOARD

Size Document Number Rev


A3 VK.3 1.1

Date: Wednesday, April 14, 2004 Sheet 1 of 1


5 4 3 2 1
5 4 3 2 1

J4 VCC

UA7805/SOT 1
J7 U1 2
VCC 3
1 1 3 4 VCC
IN OUT
2 5

GND
+ + D1 6
7 R1 U2A U6A
HEADER 2 C1 C2 8 3 + 3 +

2
1 1
D D
2 - 2 -
8 HEADER VCC

R18 R2
U2B U6B

1
5 + 5 + RESISTOR SIP 9
7 7
6 - 6 - R16

TLC393 TLC393
J3 VCC

9
8
7
6
5
4
3
2
1
2
3 VCC U10 J1
4
5 J5 VCC U3A R3 U7A 3 2 1
D0 Q0
6 3 + 3 + 4 5 2
VCC VCC D1 Q1
7 1 1 1 7 6 3
D2 Q2
8 2 2 - 2 - 8 9 4
D3 Q3
3 13 12 5
Q1 Q2 D4 Q4
4 14 15 6
8 HEADER R4 D5 Q5
5 17 16 7
2N2222 U3B U7B D6 Q6
6 18 19 8
D7 Q7
7 5 + 5 + 9
C 8 7 7 VCC 11 10 C
LE
6 - 6 - 1 11
OE
12
8 HEADER TLC393 13
TLC393 SN74LS373/LCC 14
VCC VCC

VCC U11 HEADER 14


Q3 Q4
J2 U4A R5 U8A 3 2
D0 Q0
3 + 3 + 4 5
U12 D1 Q1
1 1 7 6
D2 Q2
1 3 2 2 - 2 - 8 9
D0 Q0 D3 Q3
2 4 5 13 12
D1 Q1 D4 Q4
3 7 6 14 15
D2 Q2 R6 D5 Q5
4 8 9 17 16
D3 Q3 U4B U8B D6 Q6
5 13 12 18 19
D4 Q4 D7 Q7
6 14 15 5 + 5 +
D5 Q5
7 17 16 7 7 VCC 11
D6 Q6 LE
8 18 19 6 - 6 - 1
D7 Q7 VCC VCC OE
9
10 11 TLC393
LE TLC393 SN74LS373/LCC
11 1

2
3
4
5
6
7
8
9
OE Q5 Q6
12

B SN74LS373/LCC B
VCC
12 HEADER R17
U5A U9A
3 + R7 3 +
RESISTOR SIP 9

1
1 1
J6 VCC 2 - 2 -
VCC
1 VCC
2 R8
3 U5B R9 U9B
4 5 + 5 +
VCC VCC 5 7 7
6 6 - 6 -
7
Q7 Q8 8
TLC393 R10 TLC393

8 HEADER

J8

1
2
A 3 A
4
5
6
7
8 VCC
Title
Digitizer

8 HEADER Size Document Number Rev


A4 DIG.1

Date: Monday, May 10, 2004 Sheet 1 of 1


5 4 3 2 1
Project Report
8th Sem. I.C.

SECTION 5
Heuristics Design and Development:

This whole project in itself has been a mammoth task to complete within a short
time of five months during which the A to Z of the project was supposed to be designed
and developed physically in reliable and working conditions. Due to the same reason a lot
of research oriented activity, new ideas and heuristics designing has been done in order to
minimize efforts, time and at the same time gain more efficiency. In the same process
implementation of certain concepts mentioned below have played and important role in
the formation of this project.

ü Optoelectronic Sensor using OPT101 and LED


ü Multipurpose Schematics and PCB Designs
ü Serial Interface for Status Monitoring and Program Updating
ü LCD interface for Status Monitoring

Optoelectronic Sensor using OPT101 and LED

Using the combination of PDIP IC – OPT101 and LED with the concept of
reflective light amplification as the Optoelectronic sensor has been a totally new
development at student level. This development has been specially beneficial as the
weight constituted by the sensors is much lesser then the commercially available ready
made sensors and also if the sensor fails it is very easy to change the IC or even the
whole set up to make the system working again.

Nirma Institute of Technology


Project Report
8th Sem. I.C.

Multipurpose Schematics and PCB Designs

The Schematics and PCB Designs of the Electronic Circuits have been done such
that the PCBs are multipurpose and just with the minute change in the number of
components mounted on the PCB and some change in the interconnections between the
PCBs, they could be used for all the robots. In fact the PCBs are made such that in most
of the general robotic applications these PCBs could be used.

The robotic systems are MIMO – Multi Input Multi Output Systems and the Set
of PCBs is made so flexible that it could be used for sensing 64 Inputs as well as for
sending 48 output signals.

Serial Interface for Status Monitoring and Program Updating

Loading the microcontroller again and again with minute changes in the program
is always a time taking process especially while testing the programs. At the same time
when the program is not performing as per the desire it is necessary to find the flaw in the
program which is possible by monitoring various RAM locations, Registers,
Microcontroller Ports, and Individual Bits etc. on the microcontroller.

Implementing Serial Interface is the solution to both these problems as the


program in the microcontroller could be quickly updated using Serial Interface and at the
same time monitoring status of various memory locations and ports etc. become easy
using the serial communication.

LCD interface for Status Monitoring

Monitoring status is difficult where the serial communication between PC and


microcontroller is not easy as the PC is not nearby. In this case the LCD is interfaced
with the microcontroller in order to monitor the status and debug the program.

Nirma Institute of Technology


Ultra-High-Speed Flash
Microcontroller User’s Guide

33
16kB 1kB
FLASH MEMORY SRAM

DUAL DATA 25

MIPS
POINTERS FOUR
HIGH-SPEED 8-BIT
WITH AUTO- ONE CLOCK-CYCLE PARALLEL
SELECT 8051 MICROPROCESSOR PORTS
INCREMENT/ 5
DECREMENT

1
DUAL SERIAL
PORTS 0
ORIGINAL
8051 DS89C420

DS89C420

SECTION 1: INTRODUCTION
Dallas Semiconductor’s DS89C420 is an 8051-compatible micro- priority, and a crystal multiplier. The device provides 256 bytes of
controller that provides improved performance and power con- RAM for variables and stack; 128 bytes can be reached using
sumption when compared to the original 8051 version. It retains direct or indirect addressing, or using indirect addressing only.
instruction set and object code compatibility with the 8051, yet In addition to improved efficiency, the DS89C420 can operate at
performs the same operations in fewer clock cycles. a maximum clock rate of 33MHz. Combined with the 12 times per-
Consequently, greater throughput is possible for the same crys- formance, this allows for a maximum performance of 33 million
tal speed. As an alternative, the DS89C420 can be run at a instructions per second (MIPs). This level of computing power is
reduced frequency to save power. The more efficient design comparable to many 16-bit processors, but without the added
allows a much slower crystal speed to get the same results as an expense and complexity if implementing a 16-bit interface.
original 8051, using much less power.
The DS89C420 incorporates a power-management mode that
The fundamental innovation of the DS89C420 is the use of only allows the device to dynamically vary the internal clock speed
one clock per instruction cycle compared with 12 for the original from 1 clock per cycle (default) to 1024 clocks per cycle. Because
8051. This results in up to 12 times improvement in performance power consumption is directly proportional to clock speed, the
over the original 8051 architecture and up to four times improve- device can reduce its operating frequency during periods of little
ment over other Dallas Semiconductor high-speed microcon- switchback. This greatly reduces power consumption. The switch-
trollers. The DS89C420 provides several peripherals and features back feature allows the device to quickly return to highest speed
in addition to all of the standard features of an 80C32. These operation upon receipt of an interrupt or serial port activity, allow-
include 16kB of on-chip flash memory, 1kB of on-chip RAM, four 8- ing the device to respond to external events while in power-man-
bit I/O ports, three 16-bit timer/counters, two on-chip UARTs, dual agement mode.
data pointers, an on-chip watchdog timer, five levels of interrupt

________________________________________________________________________ Maxim Integrated Products 1


Ultra-High-Speed Flash
Microcontroller User’s Guide

DS89C420 Special-Function Register Locations


REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P0 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
SP 81h
DPL 82h
DPH 83h
DPL1 84h
DPH1 85h
DPS 86h ID1 ID0 TSL AID — — — SEL
PCON 87h SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE
TCON 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h GATE C/T M1 M0 GATE C/T M1 M0
TL0 8Ah
TL1 8Bh
TH0 8Ch
TH1 8Dh
CKCON 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0
P1 90h P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
EXIF 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS
CKMOD 96h T2MH T1MH T0MH
SCON0 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0
SBUF0 99h
ACON 9Dh PAGEE PAGES1 PAGES0
P2 A0h P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
IE A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
SADDR0 A9h
SADDR1 AAh
P3 B0h P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
IP1 B1h — MPS1 MPT2 MPS0 MPT1 MPX1 MPT0 MPX0
IP0 B8h — LPS1 LPT2 LPS0 LPT1 LPX1 LPT0 LPX0
SADEN0 B9h
SADEN1 BAh
SCON1 C0h SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
SBUF1 C1h
ROMSIZE C2h PRAME RMS2 RMS1 RMS0
PMR C4h CD1 CD0 SWB CTM 4X/2X ALEON DME1 DME0
STATUS C5h PIS2 PIS1 PIS0 — SPTA1 SPRA1 SPTA0 SPRA0
TA C7h
T2CON C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
T2MOD C9h — — — — — — T2OE DCEN
RCAP2L CAh
RCAP2H CBh
TL2 CCh
TH2 CDh
PSW D0h CY AC F0 RS1 RS0 OV F1 P
FCNTL D5h FBUSY FERR FC3 FC2 FC1 FC0
FDATA D6h
WDCON D8h SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT
ACC E0h
EIE E8h — — — EWDI EX5 EX4 EX3 EX2
B F0h
EIP1 F1h MPWDI MPX5 MPX4 MPX3 MPX2
EIP0 F8h — — — LPWDI LPX5 LPX4 LPX3 LPX2
Note: Shaded bits are timed-access protected.

_____________________________________________________________________________________________ 10
Ultra-High-Speed Flash
Microcontroller User’s Guide
ROM Size Select (ROMSIZE)
7 6 5 4 3 2 1 0
SFR C2h — — — — PRAME RMS2 RMS1 RMS0
R-1 R-1 R-1 R-1 RT-0 RT-1 RT-0 RT-1
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset
LPX0 Least Significant Priority Select Bit for External Interrupt 0. MPX0 is the least significant bit of
Bit 0 the bit pair MPX0 (IP1.0), LPX0 that designates priority level for external interrupt 0.
Bits 7–3 These bits are reserved. Read data is 1.
PRAME Program RAM Enable. When set (= 1), the internal 1k RAM is mapped as internal program
Bit 3 space between addresses 0400h–07FFh. All program fetches and MOVC accesses are directed
to this 1k RAM. When serving as program memory, the RAM continues to be accessible as MOVX
data space (if DME0 = 1). The 1k RAM is not accessible as program space when EA = 0. When
clear (= 0), the internal 1k RAM is not accessible as program space.
RMS2–0 ROM Memory Size Select 2-0. This register is used to select the maximum on-chip decoded
Bits 2–0 address. Care must be taken that the memory location of the current program counter is valid
both before and after modification. These bits can only be modified using a timed-access procedure.
The EA pin overrides the function of these bits when asserted, forcing the device to access external
program memory only. Configuring this register to a setting that exceeds the maximum amount of
internal memory can corrupt device operation. These bits default on reset to the maximum amount
of internal program memory (i.e., 16k for DS89C420).
On-Chip ROM Address
.
RS2 RS1 RS0 MAXIMUM ON-CHIP ROM ADDRESS
0 0 0 0kB/Disable on-chip ROM
0 0 1 1kB/03FFh
0 1 0 2kB/07FFh
0 1 1 4kB/0FFFh
1 0 0 8kB/1FFFh
1 0 1 16kB/3FFFh (default)
1 1 0 32kB/7FFFh
1 1 1 64kB/FFFFh

Power Management Register (PMR)


7 6 5 4 3 2 1 0
SFR C4h CD1 CD0 SWB CTM 4X / 2X ALEON DME1 DME0
RW*-1 RW*-0 RW-0 RW*-0 RW*-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description

CD1, CD0 Clock Divide Control 1-0. These bits select the number of crystal oscillator clocks required to
Bits 7, 6 generate one machine cycle. Switching between modes requires a transition through the default
divide-by-1 mode (CD1, CD0 = 10b). Attempts to perform an invalid transition are ignored. For
example, going from the crystal multiplier 2X mode to the divide-by-1024 mode would require first
switching from the 2X crystal multiplier mode to the divide-by-1 mode, followed by the switch from
the divide-by-1 to the divide-by-1024 mode. These bits cannot be modified when running from the
internal ring oscillator (RGMD = 1). The divide-by-1024 setting (CD1,CD0 = 11b) cannot be selected
when switchback is enabled (SWB = 1) and a switchback source (serial port or external interrupt)
is active.

CD1,
CLOCK FUNCTION
CD0
00 Crystal multiplier (4X or 2X mode as determined by PMR.3)
01 Reserved (forced into divide-by-1 mode if set)
10 Divide-by-1 (default state)
11 Divide-by-1024

The setting of these bits affects timer and serial port operation. Tables located in the SFR decription
for CKCON (8Eh) detail the respective operational dependencies on these bits.
_____________________________________________________________________________________________ 28
Ultra-High-Speed Flash
Microcontroller User’s Guide

UHSM UHSM 8051 8051 UHSM vs.


HEX CLOCK TIME CLOCK TIME 8051 SPEED
INSTRUCTION CODE CYCLES @ 25MHz CYCLES @ 25MHz ADVANTAGE
CJNE A, #data, rel B4 4 160 ns 24 960 ns 6
CJNE Rn, #data, rel B8..BF 4 160 ns 24 960 ns 6
CJNE @Ri, #data, rel B6..B7 5 200 ns 24 960 ns 4.8
DJNZ Rn, rel D8..DF 4 160 ns 24 960 ns 6
DJNZ direct, rel D5 5 200 ns 24 960 ns 4.8
NOP 00 1 40 ns 12 480 ns 12

Table 5-2. INSTRUCTION SPEED SUMMARY


SPEED
INSTRUCTION CATEGORY QUANTITY
ADVANTAGE
Total instructions: 1 byte 4.0 2
4.8 1
5.3 1
6.0 12
8.0 5
12.0 27
24.0 1
Total instructions: 2 byte 4.0 1
6.0 27
8.0 5
12.0 13
Total instructions: 3 byte 4.8 3
6.0 5
8.0 8
Average across all instructions 8.5 111
SPEED
OPCODE CATEGORY ADVANTAGE QUANTITY
Total opcodes: 1 byte 4.0 4
4.8 1
5.3 1
6.0 35
8.0 5
12.0 93
24.0 1
Total opcodes: two byte 4.0 1
6.0 42
8.0 5
12.0 43
Total opcodes: three byte 4.8 4
6.0 12
8.0 8
Average across all opcodes 9.4 255

SECTION 6: MEMORY ACCESS


The DS89C420 ultra-high-speed microcontroller supports the memory interface convention established for the industry standard
80C51, but also implements two new page mode memory interfaces needed to support ultra-high-speed external operation. These
external page mode interfaces are described later in this section.

53 _____________________________________________________________________________________________
Ultra-High-Speed Flash
Microcontroller User’s Guide

Program and data memory areas can be implemented on-chip, off-chip, or as a combination. When opting not to use the internal mem-
ory provided, or when exceeding the maximum address of on-chip program or data memory, the device performs an external mem-
ory access using the expanded memory bus on ports 0 and 2. While serving as a memory bus, port 0 and port 2 cannot function as
I/O ports. The PSEN signal is driven active low to function as a chip enable or output enable when performing external code memory
fetches. The RD and WR signals serve as enables when accessing external SRAM data memory.
Program execution always begins at the reset vector, address 0000h. If on-chip program memory is enabled, program execution
begins at internal location 0000h; otherwise, external program memory is used. Any reset causes the next program fetch to begin at
this location. Subsequent branches and interrupts determine how program memory fetches deviate from sequential addressing.
INTERNAL FLASH MEMORY
The DS89C420 ultra-high-speed microcontroller contains five physically distinct blocks of embedded flash memory. The two largest
blocks, each 8kB, provide a total of 16kB for use as internal program memory. A 64-byte flash security block has been incorporated
to allow encryption during program memory verify operations. To further protect internal code against undesirable access, a three-level
lock system has been implemented in a separate flash memory block. This single-byte block contains three lock bits (LB1, LB2, LB3),
each of which can individually enable higher lock levels and greater code protection. The fifth flash memory block resident to the
DS89C420 is the option control register. This byte contains a bit to enable or disable the watchdog timer reset function (EWT =
WDCON.1) on a power-on reset.
The two 8kB program memory blocks form a contiguous 16kB address range extending from 0000h through 3FFFh. The on-chip
decoded address range is controlled in hardware by the EA pin, and in software through the ROMSIZE feature. The EA pin enables or
disables the ability to access internal program memory and overrides any software configured bit settings. The logic state of the EA
pin should be changed only when the microcontroller is being held in reset. The EA pin is sampled on each exit from the reset state to
determine whether program fetching should begin internally or externally. When the EA pin is low, all code fetches are done external-
ly through the expanded bus. When the EA pin is high, code fetches begin from internal program memory. Code fetches exceeding
the maximum address of on-chip program memory cause the device to access off-chip program memory. The maximum on-chip
decoded address is selectable by software using the ROMSIZE feature.

ROMSIZE FEATURE
Using the ROMSIZE feature, software can allow the DS89C420 to behave like a device with less on-chip memory. The maximum mem-
ory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then
restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map, allowing the full 64kB
of external memory space to be addressed.
The ROMSIZE feature has two primary uses. In the first instance, it allows the device to act as a bootstrap loader for a flash memory
or nonvolatile SRAM (NVSRAM). The internal program memory can contain a bootstrap loader, which can program the external mem-
ory device. Secondly, this method can be used to increase the amount of available program memory from 64kB to 80kB without bank
switching.
The maximum amount of on-chip memory is selected by configuring the ROM size select register bits RMS2, RMS1, RMS0 (ROM-
SIZE.2-0). The reset default condition gives access to the maximum on-chip program memory of 16kB. In this configuration, only code
addresses greater than 16kB result in external program memory accesses. The possible settings for the ROM size select register are
shown in the following table.
Table 6-1. ROMSIZE REGISTER SETTINGS
RMS2 RMS1 RMS0 MAX ON-CHIP PROGRAM MEMORY
0 0 0 0kB
0 0 1 1kB (0-03FFh)
0 1 0 2kB (0-07FFh)
0 1 1 4kB (0-0FFFh)
1 0 0 8kB (0-1FFFh)
1 0 1 16kB (0-3FFFh) DEFAULT
1 1 0 INVALID – RESERVED
1 1 1 INVALID – RESERVED

Modification of the ROMSIZE (C2h) special function register requires using the timed access procedure and must be followed by a two
machine cycle delay, such as executing two NOP instructions, before jumping to the new address range. Interrupts must be disabled
during this operation, because a call to an interrupt vector during the changing of the memory map can cause erratic results. To select

_____________________________________________________________________________________________ 54
Ultra-High-Speed Flash
Microcontroller User’s Guide

the watchdog reset function automatically. Other bits of this register are undefined and are at logic 1 when read. The value of this reg-
ister can be read at address FCh in parallel programming mode or by executing the verify option control register instruction in ROM
Loader or in-application programming mode.

FFFF FFFF

Note: The hatched areas shown on the internal and external


memory are disabled on power-up (Default)

INTERNAL
MEMORY
03FF
1kB x 8
SRAM External External
Program Data
INTERNAL SCRATCH Data OR Memory Memory
REGISTERS PAD prog mem
addr from
128 Bytes SFR 0000
400–7FF

4000
FF 3FFF

8kB x 8
128 Bytes Flash
Indirect Memory
Addressing (Program)
2000
80
7F
1FFF
2F
20 Bit Addressable 8kB x 8
1F Flash
Bank 3
Memory 03FF
Bank 2 Non-usable if
(Program)
Bank 1 Internal SRAM
Bank 0 is activated
00 0000 0000 0000

Figure 6-1. Memory Map

INTERNAL SRAM MEMORY


The DS89C420 ultra-high-speed microcontroller incorporates an internal 1kB SRAM that is usable as data, program, or merged pro-
gram/data memory. Upon a power-on reset, the internal 1kB memory is disabled and transparent to both program and data memory
maps.
When used for data, the memory is addressed through MOVX commands, and is in addition to the 256 bytes of scratchpad memory.
To enable the 1kB SRAM as internal data memory, software must set the DME0 bit (PMR.0). After setting this bit, all MOVX accesses
within the first 1kB (0000h–03FFh) is directed to the internal SRAM. Any data memory accesses outside of this range are still directed
to the expanded bus. One advantage of using the internal data memory is that MOVX operations automatically default to the fastest
access possible. Note that the DME0 bit is cleared after any reset, so access to the internal data memory is prohibited until this bit is
modified. The contents of the internal data memory are not affected by the changing of the data memory enable (DME0) bit. Table 6-
3 shows how the DME1, DME0 bits affect the data memory map.

_____________________________________________________________________________________________ 56
Ultra-High-Speed Flash
Microcontroller User’s Guide

When serving as an I/O port, the drive varies as follows: for logic 0, the port invokes a strong pulldown; for logic 1, the port invokes a
strong pullup for two oscillator cycles to assist with the logic transition. Then the port reverts to a weak pullup. This weak pullup is main-
tained until the port transitions from logic 1 to logic 0. External circuits can overdrive the weak pullup. This allows the logic 1 output
state to serve as the input state as well.
Substantial DC current is available in both the high and low levels. However, the power dissipation limitations make it inadvisable to heav-
ily load multiple pins. In general, sink and source currents should not exceed 10mA total per port (8 bits) and 25mA total per package.
Input Functions
The input state of the I/O ports is the same as that of the output logic 1. That is, the pin is pulled weakly to logic 1. This logic 1 state is
easily overcome by external components. Thus, after software writes a 1 to the port pin, the port is configured for input. When the port
is read by software, the state of the pin is read. The only exception is the read-modify-write instructions, discussed earlier. If the exter-
nal circuit is driving logic 1, then the pin is logic 1. If the external circuit is driving logic 0, then it overcomes the internal pullup. Thus,
the pin is the same as the driven logic state. Note that the port latch is not altered by a read operation. Therefore, if logic 0 is driven
onto a port pin from an external source, then removed, the pin reverts to the weak pullup, as determined by the internal latch.

SECTION 11: PROGRAMMABLE TIMERS


The ultra-high-speed microcontroller incorporates three 16-bit programmable timers and has a watchdog timer with a programmable
interval. Because the watchdog timer is significantly different from the other timers, it is described separately. The 16-bit timers are
referred to as timers.
The three timers offer the same controls and I/O functions that were available in the 80C32. As mentioned, the actual timing of these func-
tions is user selectable to be compatible with the instruction cycle of the older generation of 8051 family (12 clocks per tick) or the new
generation (1 clock per tick). The timing for each of the three timers can be selected independently and can be changed dynamically.
In most modes, the timers can be used as either counters of external events or timers. When functioning as a counter, 1 to 0 transi-
tions on a port pin are monitored and counted. When functioning as timers, they effectively count oscillator or system clock cycles. The
time base for the timer function is detailed later in this section. Because an input clock pulse must be sampled high for two system
clock cycles and low for two system clock cycles in order to be recognized, this sets the maximum sampling frequency on any timer
input at one-fourth of the main system clock frequency.
Since the ultra-high-speed microcontroller timers have a variety of features, the following lists summarize the capabilities:
Timer 0 Timer 1 Timer 2
13-bit timer/counter 13-bit timer/counter 16-bit timer/counter
16-bit timer/counter 16-bit timer/counter 16-bit timer with capture
8-bit timer w/ autoreload 8-bit timer w/ autoreload 1 6-bit autoreload timer/counter
Two 8-bit timer/counters External control pulse timer/counter 16-bit up/down autoreload
External control pulse timer/counter Baud-rate generator Timer/counter
Baud-rate generator
Timer output clock generator
16-BIT TIMERS
Timers 0 and 1 are nearly identical. Timer 2 has several additional features such as up/down counting, capture values, and an option-
al output pin that make it unique. The following table summarizes the SFR bits that control operation of timers 0, 1, and 2. Detailed bit
descriptions can be found in Section 4. After the table, timers 0 and 1 are described first, followed by a separate description for timer
2. As mentioned above, the time base for each timer can be varied, which is discussed in more detail in the following pages.

_____________________________________________________________________________________________ 96
Ultra-High-Speed Flash
Microcontroller User’s Guide

Table 11-1. Programmable Timers


BIT NAMES DESCRIPTION REGISTER LOCATION BIT POSITIONS
GATE Gate control enable for INTO pin TMOD – 89h TMOD.3
C/T Counter/timer select TMOD – 89h TMOD.2
M1, M0 Timer mode select bits TMOD – 89h TMOD.1,0
TIMER 0

TF0 Timer overflow flag TCON – 88h TCON.5


TR0 Timer run control TCON – 88h TCON.4
T0M Input clock select (/4) CKCON – 8Eh CKCON.3
T0MH Input clock high-speed select (/1) CKMOD – 96h CKMOD.3
Timer LSB TL0 – 8Ah
Timer MSB TH0 – 8Ch

GATE Gate control enable for INT1 pin TMOD – 89h TMOD.7
C/T Counter/timer select TMOD – 89h TMOD.6
M1, M0 Timer mode select bits TMOD – 89h TMOD.5,4
TIMER 1

TF1 Timer overflow flag TCON – 88h TCON.7


TR1 Timer run control TCON – 88h TCON.6
T1M Input clock select (/4) CKCON – 8Eh CKCON.4
T1MH Input clock high-speed select (/1) CKMOD – 96h CKMOD.4
Timer LSB TL1 – 8Bh
Timer MSB TH1 – 8Dh

TF2 Timer overflow flag T2CON – C8h T2CON.7


EXF2 Timer external flag T2CON – C8h T2CON.6
RCLK Timer 2 receive serial clock enable T2CON – C8h T2CON.5
TCLK Timer 2 transmit serial clock enable T2CON – C8h T2CON.4
EXEN2 External enable for T2EX pin T2CON – C8h T2CON.3
TR2 Timer run control T2CON – C8h T2CON.2
C/T2 Counter/timer select T2CON – C8h T2CON.1
TIMER 2

CP/RL2 Capture/reload select T2CON – C8h T2CON.0


T2OE Output enable for T2 pin T2MOD – C9h T2MOD.1
DCEN Down count enable T2MOD – C9h T2MOD.0
T2M Input clock select (/4) CKCON – 8Eh CKCON.5
T2MH Input clock high-speed select (/1) CKMOD – 96h CKMOD.5
Timer LSB TL2 – CCh
Timer MSB TH2 – CDh
Timer capture LSB RCAP2L – CAh
Timer capture MSB RCAP2H – CBh

TIMER 0, TIMER 1 MODES


Timers 0 and 1 both have three common operating modes. They are 13-bit timer/counter, 16-bit timer/counter, and 8-bit timer/counter
with autoreload. Timer 0 can additionally be configured to operate as two 8-bit timers. These four modes, controlled by the TMOD reg-
ister, are detailed in the following pages.
MODE 0
Mode 0 configures either timer 0 or timer 1 for operation as a 13-bit timer/counter. As shown in Figure 11-1, setting TMOD register bits
M1, M0 = 00b selects this operating mode for either timer 0 or timer 1.
When using timer 0, TL0 uses only bits 0 through 4. These bits serve as the 5 LSbs of the 13-bit timer. TH0 provides the 8 MSbs of the
13-bit timer. Bit 4 of TL0 is used as a ripple out to TH0 bit 0, thereby completely bypassing bits 5 through 7 of TL0. Once the timer is
started using the TR0 (TCON.4) timer enable, the timer counts as long as GATE (TMOD.3) is 0 or GATE is 1 and pin INTO is 1. It counts
oscillator or system clock cycles if C/T (TMOD.2) is set to a logic 0 and 1 to 0 transitions on T0 (P3.4) if C/T is set to a 1. When the 13-
bit count reaches 1FFFh (all ones), the next count causes it to roll over to 0000h. The TF0 (TCON.5) flag is set and an interrupt occurs
if enabled. The upper 3 bits of TL0 are indeterminate.

97 _____________________________________________________________________________________________
Ultra-High-Speed Flash
Microcontroller User’s Guide

Table 12-5. Timer 1 Input Clock Frequency


TIMER 1
PMR REGISTER BITS INPUT CLOCK FREQUENCY
SYSTEM CLOCK MODE
4X/2X, CD1, CD0
T1MH,T1M = 00 T1MH,T1M = 01 T1MH,T1M = 1X
Crystal multiply mode 4X 100 OSC / 12 OSC / 1 OSC / 0.25
Crystal multiply mode 2X 000 OSC / 12 OSC / 2 OSC / 0.5
Divide-by-1 (default) X01, X10 OSC / 12 OSC / 4 OSC / 1
Power-management mode (/1024) X11 OSC / 3072 OSC / 1024 OSC / 1024

Using timer 1 in the 8-bit autoreload mode, serial port baud rates for mode 1 or 3 can be calculated using the formula below.

2 SMOD_x ✕ Timer 1 input clock frequency


Modes 1, 3 baud rate = 32 (256 - TH1)

Number of serial bits / Timer 1 rollover


Number of timer 1 rollovers frequency

Timer 1 input clock frequency can be found in the previous table, SMOD_x is the logic state of the baud-rate doubler bit for the asso-
ciated UART, and TH1 is the user assigned timer 1 reload value.
Often, users already know what baud rate is desired and only need to calculate the timer reload value. An equation to calculate the
timer reload value, TH1, is as follows:

2 SMOD_x ✕ timer 1 input clock frequency


TH1 = 256 - 32 ✕ baud rate
Note that the 8-bit, autoreload mode for timer 1 is the one most commonly used for serial port applications, but that it can actually be configured in any mode, even as a
counter.

Using Timer 2 for Baud-Rate Generation


To use timer 2 as baud-rate generator for serial port 0, the timer is configured in autoreload mode. Then, either the TCLK or RCLK bit
(or both) are set to a logic 1. TCLK = 1 selects timer 2 as the baud-rate generator for the transmitter and RCLK = 1 selects timer 2 for
the receiver. Thus, serial port 0 can have the transmitter and receiver operating at different baud rates by choosing timer 1 for one data
direction and timer 2 for the other. RCLK and TCLK reside in T2CON.4 and TCON.5, respectively.
Although the timer 2 input clock can be configured similarly to timer 1, it must be placed into a baud-rate generator mode in order to
be used by serial port 0. Setting either RCLK or TCLK to a logic 1 selects timer 2 for baud-rate generation. When this is done, the timer
2 input clock becomes fixed to the oscillator frequency divided by 2. This is compatible with the 80C32. The only exception is when
timer 2 is used for baud-rate generation within power-management mode. For PMM, the system clock (OSC/1024) is used as the input
clock for timer 2. The timer 2 interrupt is automatically disabled when either RCLK or TCLK is set. Also, the TF2 (TCON.7) flag is not
set on a timer rollover. The manual reload pin, T2EX (P1.1), does not cause a reload either. Table 12-6 illustrates this relationship.

Table 12-6. Timer 2 Baud-Rate Generation


TIMER 2 INPUT CLOCK FREQUENCY
PMR REGISTER BITS
SYSTEM CLOCK MODE BAUD-RATE GENERATOR MODE
4X/2X, CD1, CD0
(RCLK OR TCLK = 1)
Crystal multiply mode 4X 100 OSC / 2
Crystal multiply mode 2X 000 OSC / 2
Divide-by-1 (default) X01, X10 OSC / 2
Power-management mode (/1024) X11 OSC / 1024

111 ____________________________________________________________________________________________
Ultra-High-Speed Flash
Microcontroller User’s Guide

Serial Program Load Operation


Program loading through a serial port is a convenient method of loading application software into the flash memory or external mem-
ory. Communication is performed over a standard, asynchronous serial communications port using a terminal emulator program with
8-N-1 (8 data bits, no parity, 1 stop bit) protocol settings. A typical application would use a simple RS-232 serial interface to in-system
program the device as part of a final production procedure.
The hardware configuration for the serial program load operation is illustrated in Figure 15-2. A variety of crystals can be used to pro-
duce standard baud rates. The serial loader is designed to operate across a 3-wire interface from a standard UART. The receive, trans-
mit, and ground wires are all that are necessary to establish communication with the device.
The serial loader implements an easy-to-use command line interface, which allows an Intel hex file to be loaded and read back from
the device. Intel hex is the standard format output by 8051 cross-assemblers.

TO PC
TD
ROIN ROOUT RXDO

RD
TOOUT DS232A TOIN TXDO

DTR
R1IN R1OUT
DS89C420

T1OUT T1IN VCC RST

EA

PSEN

HC/AC125

Figure 15-2. Serial Load Hardware Configuration

AUTOBAUD-RATE DETECTION
The serial bootstrap loader can automatically detect, within certain limits, the external baud rate and configure itself to that speed. The
loader controls serial port 0 in mode 1 (asynchronous, 1 start bit, 8 data bits, no parity, 1 stop bit, full duplex), using timer 1 in 8-bit
autoreload mode with the serial port 0 doubler bit (PCON.7) set. For these settings, an equation to calculate possible serial loader
baud rates is provided as a function of crystal frequency and timer reload value. Table 15-1 shows baud rates generated using the
equation:

Crystal Frequency
Serial Loader_Baud rate =
192 x ( 256-Timer Reload )
** Timer reload values attempted by the loader:
FF, FE, FD, FC, FB, FA, F8, F6, F5, F4, F3, F0, EC, EA, E8,
E6, E0, DD, D8, D4, D0, CC, C0, BA, B0, A8, A0, 98, 80, 60, 40
When communicating with a PC COM port having a standard 8250/16450 UART, attempt to match the loader baud rate and PC COM
port baud rate within 3% in order to maintain a reliable communication channel. If baud rates cannot be matched exactly, it is suggest-
ed configuring the loader to the faster baud rate to avoid the possibility of overflowing the DS89C420 serial input buffer.

129 ____________________________________________________________________________________________
Ultra-High-Speed Flash
Microcontroller User’s Guide

USER CODE IN-APPLICATION PROGRAMMING MODE


The DS89C420 data sheet contains the most comprehensive information relating to the in-application programming mode. Additional
supporting information can be found in the SFR definitions of FCNTL (D5h) and FDATA (F6h) of this user’s guide.
INTEL HEX FILE FORMAT
Assemblers that are 8051-compatible assemblers produce an absolute output file in Intel hex format. These files are composed of a
series of records. Records in an Intel hex file have the following format:
<header><hex information><record terminator>
The specific record elements are detailed as follows:
: II aaaa tt dddddd ... dd xx
where:
: Indicates a record beginning
II Indicates the record length
aaaa Indicates the 16-bit load address
tt Indicates the record type
dd Indicates hex data
xx Indicates the checksum = (two’s complement (II+aa+a+tt+dd+dd+...dd)
Record type 00 indicates a data record and type 01 indicates an end record. An end record appears as :00 00000 01 FF. These are
the only valid record types for a NIL hex file. Spaces are provided for clarity.
The following is a short Intel hex file. The data bytes begin at 01 and count up to 2F. Notice the record’s length, beginning address,
and record type at the start of each line and the checksum at the end:

:200000000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F20D0
:0F0020002122232425262728292A2B2C2D2E2F79
:00000001FF

REVISION HISTORY
January 24, 2001 Original Issue
October 3, 2002 Revision 1

135 ____________________________________________________________________________________________
 

         
SLCS115E − DECEMBER 1986 − REVISED JULY 2003

D Very Low Power . . . 110 µW Typ at 5 V D, JG, P, OR PW PACKAGE


(TOP VIEW)
D Fast Response Time . . . tPLH = 2.5 µs Typ
With 5-mV Overdrive
1OUT 1 8 VDD
D Single Supply Operation: 1IN − 2 7 2OUT
TLC393C . . . 3 V to 16 V 1IN + 3 6 2IN −
TLC393I . . . 3 V to 16 V GND 4 5 2IN +
TLC393Q . . . 4 V to 16 V
TLC393M . . . 4 V to 16 V
TLC193M . . . 4 V to 16 V FK PACKAGE
D On-Chip ESD Protection (TOP VIEW)

1OUT

VDD
NC

NC

NC
description
The TLC193 and TLC393 consist of dual 3 2 1 20 19
independent micropower voltage comparators NC 4 18
1IN − 5 17 NC
designed to operate from a single supply. They
NC 6 16 2OUT
are functionally similar to the LM393 but uses
one-twentieth the power for similar response 1IN + 7 15 NC
times. The open-drain MOS output stage NC 8 14 2IN −
9 10 11 12 13 NC
interfaces to a variety of loads and supplies. For
a similar device with a push-pull output

GND

2IN+
NC

NC

NC
configuration (see the TLC3702 data sheet).
Texas Instruments LinCMOS process offers NC − No internal connection
superior analog performance to standard CMOS
processes. Along with the standard CMOS
advantages of low power without sacrificing symbol (each comparator)
speed, high input impedance, and low bias
currents, the LinCMOS process offers ex- IN +
tremely stable input offset voltages, even with OUT
differential input stresses of several volts. This IN −
characteristic makes it possible to build reliable
CMOS comparators.
The TLC393C is characterized for operation over the commercial temperature range of TA = 0°C to 70°C. The
TLC393I is characterized for operation over the extended industrial temperature range of TA = −40°C to 85°C.
The TLC393Q is characterized for operation over the full automotive temperature range of TA = −40°C to 125°C.
The TLC193M and TLC393M are characterized for operation over the full military temperature range of
TA = −55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.

     !"   #!$%  &"' Copyright  1986-2003, Texas Instruments Incorporated
&!    #"   #" (" "  ") !"
&& *+' &!  # ", &"  " "%+  %!&"
",  %% #""'


POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 

         
SLCS115D − DECEMBER 1986 − REVISED JULY 2003

AVAILABLE OPTIONS
PACKAGES
VIOmax
TA SMALL OUTLINE CHIP CARRIER CERAMIC DIP PLASTIC DIP TSSOP
at 25°C
(D) (FK) (JG) (P) (PW)
0°C to 70°C 5 mV TLC393CD — — TLC393CP TLC393CPWLE
− 40°C to 85°C 5 mV TLC393ID — — TLC393IP TLC393IPWLE
− 40°C to 125°C 5 mV TLC393QD — — — —
− 55°C to 125°C 5 mV TLC393MD TLC193MFK TLC193MJG TLC393MP —
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC393CDR).

schematic
OUT

OPEN-DRAIN CMOS OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 16 V
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Total supply current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range: TLC393C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC393I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
TLC393Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 125°C
TLC393M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
TLC193M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN −.

DISSIPATION RATING TABLE


TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
P 1000 mW 8.0 mW/°C 640 mW 520 mW —
PW 525 mW 4.2 mW/°C 336 mW 273 mW —

2 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 

         
SLCS115E − DECEMBER 1986 − REVISED JULY 2003

recommended operating conditions


TLC393C
UNIT
MIN NOM MAX
Supply voltage, VDD 3 5 16 V
Common-mode input voltage, VIC −0.2 VDD − 1.5 V
Low-level output current, IOL 20 mA
Operating free-air temperature, TA 0 70 °C

electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise


noted)
TLC393C
PARAMETER TEST CONDITIONS† TA UNIT
MIN TYP MAX
VIC = VICRmin, 25°C 1.4 5
VIO Inp t offset voltage
Input oltage VDD = 5 V to 10 V,
V mV
See Note 3 0°C to 70°C 6.5
25°C 1 pA
IIO Inp t offset ccurrent
Input rrent VIC = 2.5
25V
70°C 0.3 nA
25°C 5 pA
IIB Inp t bias current
Input c rrent VIC = 2.5
25V
70°C 0.6 nA
25°C 0 to VDD − 1
VICR Common mode inp
Common-mode inputt voltage
oltage range V
0°C to 70°C 0 to VDD − 1.5
25°C 84
CMMR Common-mode
Common mode rejection ratio VIC = VICRmin 70°C 84 dB
0°C 84
25°C 85
kSVR Supply-voltage
Su ly voltage rejection ratio VDD = 5 V to 10 V 70°C 85 dB
0°C 85
25°C 300 400
VOL Lo le el o
Low-level tp t voltage
output oltage VID = −1
1 V,
V IOL = 6 mA mV
70°C 650
25°C 0.8 40 nA
IOH High le el o
High-level output
tp t ccurrent
rrent VID = 1 V,
V VO = 5 V
70°C 1 µA
25°C 22 40
IDD Supply current (both comparators) Outputs low,
low No load µA
0°C to 70°C 50
† All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.


POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
®
OPT101

MONOLITHIC PHOTODIODE AND


SINGLE-SUPPLY TRANSIMPEDANCE AMPLIFIER

FEATURES DESCRIPTION
● SINGLE SUPPLY: +2.7 to +36V The OPT101 is a monolithic photodiode with on-chip
transimpedance amplifier. Output voltage increases
● PHOTODIODE SIZE: 0.090 x 0.090 inch
linearly with light intensity. The amplifier is designed
● INTERNAL 1MΩ FEEDBACK RESISTOR for single or dual power supply operation, making it
● HIGH RESPONSIVITY: 0.45A/W (650nm) ideal for battery operated equipment.
● BANDWIDTH: 14kHz at RF = 1MΩ The integrated combination of photodiode and
● LOW QUIESCENT CURRENT: 120µA transimpedance amplifier on a single chip eliminates
the problems commonly encountered in discrete de-
● AVAILABLE IN 8-PIN DIP, 5-PIN SIP, AND
signs such as leakage current errors, noise pick-up and
8-LEAD SURFACE MOUNT PACKAGES
gain peaking due to stray capacitance. The 0.09 x 0.09
inch photodiode is operated in the photoconductive
APPLICATIONS mode for excellent linearity and low dark current.
● MEDICAL INSTRUMENTATION The OPT101 operates from +2.7V to +36V supplies
● LABORATORY INSTRUMENTATION and quiescent current is only 120µA. It is available in
clear plastic 8-pin DIP, 5-pin SIP and J-formed DIP for
● POSITION AND PROXIMITY SENSORS surface mounting. Temperature range is 0°C to 70°C.
● PHOTOGRAPHIC ANALYZERS
● BARCODE SCANNERS
● SMOKE DETECTORS
● CURRENCY CHANGERS
SPECTRAL RESPONSIVITY
0.7 0.7
Yellow
Green
Blue

Red

Ultraviolet Infrared
(Pin available V+
on DIP only.) 0.6 0.6 Photodiode Responsivity (A/W)
2 (2) 1
Voltage Output (V/µW)

3pF 0.5 0.5


Using Internal
1MΩ 0.4 1MΩ Resistor 0.4
4 (4)

8pF 0.3 0.3

0.2 0.2
5 (5)
0.1 0.1
7.5mV

λ VB
0
200 300 400 500 600 700 800 900 1000 1100
0

OPT101 Wavelength (nm)


(1) 8 (3) 3

(SIP) DIP

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©
1994 Burr-Brown Corporation 1
PDS-1257D OPT101
Printed in U.S.A. March, 1998

SBBS002
SPECIFICATIONS
At TA = +25°C, VS = +2.7V to +36V, λ = 650nm, internal 1MΩ feedback resistor, and RL = 10kΩ, unless otherwise noted.

OPT101P, W
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESPONSIVITY
Photodiode Current 650nm 0.45 A/W
Voltage Output 650nm 0.45 V/µW
vs Temperature 100 ppm/°C
Unit to Unit Variation 650nm ±5 %
Nonlinearity(1) FS Output = 24V ±0.01 % of FS
Photodiode Area (0.090 x 0.090in) 0.008 in2
(2.29 x 2.29mm) 5.2 mm2

DARK ERRORS, RTO(2)


Offset Voltage, Output +5 +7.5 +10 mV
vs Temperature ±2.5 µV/°C
vs Power Supply VS = +2.7V to +36V 10 100 µV/V
Voltage Noise, Dark, fB = 0.1Hz to 20kHz VS = +15V, VPIN3 = –15V 300 µVrms

TRANSIMPEDANCE GAIN
Resistor 1 MΩ
Tolerance, P ±0.5 ±2 %
W ±0.5 %
vs Temperature ±50 ppm/°C

FREQUENCY RESPONSE
Bandwidth VOUT = 10Vp-p 14 kHz
Rise Fall Time, 10% to 90% VOUT = 10V Step 28 µs
Settling Time, 0.05% VOUT = 10V Step 160 µs
0.1% 80 µs
1% 70 µs
Overload Recovery 100%, Return to Linear Operation 50 µs

OUTPUT
Voltage Output, High (VS) – 1.3 (VS) – 1.15 V
Capacitive Load, Stable Operation 10 nF
Short-Circuit Current VS = 36V 15 mA

POWER SUPPLY
Operating Voltage Range +2.7 +36 V
Quiescent Current Dark, VPIN3 = 0V 120 240 µA
RL = ∞, VOUT = 10V 220 µA
TEMPERATURE RANGE
Specification 0 +70 °C
Operating 0 +70 °C
Storage –25 +85 °C
Thermal Resistance, θJA 100 °C/W

NOTES: (1) Deviation in percent of full scale from best-fit straight line. (2) Referred to Output. Includes all error sources.

PHOTODIODE SPECIFICATIONS
TA = +25°C, VS = +2.7V to +36V unless otherwise noted.

Photodiode of OPT101P
PARAMETER CONDITIONS MIN TYP MAX UNITS
Photodiode Area (0.090 x 0.090in) 0.008 in2
(2.29 x 2.29mm) 5.2 mm2
Current Responsivity 650nm 0.45 A/W
650nm 865 µA/W/cm2
Dark Current VDIODE = 7.5mV 2.5 pA
vs Temperature doubles every 7°C
Capacitance 1200 pF

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

OPT101 2
OP AMP SPECIFICATIONS
At TA = +25°C, VS = +2.7V to +36V, λ = 650nm, internal 1MΩ feedback resistor, and RL = 10kΩ, unless otherwise noted.

OPT101 Op Amp(1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
INPUT
Offset Voltage ±0.5 mV
vs Temperature ±2.5 µV/°C
vs Power Supply 10 µV/V
Input Bias Current (–) Input 165 pA
vs Temperature (–) Input 1 pA/°C
Input Impedance
Differential 400 || 5 MΩ || pF
Common-Mode 250 || 35 GΩ || pF
Common-Mode Input Voltage Range Linear Operation 0 to [(VS) – 1] V
Common-Mode Rejection 90 dB
OPEN-LOOP GAIN
Open-loop Voltage Gain 90 dB
FREQUENCY RESPONSE
Gain-Bandwidth Product(2) 2 MHz
Slew Rate 1 V/µs
Settling Time 1% 5.8 µs
0.1% 7.7 µs
0.05% 8.0 µs
OUTPUT
Voltage Output, High (VS) – 1.3 (VS) – 1.15 V
Short-Circuit Current VS = +36V 15 mA
POWER SUPPLY
Operating Voltage Range +2.7 +36 V
Quiescent Current Dark, VPIN3 = 0V 120 240 µA
RL ∞, VOUT = 10V 220 µA

NOTES: (1) Op amp specifications provided for information and comparison only. (2) Stable gains ≥ 10V/V.

3 OPT101
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

D Choice of Eight Latches or Eight D-Type SN54LS373, SN54LS374, SN54S373,


Flip-Flops in a Single Package SN54S374 . . . J OR W PACKAGE
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
D 3-State Bus-Driving Outputs SN74LS374 . . . DB, DW, N, OR NS PACKAGE
D Full Parallel Access for Loading SN74S373 . . . DW OR N PACKAGE
(TOP VIEW)
D Buffered Control Inputs
D Clock-Enable Input Has Hysteresis to OC 1 20 VCC
Improve Noise Rejection (’S373 and ’S374) 1Q 2 19 8Q
D P-N-P Inputs Reduce DC Loading on Data 1D 3 18 8D
Lines (’S373 and ’S374) 2D 4 17 7D
2Q 5 16 7Q
description 3Q 6 15 6Q
3D 7 14 6D
These 8-bit registers feature 3-state outputs 4D 8 13 5D
designed specifically for driving highly capacitive 4Q 9 12 5Q
or relatively low-impedance loads. The GND 10 11 C†
high-impedance 3-state and increased
† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
without need for interface or pullup components. (TOP VIEW)
These devices are particularly attractive for

VCC
OC
implementing buffer registers, I/O ports,

1Q

8Q
1D
bidirectional bus drivers, and working registers.
3 2 1 20 19
The eight latches of the ’LS373 and ’S373 are 2D 4 18 8D
transparent D-type latches, meaning that while 2Q 5 17 7D
the enable (C or CLK) input is high, the Q outputs 3Q 6 16 7Q
follow the data (D) inputs. When C or CLK is taken 3D 7 15 6Q
low, the output is latched at the level of the data 4D 8 14 6D
that was set up. 9 10 11 12 13

The eight flip-flops of the ’LS374 and ’S374 are


4Q

5Q
5D
GND
edge-triggered D-type flip-flops. On the positive C†
transition of the clock, the Q outputs are set to the † C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
(’LS devices)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions


SN54LS’ SN74LS’
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5 4.75 5 5.25 V
VOH High-level output voltage 5.5 5.5 V
IOH High-level output current –1 –2.6 mA
IOL Low-level output current 12 24 mA
CLK high 15 15
tw Pulse duration ns
CLK low 15 15
’LS373 5↓ 5↓
tsu Data setup time ns
’LS374 20↑ 20↑
’LS373 20↓ 20↓
th Data hold time ns
’LS374‡ 5↑ 0↑
TA Operating free-air temperature –55 125 0 70 °C
‡ The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

electrical characteristics over recommended operating free-air temperature range (unless


otherwise noted)
SN54LS’ SN74LS’
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V
VCC = MIN,, VIH = 2 V,,
VOH High level output voltage
High-level 24
2.4 34
3.4 24
2.4 31
3.1 V
VIL = VIL max, IOH = MAX
VCC = MIN,, VIH = 2 V,, IOL = 12 mA 0.25 0.4 0.25 0.4
VOL Low level output voltage
Low-level V
VIL = VIL max IOL = 24 mA 0.35 0.5
Off-state output current,, VCC = MAX,, VIH = 2 V,,
IOZH 20 20 m A
high-level voltage applied VO = 2.7 V
Off-state output current,, VCC = MAX,, VIH = 2 V,,
IOZL –20
20 –20
20 m A
low-level voltage applied VO = 0.4 V
Input current at maximum
II VCC = MAX
MAX, VI = 7 V 01
0.1 01
0.1 mA
input voltage
IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 m A
IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA
IOS Short-circuit output current§ VCC = MAX –30 –130 –30 –130 mA
VCC = MAX,, ’LS373 24 40 24 40
ICC Supply current mA
Output control at 4.5 V ’LS374 27 40 27 40
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)


FROM TO ’LS373 ’LS374
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
RL = 667 Ω, CL = 45 pF,
fmax 35 50 MHz
See Note 3
tPLH RL = 667 Ω, CL = 45 pF,, 12 18
Data Any Q ns
tPHL See Note 3 12 18
tPLH RL = 667 Ω, CL = 45 pF,, 20 30 15 28
C or CLK Any Q ns
tPHL See Note 3 18 30 19 28
tPZH RL = 667 Ω, CL = 45 pF,, 15 28 20 26
OC Any Q ns
tPZL See Note 3 25 36 21 28
tPHZ 15 25 15 28
OC Any Q RL = 667 Ω, CL = 5 pF ns
tPLZ 12 20 12 20
NOTE 3: Maximum clock frequency is tested with all outputs loaded.
fmax = maximum clock frequency
tPLH = propagation delay time, low-to-high-level output
tPHL = propagation delay time, high-to-low-level output
tPZH = output enable time to high level
tPZL = output enable time to low level
tPHZ = output disable time from high level
tPLZ = output disable time from low level

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7


LMD18200 3A, 55V H-Bridge
December 1999

LMD18200
3A, 55V H-Bridge
General Description n No “shoot-through” current
n Thermal warning flag output at 145˚C
The LMD18200 is a 3A H-Bridge designed for motion control
n Thermal shutdown (outputs off) at 170˚C
applications. The device is built using a multi-technology pro-
cess which combines bipolar and CMOS control circuitry n Internal clamp diodes
with DMOS power devices on the same monolithic structure. n Shorted load protection
Ideal for driving DC and stepper motors; the LMD18200 ac- n Internal charge pump with external bootstrap capability
commodates peak output currents up to 6A. An innovative
circuit which facilitates low-loss sensing of the output current Applications
has been implemented.
n DC and stepper motor drives
n Position and velocity servomechanisms
Features n Factory automation robots
n Delivers up to 3A continuous output n Numerically controlled machinery
n Operates at supply voltages up to 55V n Computer printers and plotters
n Low RDS(ON) typically 0.3Ω per switch
n TTL and CMOS compatible inputs

Functional Diagram

DS010568-1

FIGURE 1. Functional Block Diagram of LMD18200

© 1999 National Semiconductor Corporation DS010568 www.national.com


LMD18200
Absolute Maximum Ratings (Note 1) Power Dissipation (TA = 25˚C, Free Air) 3W
If Military/Aerospace specified devices are required, Junction Temperature, TJ(max) 150˚C
please contact the National Semiconductor Sales Office/ ESD Susceptibility (Note 4) 1500V
Distributors for availability and specifications. Storage Temperature, TSTG −40˚C to +150˚C
Total Supply Voltage (VS, Pin 6) 60V Lead Temperature (Soldering, 10 sec.) 300˚C
Voltage at Pins 3, 4, 5, 8 and 9 12V
Voltage at Bootstrap Pins Operating Ratings(Note 1)
(Pins 1 and 11) VOUT +16V Junction Temperature, TJ −40˚C to +125˚C
Peak Output Current (200 ms) 6A VS Supply Voltage +12V to +55V
Continuous Output Current (Note 2) 3A
Power Dissipation (Note 3) 25W

Electrical Characteristics (Note 5)


The following specifications apply for VS = 42V, unless otherwise specified. Boldface limits apply over the entire operating
temperature range, −40˚C ≤ TJ ≤ +125˚C, all other limits are for TA = TJ = 25˚C.
Symbol Parameter Conditions Typ Limit Units
RDS(ON) Switch ON Resistance Output Current = 3A (Note 6) 0.33 0.4/0.6 Ω (max)
RDS(ON) Switch ON Resistance Output Current = 6A (Note 6) 0.33 0.4/0.6 Ω (max)
VCLAMP Clamp Diode Forward Drop Clamp Current = 3A (Note 6) 1.2 1.5 V (max)
VIL Logic Low Input Voltage Pins 3, 4, 5 −0.1 V (min)
0.8 V (max)
IIL Logic Low Input Current VIN = −0.1V, Pins = 3, 4, 5 −10 µA (max)
VIH Logic High Input Voltage Pins 3, 4, 5 2 V (min)
12 V (max)
IIH Logic High Input Current VIN = 12V, Pins = 3, 4, 5 10 µA (max)
Current Sense Output IOUT = 1A (Note 8) 377 325/300 µA (min)
425/450 µA (max)
Current Sense Linearity 1A ≤ IOUT ≤ 3A (Note 7) ±6 ±9 %
Undervoltage Lockout Outputs turn OFF 9 V (min)
11 V (max)
TJW Warning Flag Temperature Pin 9 ≤ 0.8V, IL = 2 mA 145 ˚C
VF(ON) Flag Output Saturation Voltage TJ = TJW, IL = 2 mA 0.15 V
IF(OFF) Flag Output Leakage VF = 12V 0.2 10 µA (max)
TJSD Shutdown Temperature Outputs Turn OFF 170 ˚C
IS Quiescent Supply Current All Logic Inputs Low 13 25 mA (max)
tDon Output Turn-On Delay Time Sourcing Outputs, IOUT = 3A 300 ns
Sinking Outputs, IOUT = 3A 300 ns
ton Output Turn-On Switching Time Bootstrap Capacitor = 10 nF
Sourcing Outputs, IOUT = 3A 100 ns
Sinking Outputs, IOUT = 3A 80 ns
tDoff Output Turn-Off Delay Times Sourcing Outputs, IOUT = 3A 200 ns
Sinking Outputs, IOUT = 3A 200 ns
toff Output Turn-Off Switching Times Bootstrap Capacitor = 10 nF
Sourcing Outputs, IOUT = 3A 75 ns
Sinking Outputs, IOUT = 3A 70 ns
tpw Minimum Input Pulse Width Pins 3, 4 and 5 1 µs
tcpr Charge Pump Rise Time No Bootstrap Capacitor 20 µs

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LMD18200
Pinout Description
(See Connection Diagram) (Continued)

Pin 6, VS Power Supply


Pin 7, GROUND Connection: This pin is the ground return,
and is internally connected to the mounting tab.
Pin 8, CURRENT SENSE Output: This pin provides the
sourcing current sensing output signal, which is typically
377 µA/A.
Pin 9, THERMAL FLAG Output: This pin provides the ther-
mal warning flag output signal. Pin 9 becomes active-low at
DS010568-4
145˚C (junction temperature). However the chip will not shut
itself down until 170˚C is reached at the junction. FIGURE 2. Locked Anti-Phase PWM Control
Pin 10, OUTPUT 2: Half H-bridge number 2 output.
Sign/magnitude PWM consists of separate direction (sign)
Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for
and amplitude (magnitude) signals (see Figure 3). The (ab-
Half H-bridge number 2. The recommended capacitor
solute) magnitude signal is duty-cycle modulated, and the
(10 nF) is connected between pins 10 and 11.
absence of a pulse signal (a continuous logic low level) rep-
resents zero drive. Current delivered to the load is propor-
TABLE 1. Logic Truth Table tional to pulse width. For the LMD18200, the DIRECTION in-
put (pin 3) is driven by the sign signal and the PWM input
PWM Dir Brake Active Output Drivers (pin 5) is driven by the magnitude signal.
H H L Source 1, Sink 2
H L L Sink 1, Source 2
L X L Source 1, Source 2
H H H Source 1, Source 2
H L H Sink 1, Sink 2
L X H NONE

Application Information
TYPES OF PWM SIGNALS
The LMD18200 readily interfaces with different forms of
PWM signals. Use of the part with two of the more popular DS010568-5
forms of PWM is described in the following paragraphs.
FIGURE 3. Sign/Magnitude PWM Control
Simple, locked anti-phase PWM consists of a single, vari-
able duty-cycle signal in which is encoded both direction and SIGNAL TRANSITION REQUIREMENTS
amplitude information (see Figure 2). A 50% duty-cycle To ensure proper internal logic performance, it is good prac-
PWM signal represents zero drive, since the net value of tice to avoid aligning the falling and rising edges of input sig-
voltage (integrated over one period) delivered to the load is nals. A delay of at least 1 µsec should be incorporated be-
zero. For the LMD18200, the PWM signal drives the direc- tween transitions of the Direction, Brake, and/or PWM input
tion input (pin 3) and the PWM input (pin 5) is tied to logic signals. A conservative approach is be sure there is at least
high. 500ns delay between the end of the first transition and the
beginning of the second transition. See Figure 4.

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Continental Device India Limited
An ISO/TS16949 and ISO 9001 Certified Company

NPN SILICON PLANAR SWITCHING TRANSISTORS 2N2221A


2N2222A
TO-18

Switching And Linear Application DC And VHF Amplifier Applications

ABSOLUTE MAXIMUM RATINGS


DESCRIPTION SYMBOL 2N2221A,22A UNIT

Collector -Emitter Voltage VCEO 40 V


Collector -Base Voltage VCBO 75 V
Emitter -Base Voltage VEBO 6.0 V
Collector Current Continuous IC 800 mA
Power Dissipation @Ta=25 degC PD 500 mW
Derate Above 25deg C 2.28 mW/deg C
@ Tc=25 degC PD 1.2 W
Derate Above 25deg C 6.85 mW/deg C
Operating And Storage Junction Tj, Tstg -65 to +200 deg C
Temperature Range
ELECTRICAL CHARACTERISTICS (Ta=25 deg C Unless Otherwise Specified)

DESCRIPTION SYMBOL TEST CONDITION VALUE


MIN MAX UNIT
Collector -Emitter Voltage VCEO IC=10mA,IB=0 40 - V
Collector -Base Voltage VCBO IC=10uA.IE=0 75 - V
Emitter-Base Voltage VEBO IE=10uA, IC=0 6.0 - V
Collector-Cut off Current ICBO VCB=60V, IE=0 - 10 nA

Ta=150 deg C
VCB=60V, IE=0 - 10 uA
ICEX VCE=60V, VEB=3V - 10 nA
Emitter-Cut off Current IEBO VEB=3V, IC=0 - 10 nA
Base-Cut off Current IBL VCE=60V, VEB=3V - 20 nA
Collector Emitter Saturation Voltage VCE(Sat)* IC=150mA,IB=15mA - 0.3 V
IC=500mA,IB=50mA 1.0 V
Base Emitter Saturation Voltage VBE(Sat) * IC=150mA,IB=15mA - 0.6-1.2 V
IC=500mA,IB=50mA - 2.0 V

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