PROGRAM – 2

AIM: To study the voltage analysis of Folded cascade stage using S-EDIT.

* SPICE export by: SEDIT 13.01

* Export time: Tue Mar 29 15:12:06 2011

* Design: n_foldedcascode

* Cell: folded

* View: view0

* Export as: top-level cell

* Export mode: hierarchical

* Exclude .model: no

* Exclude .end: no

* Expand paths: yes

* Wrap lines: no

* Root path: C:\Documents and Settings\Administrator\Desktop\neetu\n_foldedcascode

* Exclude global pins: no

* Control property name: SPICE

*-------- Devices: SPICE.ORDER > 0 --------

.include "C:\Documents and Settings\Administrator\Desktop\model\ml2_125[1].md"

RResistor_1 N_5 Out R=1k

MNMOS_1 Vx N_3 Out N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MPMOS_1 Vx In1 N_5 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_1 N_5 Gnd DC 3.3

VVoltageSource_2 N_3 Gnd DC 1.2

ICurrentSource_1 Vx Gnd DC 0.1m

vin in1 gnd PULSE (0 5)

.print dc v(out) v(Vx)

.dc lin source vin 0 5V 0.1

.end