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  • Toshiba Satellite M35 Compal LA-2461

    Загружено:

    Manish Patel
    618 просмотров47 страниц
    This document is a cover sheet for an engineering drawing of a schematic for the Compal EAL20 notebook computer. It contains confidential information about the schematic design. The schematic includes components like the ATI M11-P graphics card, Intel 855GME chipset, memory interfaces, USB, IEEE 1394, LAN, and other connections. The document states it is the proprietary property of Compal Electronics and may not be shared without permission.

    Исходное описание:

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    © Attribution Non-Commercial (BY-NC)

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    This document is a cover sheet for an engineering drawing of a schematic for the Compal EAL20 notebook computer. It contains confidential information about the schematic design. The schematic includes components like the ATI M11-P graphics card, Intel 855GME chipset, memory interfaces, USB, IEEE 1394, LAN, and other connections. The document states it is the proprietary property of Compal Electronics and may not be shared without permission.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    618 просмотров47 страниц

    Toshiba Satellite M35 Compal LA-2461

    Загружено:

    Manish Patel
    This document is a cover sheet for an engineering drawing of a schematic for the Compal EAL20 notebook computer. It contains confidential information about the schematic design. The schematic includes components like the ATI M11-P graphics card, Intel 855GME chipset, memory interfaces, USB, IEEE 1394, LAN, and other connections. The document states it is the proprietary property of Compal Electronics and may not be shared without permission.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 47

    A B C D E

    1 1

    Compal Confidential
    2

    Fortworth Banias 2

    EAL20 LA-2461 Schematic


    uFC-PGA Dothan / Montara-GM+
    3
    M11P-128M VRAM / ICH4-M 3

    2004-07-21
    REV: 0.3

    4 4

    Compal Electronics, Inc.


    Title
    Cover Sheet
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL20 LA-2461 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期三, 八月 04, 2004 Sheet 1 of 47
    A B C D E
    A B C D E

    Compal Confidential
    Model Name : EAL20 Fan Control Mobile Banias/Dothan
    page 4
    Thermal Sensor Clock Generator
    File Name : LA-2461 Celeron-M ADI ADM1032AR Cypress CY28346ZCT-2
    uFCPGA-478 CPU page 4,5
    1
    page 4 page 12 1

    H_A#(3..31) PSB H_D#(0..63)


    400MHz

    LCD Conn.
    page 20 Memory BUS(DDR) 200pin DDR-SO-DIMM X2
    ATI M11-P Intel 855GME BANK 0, 1, 2, 3 page 10,11

    CRT Conn. BGA-708 Pin AGP4X/DVO uFCBGA-732


    2.5V DDR200/266/333
    page 21
    with 32/64/128MB 1.5V 266MHz page 6,7,8,9

    TV-OUT Conn. On Board VRAM


    page 13,14,15,16,17,18
    page 21
    Port 2,3
    Hub-Link USB conn
    TV Encoder x2 page 35
    CH-7011A
    2
    page 19 2
    Port 4
    PCI BUS USB conn
    3.3V 33 MHz
    x1 page 35
    USB 2.0
    IDSEL:AD16
    (PIRQE#,
    IDSEL:AD18
    (PIRQ[G..H]#,
    IDSEL:AD17
    (PIRQB#,
    IDSEL:AD20
    (PIRQ[A..B]#, Intel ICH4-M
    GNT#0, GNT#3/4, GNT#1, GNT#2, 3.3V 48MHz
    REQ#0) REQ#3/4) REQ#1) REQ#2)
    BGA-421 3.3V 24.576MHz AC-LINK
    IEEE 1394a Mini PCI LAN CardBus 3.3V ATA-100
    VIA VT6301S socket RTL8100CL ENE CB714/CB1410 page 22,23,24
    page 27 page 30 page 26 page 28 IDE
    CDROM AC97 Codec MDC Conn
    Conn. page ALC250 Ver.C page 31
    25 page 31
    1394 Conn. RJ45/RJ11 5 in 1 Slot Slot 0
    page 27 page 26 page 29 page 29
    AMP EAL20 Sub Board
    HDD Conn.
    3 TPA0232 LED/SW Board 3
    LPC BUS 3.3V 33MHz
    page 25 page 32
    Conn
    SW DJ Ckt. Audio Board LS-2462 page 36
    SMsC LPC47N217 Conn
    ENE KB910 Super I/O
    page 25
    T/P Board
    RTC CKT. page 34 page 33 LS-2463 page 32 Conn
    page 24
    LS-2461 page 36

    Power On/Off CKT. Touch Pad Int.KBD PARALLEL FIR


    WL-KSW Board
    page 36 page 33 page 33
    page 37

    LS-2464
    DC/DC Interface CKT. 512KB BIOS
    page 35

    4
    page 38 4

    Power Circuit DC/DC


    page 38,39,40,41 Compal Electronics, Inc.
    42,43,44,45 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Block Diagram
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 2 of 47


    A B C D E
    A

    Symbol note:
    Voltage Rails
    :means digital ground.
    Power Plane Description S0-S1 S3 S5
    :means analog ground.
    VIN Adapter power supply (19V) N/A N/A N/A
    B+ AC or battery power rail for power circuit N/A N/A N/A @ :means reserved.
    +CPU_CORE Core voltage for CPU ON OFF OFF
    +VCCP 1.05V rail for Processor I/O ON OFF OFF
    Fortworth Banias Comparison Table
    +1.25VS 1.25V switched power rail for DDR Vtt ON OFF OFF
    +VGA_CORE 1.2V/1.0V switched power rail for VGA core power ON OFF OFF
    Item * Descrite UMA Page
    +1.35VS 1.35V switched power rail for GMCH core power ON OFF OFF
    +1.5VALW 1.5V always on power rail ON ON ON*
    +1.5VS 1.5V switched power rail for AGP interface ON OFF OFF
    VGA ATI M11P UMA 13 ~ 16

    +1.8VS 1.8V switched power rail for CPU PLL & Hub-Link ON OFF OFF VRAM 128MB/64MB N/A 13 ~ 14
    +2.5V 2.5V power rail for system DDR ON ON OFF
    +2.5VS 2.5V power rail for VGA DDR ON OFF OFF
    TV Encoder N/A CH7011A 19

    +3V
    +3VALW 3.3V always on power rail ON ON ON*
    +3V 3.3V switched power rail ON ON OFF
    +3VS 3.3V switched power rail ON OFF OFF
    +5VALW 5V always on power rail ON ON ON*
    +5VS 5V switched power rail ON OFF OFF
    +12VALW 12V always on power rail ON ON ON*
    RTCVCC RTC power ON ON ON

    Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
    Board ID Table for AD channel
    Vcc 3.3V +/- 5%
    Ra 10K +/- 5%
    ICH4-M I2C / SMBUS ADDRESSING
    1 1

    BID/PID Rb/Rc V AD_BID min V AD_BID typ V AD_BID max


    DEVICE HEX ADDRESS 0 0 0 V 0 V 0 V
    1 8.2K +/- 5% 1.412 V 1.486 V 1.560 V
    DDR SO-DIMM 0 A0 1010000X
    2 18K +/- 5% 2.015 V 2.121 V 2.227 V
    DDR SO-DIMM 1 A2 1010001X
    3 33K +/- 5% 2.406 V 2.533 V 2.659 V
    CLOCK GENERATOR (EXT.) D2 1101001X
    4 56K +/- 5% 2.660 V 2.800 V 2.940 V
    5 NC 3.135 V 3.300 V 3.465 V
    KB910 I2C / SMBUS ADDRESSING
    DEVICE HEX ADDRESS
    SM1 24C16 A 0H 1010000Xb
    Board ID PCB Revision
    SM1 SMART BATTERY 16H 0001011Xb
    SM2 ADM0132 98H 1001100Xb * 0 0.1
    CPU THERMAL MONITOR 1 0.2
    SM2 ALC250 AUDIO CODEC 00H 0000000Xb 2 0.3
    3 0.4
    4 0.5
    External PCI Devices 5
    DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ 6
    7
    1394 D0 AD16 0 E
    LAN D1 AD17 1 F
    CARD BUS D4 AD20 2 A
    5IN1 D4 AD20 2 B
    Mini-PCI D2 AD18 3,4 G,H
    AGP BUS N/A AGP_DEVSEL# N/A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 3 of 47


    A
    A B C D E

    H_D#[0..63]
    H_D#[0..63] <6>
    U12A

    H_A#[3..31] H_A#3 H_D#0


    <6> H_A#[3..31]
    H_A#4
    H_A#5
    P4
    U4
    A3#
    A4#
    Banias D0#
    D1#
    A19
    A25 H_D#1
    H_D#2
    +VCCP +VCCP
    V3 A5# D2# A22
    H_A#6 R3 B21 H_D#3
    A6# D3#

    2
    H_A#7 V2 A24 H_D#4
    H_A#8 A7# D4# H_D#5 R144 R147
    W1 A8# D5# B26
    H_A#9 T4 A21 H_D#6 54.9_0402_1% 54.9_0402_1%
    H_A#10 A9# D6# H_D#7 @ @
    W2 A10# D7# B20
    H_A#11 Y4 C20 H_D#8
    A11# D8#

    1
    H_A#12 Y1 B24 H_D#9
    H_A#13 A12# D9# H_D#10 H_CPURST# ITP_TDO
    U1 A13# D10# D24
    4 H_A#14 H_D#11 4
    AA3 A14# D11# E24
    H_A#15 Y3 C26 H_D#12
    H_A#16 A15# D12# H_D#13
    AA2 A16# D13# B23
    H_A#17 AF4 E23 H_D#14
    H_A#18 A17# D14# H_D#15
    AC4 A18# D15# C25
    H_A#19 AC7 H23 H_D#16
    H_A#20 A19# D16# H_D#17 +VCCP
    AC3 A20# D17# G25
    H_A#21 AD3 L23 H_D#18
    H_A#22 A21# D18# H_D#19 ITP_TMS ITP_TRST#
    AE4 A22# D19# M26 1 2 1 2
    H_A#23 AD2 H24 H_D#20 R149 39.2_0603_1% R154 680_0402_5%
    H_A#24 A23# D20# H_D#21 ITP_TDI ITP_TCK
    AB4 A24# D21# F25 1 2 1 2
    H_A#25 AC6 A25# ADDR GROUP DATA GROUP D22# G24 H_D#22 R151 150_0402_1% R153 27.4_0402_1%
    H_A#26 AD5 J23 H_D#23
    H_A#27 A26# D23# H_D#24
    AE2 A27# D24# M23
    H_A#28 AD6 J25 H_D#25
    H_REQ#[0..4] H_A#29 A28# D25# H_D#26
    <6> H_REQ#[0:4] AF3 A29# D26# L26
    H_A#30 AE1 N24 H_D#27
    H_A#31 A30# D27# H_D#28
    AF1 A31# D28# M25
    H26 H_D#29
    H_REQ#0 D29# H_D#30
    R2 REQ0# D30# N25
    H_REQ#1 P3 K25 H_D#31
    H_REQ#2 REQ1# D31# H_D#32
    T2 REQ2# D32# Y26
    H_REQ#3 H_D#33
    H_REQ#4
    P1
    T1
    REQ3#
    REQ4#
    D33#
    D34#
    AA24
    T25
    U23
    H_D#34
    H_D#35
    Thermal Sensor ADI ADM1032AR
    D35# H_D#36 +3VS
    <6> H_ADSTB#0 U3 ADSTB0# D36# V23
    AE5 R24 H_D#37
    <6> H_ADSTB#1 ADSTB1# D37#
    R26 H_D#38
    D38# H_D#39
    D39# R23
    A16 AA23 H_D#40 W =15mil U11
    <12> CLK_CPU_ITP ITP_CLK0 D40#
    A15 U26 H_D#41 2 1 8
    <12> CLK_CPU_ITP# ITP_CLK1 D41# VDD SCLK EC_SMC_2 <31,34>

    1
    V24 H_D#42 C94 R121@ 1
    3 D42# H_D#43 H_THERMDA 3
    <12> CLK_CPU_BCLK B15 BCLK0 D43# U25 2 D+ SDATA 7 EC_SMD_2 <31,34>
    HOST CLK

    10K_0402_5%
    H_D#44

    0.1U_0402_16V4Z
    <12> CLK_CPU_BCLK# B14 BCLK1 D44# V26
    H_D#45 1 C88 H_THERMDC
    D45# Y23 3 D- ALERT# 6
    H_D#46 2
    D46# AA26

    2
    Y25 H_D#47 2200P_0402_25V7K 4 5
    D47# H_D#48 THERM# GND
    <6> H_ADS# N2 ADS# D48# AB25
    L1 AC23 H_D#49
    <6> H_BNR# BNR# D49#
    J3 AB24 H_D#50 ADM1032AR_SOP8
    <6> H_BPRI# BPRI# D50#
    <6> H_BR0# N4 BR0# D51# AC20 H_D#51 Address:1001_100X
    L4 AC22 H_D#52
    <6> H_DEFER# DEFER# D52# H_D#53
    <6> H_DRDY# H2 DRDY# D53# AC25
    K3 AD23 H_D#54
    <6> H_HIT# HIT# D54#
    <6> H_HITM# K4 HITM# CONTROL GROUP D55# AE22 H_D#55
    1 2 H_IERR# A4 AF23 H_D#56
    +VCCP R152 IERR# D56# H_D#57
    <6> H_LOCK# J2 LOCK# D57# AD24
    56_0402_5% H_CPURST# B11 AF20 H_D#58
    <6> H_CPURST# RESET# D58# H_D#59
    D59# AE21
    AD21 H_D#60
    H_RS#0 D60# H_D#61
    <6> H_RS#0 H1 RS0# D61# AF25
    H_RS#1 K1 AF22 H_D#62
    <6> H_RS#1 RS1# D62#
    H_RS#2 L2 AF26 H_D#63
    <6> H_RS#2 RS2# D63#
    <6> H_TRDY# M3 TRDY#

    DINV0# D25 H_DINV#0 <6>


    C8
    B8
    BPM0#
    DINV1#
    DINV2#
    J26
    T24
    AD20
    H_DINV#1
    H_DINV#2
    <6>
    <6> Fan Control circuit
    BPM1# DINV3# H_DINV#3 <6>
    A9 BPM2#
    +3VALW 1 R145 2 C9 BPM3#
    150_0402_1% C23
    DSTBN0# H_DSTBN#0 <6>
    ITP_DBRESET# R1501 2 0_0402_5% A7 K24
    <23> ITP_DBRESET# DBR# DSTBN1# H_DSTBN#1 <6>
    <6> H_DBSY# M2 DBSY# DSTBN2# W25 H_DSTBN#2 <6>
    2 2
    <7,22> H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 <6> +5VS
    <7> H_DPWR# C19 DPWR# DSTBP0# C22 H_DSTBP#0 <6> Joint use LM358A with Power
    A10 L24 C412
    1 2 B10
    PRDY#
    MISC DSTBP1#
    W24
    H_DSTBP#1 <6>
    0.1U_0402_16V4Z Battery detect circuit.
    +VCCP PREQ# DSTBP2# H_DSTBP#2 <6>
    R374 H_PROCHOT# B17 AE25 1 2
    PROCHOT# DSTBP3# H_DSTBP#3 <6>
    330_0402_5% 1

    1
    H_CPUPWRGD E4 PU5B C397
    <22> H_CPUPWRGD PWRGOOD

    1
    H_CPUSLP# A6 5 LM358A_SO8 C D21
    <22> H_CPUSLP# SLP# <34> EN_DFAN1 +
    ITP_TCK A13 FAN1_ON 1 Q32 10U_0805_10V4Z
    ITP_TDI TCK 0 7 R361
    2
    100_0402_5%
    2
    B 2
    FMMT619_SOT23 1SS355_SOD323
    C12 TDI 1 2 6 -
    ITP_TDO A12 C2 H_A20M# R358 1 E
    TDO A20M# H_A20M# <22>

    2
    R1462 1 @ 1K_0402_5% TEST1 C5 D3 10K_0402_5%
    TEST1 FERR# H_FERR# <22>
    1 2 @ 1K_0402_5% TEST2 F23 TEST2 IGNNE# A3 H_IGNNE#
    H_IGNNE# <22>
    C410

    1
    R378 ITP_TMS C11 B5 H_INIT# 0.1U_0402_16V4Z
    TMS INIT# H_INIT# <22> 2
    ITP_TRST# B13 D1 H_INTR D20
    TRST# LINT0/INTR H_INTR <22>
    D4 H_NMI 1 2 1N4148_SOD80
    LINT1/NMI H_NMI <22>
    R364 8.2K_0402_5%
    THERMAL STPCLK# C6 H_STPCLK#
    H_STPCLK# <22>
    JP7

    2
    H_THERMDA B18 B4 H_SMI# FAN1_VOUT
    H_THERMDC THERMDA DIODE SMI# H_SMI# <22> 1
    A18 THERMDC 2
    H_THERMTRIP# C17
    THERMTRIP# LEGACY CPU 3
    +3VS 1 2
    R297 10K_0402_5% ACES_85205-0300
    mFCBGA479
    <34> FANSPEED1 1
    1 @
    @ C313
    C310 1000P_0402_50V7K
    1000P_0402_50V7K 2
    2

    1
    Close to Fan Conn. 1
    H_PROCHOT# 1 2 +VCCP
    R148 56_0402_5% 1 2 2 1
    +VCCP THRMTRIP# <23>
    R155 R156
    56_0402_5% 56_0402_5%

    H_THERMTRIP#
    Compal Electronics, Inc.
    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL INTEL CPU BANIAS (1 of 2)
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 4 of 47
    A B C D E
    A B C D E

    +CPU_CORE
    U12B +CPU_CORE U12C
    R44 54.9_0402_1%
    1 @ 2 VCCSENSE AE7 A2 F20 T26
    VSSSENSE AF6 VCCSENSE VSS VCC VSS
    1 2 VSSSENSE VSS A5 1 1 1 1 F22 VCC VSS U2
    R45 @ 54.9_0402_1% A8 G5 U6
    VSS + C333 + C334 + C336 + C335 VCC VSS
    VSS A11 G21 VCC VSS U22
    +CPU_VCCA F26 A14 220U_D2_2VM 220U_D2_2VM 220U_D2_2VM 220U_D2_2VM H6 U24
    1 VCCA0 VSS VCC VSS 1
    B1 A17 @ H22 V1
    VCCA1 VSS 2 2 2 2 VCC VSS
    +1.8VS 1 R75 2 N1 VCCA2 VSS A20 J5 VCC VSS V4
    0_1206_5% AC26 A23 J21 V5
    VCCA3 VSS VCC VSS
    VSS A26 K22 VCC VSS V21
    +1.5VS 1 R108 2 +VCCP P23 VCCQ0 VSS B3 U5 VCC VSS V25
    @ 0_1206_5% W4 B6 V6 W3
    VCCQ1 VSS +CPU_CORE VCC VSS
    VSS B9 V22 VCC VSS W6

    Dothan VCCA update(WW45 2003) D10 VCCP


    Banias VSS
    VSS
    B12
    B16
    10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
    W5
    W21
    VCC
    VCC
    VSS
    VSS
    W22
    W23
    Dothan B-Step support 1.5V only for VCCA
    D12
    D14
    VCCP
    VCCP
    VSS
    VSS
    B19
    B22
    1
    C387
    1
    C382
    1
    C38
    1
    C52
    1
    C443
    1
    C385
    1
    C383
    Y6
    Y22
    VCC
    VCC
    Banias VSS
    VSS
    W26
    Y2
    D16 VCCP VSS B25 AA5 VCC VSS Y5
    E11 C1 10U_1206_6.3V6M AA7 Y21
    VCCP VSS 2 2 2 2 2 2 2 VCC VSS
    E13 VCCP VSS C4 AA9 VCC VSS Y24
    E15 C7 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M AA11 AA1
    VCCP VSS VCC VSS
    F10 VCCP VSS C10 AA13 VCC VSS AA4
    F12 VCCP VSS C13 AA15 VCC VSS AA6
    F14 C15 +CPU_CORE AA17 AA8
    VCCP VSS VCC VSS
    F16 VCCP VSS C18 AA19 VCC VSS AA10
    K6 C21 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M AA21 AA12
    VCCP VSS VCC VSS
    L5 C24 1 1 1 1 1 1 1 AB6 AA14

    POWER, GROUNG, RESERVED SIGNALS AND NC


    VCCP VSS VCC VSS
    L21 VCCP VSS D2 AB8 VCC VSS AA16
    M6 D5 C409 C442 C424 C80 C43 C39 C41 AB10 AA18
    VCCP VSS 10U_1206_6.3V6M VCC VSS
    M22 VCCP VSS D7 AB12 VCC VSS AA20
    2 2 2 2 2 2 2
    N5 VCCP VSS D9 AB14 VCC VSS AA22
    N21 VCCP VSS D11 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M AB16 VCC POWER, GROUND VSS AA25
    P6 VCCP VSS D13 AB18 VCC VSS AB3
    P22 VCCP VSS D15 AB20 VCC VSS AB5
    R5 D17 +CPU_CORE AB22 AB7
    VCCP VSS VCC VSS
    R21 VCCP VSS D19 AC9 VCC VSS AB9
    10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
    T6 VCCP VSS D21 AC11 VCC VSS AB11
    2 2
    T22 VCCP VSS D23 1 1 1 1 1 1 1 AC13 VCC VSS AB13
    U21 VCCP VSS D26 AC15 VCC VSS AB15
    E3 C42 C63 C75 C446 C444 C386 C384 AC17 AB17
    VSS 10U_1206_6.3V6M VCC VSS
    VSS E6 AC19 VCC VSS AB19
    2 2 2 2 2 2 2
    +CPU_CORE D6 VCC VSS E8 AD8 VCC VSS AB21
    D8 E10 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M AD10 AB23
    VCC VSS VCC VSS
    D18 VCC VSS E12 AD12 VCC VSS AB26
    D20 VCC VSS E14 AD14 VCC VSS AC2
    D22 E16 +CPU_CORE AD16 AC5
    VCC VSS VCC VSS
    E5 VCC VSS E18 AD18 VCC VSS AC8
    10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
    E7 VCC VSS E20 AE9 VCC VSS AC10
    E9 VCC VSS E22 1 1 1 1 1 1 1 AE11 VCC VSS AC12
    Resistor placed within E17 VCC VSS E25 AE13 VCC VSS AC14
    E19 F1 C425 C408 C373 C374 C441 C375 C51 AE15 AC16
    0.5" of CPU pin.Trace E21
    VCC VSS
    F4 10U_1206_6.3V6M AE17
    VCC VSS
    AC18
    should be at least 25 VCC VSS 2 2 2 2 2 2 2 VCC VSS
    F6 VCC VSS F5 AE19 VCC VSS AC21
    miles away from any F8 F7 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M AF8 AC24
    VCC VSS VCC VSS
    F18 F9 AF10 AD1
    other toggling signal. VCC VSS
    F11 AF12
    VCC VSS
    AD4
    VSS +CPU_CORE VCC VSS
    VSS F13 AF14 VCC VSS AD7
    <45> PSI# E1 PSI# VSS F15 10U_1206_6.3V6M 10U_1206_6.3V6M AF16 VCC VSS AD9
    10U_1206_6.3V6M
    VSS F17 AF18 VCC VSS AD11
    +VCCP E2 F19 AD13
    <45> CPU_VID0 VID0 VSS 1 1 1 1 1 1 1 VSS
    <45> CPU_VID1 F2 VID1 VSS F21 VSS AD15
    <45> CPU_VID2 F3 F24 C40 C62 C76 C77 C78 C79 C445 AD17
    VID2 VSS VSS
    1

    <45> CPU_VID3 G3 G2 10U_1206_6.3V6M AD19


    R66 VID3 VSS 2 2 2 2 2 2 2 VSS
    <45> CPU_VID4 G4 VID4 VSS G6 VSS AD22
    1K_0402_1% <45> CPU_VID5 H4 G22 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M M4 AD25
    VID5 VSS VSS VSS
    VSS G23 M5 VSS VSS AE3
    VSS G26 M21 VSS VSS AE6
    2

    GTL_REF0 AD26 H3 M24 AE8


    3 GTLREF0 VSS VSS VSS 3
    E26 GTLREF1 VSS H5 N3 VSS VSS AE10
    2

    1 1 G1 GTLREF2 VSS H21 N6 VSS VSS AE12


    R65 AC1 GTLREF3 VSS H25 Vcc-core C,uF ESR, mohm ESL,nH N22 VSS VSS AE14
    2K_0402_1% C30 C29 J1 N23 AE16
    1U_0603_10V4Z 220P_0402_50V7K VSS
    J4
    Decoupling N26
    VSS VSS
    AE18
    2 2 VSS VSS VSS
    COMP0 P25 COMP0 VSS J6 SPCAP,Polymer 4X220uF 12m ohm/4 3.5nH/4 P2 VSS VSS AE20
    1

    COMP1 P26 J22 P5 AE23


    COMP1 VSS VSS VSS
    COMP2 AB2 COMP2 VSS J24 MLCC 0805 X5R 35X10uF 5m ohm/35 0.6nH/35 P21 VSS VSS AE26
    COMP3 AB1 K2 P24 AF2
    COMP3 VSS VSS VSS
    VSS K5 R1 VSS VSS AF5
    VSS K21 R4 VSS VSS AF9
    B2 RSVD VSS K23 R6 VSS VSS AF11
    AF7 RSVD VSS K26 R22 VSS VSS AF13
    C14 RSVD VSS L3 R25 VSS VSS AF15
    C3 L6 +CPU_VCCA T3 AF17
    R158 RSVD VSS VSS VSS
    VSS L22 T5 VSS VSS AF19
    2 1 C16 TEST3 VSS L25 T21 VSS VSS AF21
    @ 1K_0402_5% M1 T23 AF24
    VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VSS VSS
    1

    R88 R93 R60 R58 1 1 1 1 1 1 1 1


    mFCBGA479 mFCBGA479
    27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% C74 C71 C34 C37 C64 C58 C104 C97
    0.01U_0402_16V7K 10U_1206_6.3V6M
    2 2 2 2 2 2 2 2
    2

    0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K

    +VCCP

    0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


    1 1
    4 1 1 1 1 1 1 1 1 1 1 4
    C93 + C113 + @ C399
    C457 C434 C413 C392 C456 C404 C454 C419 C437 0.1U_0402_10V6K
    150U_D2_6.3VM 150U_D2_6.3VM
    2 2 2 2 2 2 2 2 2 2 2 2
    Resistor placed within
    0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
    0.5" of CPU pin.Trace
    should be at least 25 Compal Electronics, Inc.
    miles away from any Title

    other toggling signal. INTEL CPU BANIAS (2 of 2)


    Size Document Number R ev
    0.3
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 5 of 47
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    A B C D E
    5 4 3 2 1

    U14A
    H_A#[3..31] H_D#[0..63]
    <4> H_A#[3..31] H_D#[0..63] <4>
    H_REQ#[0..4] Montara-GM(L)
    <4> H_REQ#[0..4]
    H_A#3
    H_A#4
    P23 HA#3 HD#0 K22 H_D#0
    H_D#1
    HOST REF VOLTAGE
    T25 HA#4 HD#1 H27
    HUB_PD[0..10] H_A#5 T28 K25 H_D#2
    D <22> HUB_PD[0..10] HA#5 HD#2 D
    H_A#6 R27 L24 H_D#3
    H_A#7 HA#6 HD#3 H_D#4 +VCCP +VCCP +VCCP
    U23 HA7# HD#4 J27
    H_A#8 U24 G28 H_D#5
    H_A#9 HA#8 HD#5 H_D#6
    R24 HA#9 HD#6 L27

    2
    H_A#10 U28 L23 H_D#7
    H_A#11 HA#10 HD#7 H_D#8 R137 R138 R161
    V28 HA#11 HD#8 L25
    H_A#12 U27 J24 H_D#9 301_0603_1% 301_0603_1% 49.9_0603_1%
    H_A#13 HA#12 HD#9 H_D#10
    T27 HA#13 HD#10 H25
    H_A#14 V27 K23 H_D#11 W=10mil W=10mil W=10mil
    HA#14 HD#11

    1
    H_A#15 U25 G27 H_D#12 HXSWING HY SWING HCCVREF
    H_A#16 HA#15 HD#12 H_D#13
    V26 HA#16 HD#13 K26 (0.35V) (0.35V) (0.7V)

    2
    H_A#17 Y24 J23 H_D#14 2 2 2 2
    H_A#18 HA#17 HD#14 H_D#15 R136 R139 C106 R162 C119
    V25 HA#18 HD#15 H26
    H_A#19 V23 F25 H_D#16 C108 C122
    H_A#20 HA#19 HD#16 H_D#17 150_0603_1% 0.1U_0402_16V4Z 150_0603_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    W25 HA#20 HD#17 F26
    H_A#21 H_D#18 1 1 1
    100_0603_1% 1U_0603_10V4Z 1
    Y25 HA#21 HD#18 B27

    1
    H_A#22 AA27 H23 H_D#19
    H_A#23 HA#22 HD#19 H_D#20
    W24 HA#23 HD#20 E27
    H_A#24 W23 G25 H_D#21
    H_A#25 HA#24 HD#21 H_D#22
    W27 HA#25 HD#22 F28
    H_A#26 Y27 D27 H_D#23
    H_A#27 HA#26 HD#23 H_D#24 +VCCP +VCCP
    AA28 HA#27 HD#24 G24
    H_A#28 W28 C28 H_D#25
    H_A#29 HA#28 HD#25 H_D#26
    AB27 HA#29 HD#26 B26

    2
    H_A#30 Y26 G22 H_D#27
    H_A#31 HA#30 HD#27 H_D#28 R425 R417
    AB28 HA#31 HD#28 C26
    E26 H_D#29 49.9_0603_1% 49.9_0603_1%
    H_REQ#0 HD#29 H_D#30
    R28 HREQ#0 HD#30 G23
    H_REQ#1 P25 B28 H_D#31 W=10mil W=20mil
    HREQ#1 HD#31

    1
    H_REQ#2 R23 B21 H_D#32 HAVREF HDVREF
    H_REQ#3 HREQ#2 HD#32 H_D#33
    R25 HREQ#3 HD#33 G21 (0.7V) (0.7V)

    2
    C C

    <4> H_ADSTB#0
    H_REQ#4 T23
    T26
    HREQ#4
    HADSTB#0
    HOST HD#34
    HD#35
    C24
    C23
    H_D#34
    H_D#35
    2 2 2
    C490
    AA26 D22 H_D#36 R427 C516 C494
    <4> H_ADSTB#1 HADSTB#1 HD#36 R416
    C25 H_D#37 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    HD#37 H_D#38 100_0603_1% 1 1
    1U_0603_10V4Z 1
    <12> CLK_MCH_BCLK# AD29 BCLK# HD#38 E24

    1
    AE29 D24 H_D#39 100_0603_1%
    <12> CLK_MCH_BCLK BCLK HD#39
    HY SWING K28 G20 H_D#40
    HXSWING B18 HYSWING HD#40 H_D#41
    W=10mil HXSWING HD#41 E23
    R390 1 2 27.4_0402_1% HYRCOMP H28 B22 H_D#42
    R134 1 HXRCOMP B20 HYRCOMP HD#42 H_D#43
    2 27.4_0402_1% HXRCOMP HD#43 B23
    F23 H_D#44
    HDVREF HD#44 H_D#45
    K21 HVREF0 HD#45 F21
    J21 C20 H_D#46
    HVREF1 HD#46 H_D#47
    HCCVREF
    HAVREF
    J17
    Y28
    HVREF2
    HCCVREF
    HD#47
    HD#48
    C21
    G18 H_D#48
    H_D#49
    HUB I/F REF VOLTAGE
    Y22 HAVREF HD#49 E19
    E20 H_D#50
    H_DSTBN#0 HD#50 H_D#51 +1.5VS
    <4> H_DSTBN#0 J28 HDSTBN#0 HD#51 G17
    H_DSTBN#1 C27 D20 H_D#52
    <4> H_DSTBN#1 H_DSTBN#2 HDSTBN#1 HD#52 H_D#53
    <4> H_DSTBN#2 E22 HDSTBN#2 HD#53 F19

    2
    H_DSTBN#3 D18 C19 H_D#54
    <4> H_DSTBN#3 H_DSTBP#0 HDSTBN#3 HD#54 H_D#55 R171
    <4> H_DSTBP#0 K27 HDSTBP#0 HD#55 C17
    H_DSTBP#1 D26 F17 H_D#56 80.6_0603_1%
    <4> H_DSTBP#1 H_DSTBP#2 HDSTBP#1 HD#56 H_D#57
    <4> H_DSTBP#2 E21 HDSTBP#2 HD#57 B19
    H_DSTBP#3 E18 G16 H_D#58
    <4> H_DSTBP#3 HDSTBP#3 HD#58

    1
    H_DINV#0 J25 E16 H_D#59 W=20mil
    <4> H_DINV#0 H_DINV#1 DINV0# HD#59 H_D#60 HUB_VSWING
    <4> H_DINV#1 E25 DINV1# HD#60 C16 HUB_VSWING (0.796V)
    H_DINV#2 B25 E17 H_D#61
    <4> H_DINV#2 H_DINV#3 DINV2# HD#61 H_D#62
    <4> H_DINV#3 G19 DINV3# HD#62 D16 2 2

    2
    C18 H_D#63 C145 C146
    CPURST# HD#63
    <4> H_CPURST# F15 CPURST# R172
    B 51.1_0603_1% 0.1U_0402_16V4Z 0.01U_0402_16V7K B
    HUB_PD0 1 1
    U7 HL_0
    HUB_PD1 U4 HL_1

    1
    HUB_PD2 U3 L28 W=20mil
    HL_2 ADS# H_ADS# <4>
    HUB_PD3 V3 M25 HUB_VREF HUB_VREF (0.35V)
    HL_3 HTRDY# H_TRDY# <4>
    HUB_PD4 W2 N24
    HL_4 DRDY# H_DRDY# <4>
    HUB_PD5 W6 M28 2 2
    HL_5 DEFER# H_DEFER# <4>

    2
    HUB_PD6 V6 N28 C169 C170
    HL_6 HITM# H_HITM# <4> R180
    HUB_PD7 W7 N27
    HL_7 HIT# H_HIT# <4> 40.2_0603_1% 0.01U_0402_16V7K
    HUB_PD8 T3 P27 0.1U_0402_16V4Z
    HL_8 HLOCK# H_LOCK# <4> 1 1
    HUB_PD9 V5 M23
    HL_9 BREQ0# H_BR0# <4>
    HUB I/F

    HUB_PD10 V4 N25
    HL_10 BNR# H_BNR# <4>
    1
    HI_PSTRB W3 P28
    <22> HUB_PSTRB HLSTB BPRI# H_BPRI# <4>
    HI_PSTRB# V2 M26
    <22> HUB_PSTRB# HLSTB# DBSY# H_DBSY# <4>
    2 1 HUB_RCOMP T2 N23
    +1.35VS HLRCOMP RS#0 H_RS#0 <4>
    R461 37.4_0402_1% HUB_VSWING U2 P26
    PSWING RS#1 H_RS#1 <4>
    HUB_VREF W1 M27
    HLVREF RS#2 H_RS#2 <4>

    RG82855GME_uFCBGA732

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    INTEL 855GME-HOST(1/4)
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 6 of 47


    5 4 3 2 1
    5 4 3 2 1

    U14B 855GME DVO/AGP Pin Muxing


    DVOC_D[0..11]
    <13,19> DVOC_D[0..11]
    DVOB_D[0..11] DVOB_D0
    Montara-GM(L) Ball DVO Mode AGP Mode
    <13> DVOB_D[0..11] R3 DVOBD0/(NC) BLUE C9 GMCH_CRT_B <21>
    DVOB_D1 R5 D9 R3 DVOBD0 GAD3
    AGP_SBA[0..7] DVOB_D2 DVOBD1/(NC) BLUE#
    <13> AGP_SBA[0..7] R6 C8 GMCH_CRT_G <21> R5 DVOBD1 GAD2
    DVOB_D3 DVOBD2/(NC) GREEN
    R4 D8 R6 DVOBD2 GAD5
    DVOB_D4 DVOBD3/(NC) GREEN#
    P6 A7 GMCH_CRT_R <21> R4 DVOBD3 GAD4
    DVOB_D5 DVOBD4/(NC) RED CLK_MCH_48M CLK_SSC_66M
    P5 A8 P6 DVOBD4 GAD7
    DVOB_D6 DVOBD5/(NC) RED#
    N5 H10 GMCH_CRT_HSYNC <21> P5 DVOBD5 GAD6
    DVOBD6/(NC) HSYNC

    2
    DVOB_D7 P2 J9 N5 DVOBD6 GAD8

    DAC
    DVOBD7/(NC) VSYNC GMCH_CRT_VSYNC <21>

    2
    DVOB_D8 N2 E8 REFSET @ R142 P2 DVOBD7 GCBE#0
    DVOB_D9 DVOBD8/(NC) REFSET
    D N3 B6 GMCH_CRT_CLK <21>
    R418 33_0402_5% N2 DVOBD8 GAD10
    DVOBD9/(NC) DDCACLK D

    2
    DVOB_D10 M1 G9 33_0402_5% @ N3 DVOBD9 GAD9
    DVOBD10/(NC) DDCADATA GMCH_CRT_DATA <21>
    CLK_MCH_66M DVOB_D11 M5 R420 M1 DVOBD10 GAD12
    DVOBD11/(NC)

    1
    127_0603_1% M5 DVOBD11 GAD11

    1
    1

    AGP_ADSTB0 P3 2 2 P3 DVOBCLK GADSTB0


    <13> AGP_ADSTB0 DVOBCLK/(NC)
    @ AGP_ADSTB0# P4 G14 C491 C107 P4 DVOBCLK# GADSTB0#
    <13> AGP_ADSTB0# DVOBCLK#/(NC) IYAM0 GMCH_TXOUT0- <20>

    1
    R469 AGP_AD0 T6 E15 @ @ T6 DVOBHSYNC GAD0
    <13> AGP_AD0 DVOBHSYNC/(NC) IYAM1 GMCH_TXOUT1- <20>
    33_0402_5% AGP_AD1 T5 C15 22P_0402_50V8J 22P_0402_50V8J T5 DVOBVSYNC GAD1
    <13> AGP_AD1 DVOBVSYNC/(NC) IYAM2 GMCH_TXOUT2- <20> 1 1
    AGP_CBE#1 L2 C13 L2 DVOBBLANK GCBE#1
    <13> AGP_CBE#1 DVOBBLANK#/(NC) IYAM3
    2

    AGP_AD14 M2 F14 M2 DVOBFLDSTL GAD14


    <13> AGP_AD14 DVOBFLDSTL/(NC) IYAP0 GMCH_TXOUT0+ <20>
    1 E14 GMCH_TXOUT1+ <20> G2 DVOBCINTR# GAD30
    AGP_AD30 IYAP1
    @
    <13> AGP_AD30 G2 C14 GMCH_TXOUT2+ <20> M3 DVOBCCLKINT GAD13
    DVOBC_CLKINT M3 DVOBCINTR# IYAP2
    C565
    <13,19> DVOBC_CLKINT B13 J3 DVOCCLK GADSTB1
    DVOBCCLKINT IYAP3
    22P_0402_50V8J H12 GMCH_TZOUT0- <20> J2 DVOCCLK# GADSTB1#
    2 DVOC_CLK IYBM0
    <13,19> DVOC_CLK J3 E12 GMCH_TZOUT1- <20> K6 DVOCHSYNC GAD17
    DVOC_CLK# DVOCCLK IYBM1
    <13,19> DVOC_CLK# J2 C12 GMCH_TZOUT2- <20> L5 DVOCVSYNC GAD16
    DVOC_HSYNC DVOCCLK# IYBM2
    K6 G11 L3 DVOCBLANK GAD18
    <13,19> DVOC_HSYNC DVOC_VSYNC DVOCHSYNC IYBM3
    L5 G12 GMCH_TZOUT0+ <20> H5 DVOCFLDSTL GAD31
    <13,19> DVOC_VSYNC AGP_AD18 DVOCVSYNC IYBP0
    <13> AGP_AD18 L3 E11 GMCH_TZOUT1+ <20> K7 MI2CCLK GIRDY#
    AGP_AD31 DVOCBLANK# IYBP1
    <13> AGP_AD31 H5 C11 GMCH_TZOUT2+ <20> N6 MI2CDATA GDEVSEL#
    DVOCFLDSTL IYBP2
    G10 N7 MDVICLK GTRDY#
    IYBP3
    D14 GMCH_TXCLK- <20> M6 MDVIDATA GFRAME#
    MI2CCLK ICLKAM
    <13,19> MI2CCLK K7 E13 GMCH_TXCLK+ <20> P7 MDDCCLK GSTOP#
    MI2CDATA MI2CCLK ICLKAP
    N6 E10 T7 MDDCDATA GAD15

    DVO
    LVDS
    <13,19> MI2CDATA MI2CDATA ICLKBM GMCH_TZCLK- <20>
    MDVICLK N7 F10 K5 DVOCD0 GAD19
    <13> MDVICLK MDVICLK ICLKBP GMCH_TZCLK+ <20>
    MDVIDATA M6 K1 DVOCD1 GAD20
    <13> MDVIDATA MDVIDATA
    2 1 AGP_AD14 <13> MDDCCLK
    MDDCCLK P7 MDDCCLK DDCPCLK B4 GMCH_LCD_CLK
    GMCH_LCD_CLK <20> K3 DVOCD2 GAD21
    R451 100K_0402_5% MDDCDATA T7 C5 GMCH_LCD_DATA K2 DVOCD3 GAD22
    <13> MDDCDATA MDDCDATA DDCPDATA GMCH_LCD_DATA <20>
    1 2 AGP_AD31 J6 DVOCD4 GAD23
    R434 100K_0402_5% G8 J5 DVOCD5 GCBE#3
    PANELBKLTCTL
    1 2 DVOBC_CLKINT DVOC_D0 K5 DVOCD0 PANELBKLTEN F8 GMCH_ENBKL <34> H2 DVOCD6 GAD25
    R445 100K_0402_5% DVOC_D1 K1 A5 H1 DVOCD7 GAD24
    C DVOCD1 PANELVDDEN GMCH_ENVDD <20> C
    DVOC_D2 K3 1 2 H3 DVOCD8 GAD27
    DVOC_D3 DVOCD2
    K2 D12 C507 22P_0402_50V8J H4 DVOCD9 GAD26
    DVOC_D4 DVOCD3 LVREFH
    J6 F12 H6 DVOCD10 GAD29
    DVOCD4 LVREFL
    +1.5VS 2 1 AGP_AD30 DVOC_D5 J5 DVOCD5
    G3 DVOCD11 GAD28
    R437 100K_0402_5% DVOC_D6 H2 B12 +3VS E5 ADDID0 GSBA0
    DVOC_D7 DVOCD6 LVBG LIBG
    H1 A10 2 1 F5 ADDID1 GSBA1
    DVOC_D8 DVOCD7 LIBG
    H3 R409 1.5K_0603_1% E3 ADDID2 GSBA2
    DVOCD8

    2
    DVOC_D9 H4 E2 ADDID3 GSBA3
    DVOC_D10 DVOCD9
    H6 R421 G5 ADDID4 GSBA4
    DVOC_D11 DVOCD10 CLK_MCH_48M
    G3 B7 CLK_MCH_48M <12> 510_0402_5% F4 ADDID5 GSBA5
    DVOCD11 DREFCLK
    <13,23> AGP_BUSY# 1 2 AGPBUSY# DREFSSCLK B17 CLK_SSC_66M
    CLK_SSC_66M <12>
    @ G6 ADDID6 GSBA6
    R422 UMA@ 0_0402_5% F6 ADDID7 GSBA7

    CLKS
    LCLKCTLA H9

    1
    C6 LCLKCTLB L7 DVODETECT GPAR
    LCLKCTLB
    reserved for DVO mode unpoped for 1.05V FSB D5 DPMS GPIPE#
    AGP_SBA0 E5 F2 RVSD1 GSBSTB
    AGP_SBA1 ADDID0
    F5 LCLKCTLB: High for P4, NC for Banias F3 RVSD2 GSBSTB#
    AGP_SBA2 ADDID1
    +1.5VS E3 AA22 H_DPWR# <4> B2 RVSD3 GGNT#
    AGP_SBA3 ADDID2 DPWR#/(NC)
    E2 Y23 H_DPSLP# <4,22> B3 RVSD4 GREQ#
    AGP_SBA4 ADDID3 DPSLP# PCIRST#
    G5 AD28 PCIRST# <13,19,22,25,27,28,30> C2 RVSD5 GST2
    ADDID4 RSTIN#
    2

    AGP_SBA5 C3 GST1 GST1


    MISC

    F4 ADDID5
    R419 AGP_SBA6 G6 J11 C4 GST0 GST0
    ADDID6 PWROK VGATE <12,23,45>
    10K_0603_5% 1 2 AGP_SBA7 F6 D2 RVSD8 GWBF#
    ADDID7 EXTTS
    UMA@ R426 1K_0402_5% D6 1 2 +3VS D3 RVSD9 GRBF#
    AGP_PAR EXTTS0
    <13> AGP_PAR L7 AJ1 R423 10K_0402_5% L4 RVSD11 GCBE#2
    DVODETECT MCHDETECTVSS
    1

    Q35 D5
    BSN20_SOT23 +AGP_VREF DPMS
    D +AGP_VREF F1 GVREF
    1

    AGPBUSY# F7
    DVORCOMP AGPBUSY#
    <23> RTCCLK 2 D1 DVORCOMP NC0 B1
    CLK_MCH_66M
    G
    UMA@ S
    <12> CLK_MCH_66M
    W=10mil
    Y3 GCLKIN NC1
    NC2
    AH1
    A2 Isolating AGP singals Starp Pin:
    3

    AA5 RVSD0 NC3 AJ2


    (For M11P) (For UMA)
    2

    B AGP_SBSTB F2 A28 B
    <13> AGP_SBSTB RVSD1 NC4 +5VS
    reserved for DVO mode AGP_SBSTB# F3 AJ28 *
    <13> AGP_SBSTB# RVSD2 NC5
    R432 AGP_GNT# B2 A29 U39 M11@ +1.5VS
    <13> AGP_GNT# RVSD3 NC6
    NC

    40.2_0603_1% AGP_REQ# B3 B29 PCIRST# 1 14 *


    <13> AGP_REQ# RVSD4 NC7 OE1# VCC
    AGP_ST2 C2 AH29 AGP_ST0 2 13 PCIRST# AGP_ST0 R413 1 UMA@ 2 1K_0402_5%
    <13> AGP_ST2 RVSD5 NC8 1A OE4#
    1

    AGP_ST1 C3 AJ29 GST0 3 12 AGP_ST1 *


    <13> AGP_ST1 GST[1] NC9 1B 4A
    AGP_ST0 C4 AA9 4 11 GST1 AGP_ST1 R405 1 UMA@ 2 1K_0402_5%
    <13> AGP_ST0 GST[0] NC10 OE2# 4B
    AGP_WBF# D2 AJ4 AGP_ST2 5 10 *
    <13> AGP_WBF# RVSD8 NC11 2A OE3#
    AGP_RBF# D3 GST2 6 9 AGP_PAR AGP_ST2 R430 1 UMA@ 2 1K_0402_5%
    <13> AGP_RBF# RVSD9 2B 3A
    D7 7 8 GPAR *
    AGP_CBE#2 RVSD10 GND 3B R412 1 @
    <13> AGP_CBE#2 L4 RVSD11 2 1K_0402_5%
    FST3125MTCX_SSOP14 +1.5VS
    RG82855GME_uFCBGA732 AGP_PAR R411 1 UMA@ 2 1K_0402_5%
    GST0 1 2
    R414 M11@ 1K_0402_5%
    GST1 1 2
    +1.5VS R406 M11@ 1K_0402_5%
    I2C BUS PULL UP +1.5VS DVO/AGP REF Voltage GST2 1 2
    DVODETECT(AGP_PAR):
    R415 M11@ 1K_0402_5% HIGH for AGP, LOW for DVO
    2

    RP50 1 2
    MDVICLK 1 8 R439 R407 M11@ 1K_0402_5%
    MDDCCLK 2 7 1K_0603_1% GPAR 2 1
    MDVIDATA 3 6 R401 @ 1K_0402_5%
    MDDCDATA 4 5 +AGP_VREF +AGP_VREF
    2 1

    2.2K_1206_8P4R_5% 2
    R442
    MI2CCLK C533
    2
    R429
    1
    2.2K_0402_5% 0.1U_0402_16V4Z Starp pin list
    MI2CDATA 1K_0603_1% 1
    2 1
    1

    R441 2.2K_0402_5%
    A
    ST2 ST1 ST0 PSB/Mem/GFX A
    0 0 0 400 / 266 / 200
    0 0 1 400 / 200 / 200
    0 1 0 400 / 200 / 133
    1 1 1 400 / 333 / 250 * Compal Electronics, Inc.
    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    INTEL 855GME-AGP&LVDS(2/4)
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 7 of 47


    5 4 3 2 1
    5 4 3 2 1

    DDR_SDQ[0..63] DDR_SMA[6..12] U14D


    DDR_SDQ[0..63] <10> DDR_SMA[6..12] <10,11>
    C1 VSS0 VSS91 R17
    DDR_SDQS[0..7] DDR_SDM[0..7] G1 U17
    DDR_SDQS[0..7] <10> DDR_SDM[0..7] <10> VSS1 VSS92
    L1 VSS2 VSS93 AB17
    U1 VSS3 VSS94 AC17
    AA1 VSS4 VSS95 F18
    U14C AE1 VSS5 VSS96 J18
    R2 VSS6 VSS97 AA18
    AG3 VSS7 VSS98 AG18

    DDR_SMA0
    Montara-GM(L) DDR_SDQ0
    AJ3
    D4
    VSS8
    VSS9
    VSS99
    VSS100
    A19
    D19
    <10,11> DDR_SMA0 AC18 SMA0 SDQ0 AF2 G4 VSS10 VSS101 H19
    DDR_SMA1 AD14 AE3 DDR_SDQ1 K4 AB19
    <10,11> DDR_SMA1 SMA1 SDQ1 VSS11 VSS102
    DDR_SMA2 AD13 AF4 DDR_SDQ2 N4 AE19
    D <10,11> DDR_SMA2 SMA2 SDQ2 VSS12 VSS103 D
    DDR_SMA3 AD17 AH2 DDR_SDQ3 T4 F20
    <10,11> DDR_SMA3 SMA3 SDQ3 VSS13 VSS105
    DDR_SMA4 AD11 AD3 DDR_SDQ4 W4 J20
    <10,11> DDR_SMA4 SMA4 SDQ4 VSS14 VSS106
    DDR_SMA5 AC13 AE2 DDR_SDQ5 AA4 AA20
    <10,11> DDR_SMA5 SMA5 SDQ5 VSS15 VSS107
    DDR_SMA6 AD8 AG4 DDR_SDQ6 AC4 AC20
    DDR_SMA7 SMA6 SDQ6 DDR_SDQ7 VSS16 VSS108
    AD7 SMA7 SDQ7 AH3 AE4 VSS17 VSS109 A21
    DDR_SMA8 AC6 AD6 DDR_SDQ8 B5 D21
    DDR_SMA9 SMA8 SDQ8 DDR_SDQ9 VSS18 VSS110
    AC5 SMA9 SDQ9 AG5 U5 VSS19 VSS111 H21
    DDR_SMA10 AC19 AG7 DDR_SDQ10 Y5 M21
    DDR_SMA11 SMA10 SDQ10 DDR_SDQ11 VSS20 VSS112
    AD5 SMA11 SDQ11 AE8 Y6 VSS21 VSS113 P21
    DDR_SMA12 AB5 AF5 DDR_SDQ12 AG6 T21
    SMA12 SDQ12 DDR_SDQ13 VSS22 VSS114
    SDQ13 AH4 C7 VSS23 VSS115 V21
    AF7 DDR_SDQ14 E7 Y21
    SDQ14 VSS24 VSS116

    Montara-GM(L)
    AH6 DDR_SDQ15 G7 AA21
    SDQ15 VSS25 VSS117
    DDR_SDQS0
    DDR_SDQS1
    AG2
    AH5
    SDQS0
    SDQS1
    MEMORY SDQ16
    SDQ17
    AF8
    AG8
    DDR_SDQ16
    DDR_SDQ17
    J7
    M7
    VSS26
    VSS27
    VSS118
    VSS119
    AB21
    AG21
    DDR_SDQS2 AH8 AH9 DDR_SDQ18 R7 B24
    DDR_SDQS3 SDQS2 SDQ18 DDR_SDQ19 VSS28 VSS120
    AE12 SDQS3 SDQ19 AG10 AA7 VSS29 VSS121 F22
    DDR_SDQS4 AH17 AH7 DDR_SDQ20 AE7 J22
    DDR_SDQS5 SDQS4 SDQ20 DDR_SDQ21 VSS30 VSS122
    AE21 SDQS5 SDQ21 AD9 AJ7 VSS31 VSS123 L22
    DDR_SDQS6 AH24 AF10 DDR_SDQ22 H8 N22
    DDR_SDQS7 SDQS6 SDQ22 DDR_SDQ23 VSS32 VSS124
    AH27 SDQS7 SDQ23 AE11 K8 VSS33 VSS125 R22
    AD15 AH10 DDR_SDQ24 P8 U22
    SDQS8 SDQ24 DDR_SDQ25 VSS34 VSS126
    SDQ25 AH11 T8 VSS35 VSS127 W22
    AG13 DDR_SDQ26 V8 AE22
    DDR_SWE# SDQ26 DDR_SDQ27 VSS36 VSS128
    <10,11> DDR_SWE# AD25 SWE# SDQ27 AF14 Y8 VSS37 VSS129 A23
    DDR_SRAS# AC21 AG11 DDR_SDQ28 AC8 D23
    <10,11> DDR_SRAS# SRAS# SDQ28 VSS38 VSS130
    DDR_SCAS# AC24 AD12 DDR_SDQ29 E9 AA23
    <10,11> DDR_SCAS# SCAS# SDQ29 VSS39 VSS131
    AF13 DDR_SDQ30 L9 AC23
    SDQ30 DDR_SDQ31 VSS40 VSS132
    SDQ31 AH13 N9 VSS41 VSS133 AJ23
    AB2 AH16 DDR_SDQ32 R9 F24
    <10> DDR_CLK0 SCK0 SDQ32 VSS42 VSS134
    AA2 AG17 DDR_SDQ33 U9 H24
    C <10> DDR_CLK0# SCK0# SDQ33 VSS43 VSS135 C
    AC26 AF19 DDR_SDQ34 W9 K24
    <10> DDR_CLK1 SCK1 SDQ34 VSS44 VSS136
    AB25 AE20 DDR_SDQ35 AB9 M24
    <10> DDR_CLK1# SCK1# SDQ35 VSS45 VSS137
    AC3 AD18 DDR_SDQ36 AG9 P24
    SCK2 SDQ36 DDR_SDQ37 VSS46 VSS138
    AD4 SCK2# SDQ37 AE18 C10 VSS47 VSS139 T24
    AC2 AH18 DDR_SDQ38 J10 V24
    <10> DDR_CLK3 SCK3 SDQ38 VSS48 VSS140
    AD2 AG19 DDR_SDQ39 AA10 AA24
    <10> DDR_CLK3# SCK3# SDQ39 VSS49 VSS141
    AB23 AH20 DDR_SDQ40 AE10 AG24
    <10> DDR_CLK4 SCK4 SDQ40 VSS50 VSS142
    AB24 AG20 DDR_SDQ41 D11 A25
    <10> DDR_CLK4# SCK4# SDQ41 VSS51 VSS143
    AA3 AF22 DDR_SDQ42 F11 D25
    SCK5 SDQ42 DDR_SDQ43 VSS52 VSS144
    AB4 SCK5# SDQ43 AH22 H11 VSS53 VSS145 AA25
    AF20 DDR_SDQ44 AB11 AE25
    SDQ44 DDR_SDQ45 VSS54 VSS146
    SDQ45 AH19 AC11 VSS55 VSS147 G26
    AC7 AH21 DDR_SDQ46 AJ11 J26
    <10,11> DDR_CKE0 SCKE0 SDQ46 VSS56 VSS148
    AB7 AG22 DDR_SDQ47 J12 L26
    <10,11> DDR_CKE1 SCKE1 SDQ47 VSS57 VSS149
    AC9 AE23 DDR_SDQ48 AA12 N26
    <10,11> DDR_CKE2 SCKE2 SDQ48 VSS58 VSS150
    AC10 AH23 DDR_SDQ49 AG12 R26
    <10,11> DDR_CKE3 SCKE3 SDQ49 VSS59 VSS151
    AD23 AE24 DDR_SDQ50 A13 U26
    <10,11> DDR_SCS#0 SCS#0 SDQ50 VSS60 VSS152
    AD26 AH25 DDR_SDQ51 D13 W26
    <10,11> DDR_SCS#1 SCS#1 SDQ51 VSS61 VSS153
    AC22 AG23 DDR_SDQ52 F13 AB26
    <10,11> DDR_SCS#2 SCS#2 SDQ52 VSS62 VSS154
    DDR_SDQ53
    DDR REF & SWING VOLTAGE <10,11> DDR_SCS#3 AC25 SCS#3 SDQ53 AF23
    AF25 DDR_SDQ54
    H13
    N13
    VSS63 VSS155 A27
    F27
    SDQ54 DDR_SDQ55 VSS64 VSS156
    SDQ55 AG25 R13 VSS65 VSS157 AC27
    +2.5V DDR_SBS0 AD22 AH26 DDR_SDQ56 U13 AG27
    <10,11> DDR_SBS0 SBA0 SDQ56 VSS66 VSS158
    DDR_SBS1 AD20 AE26 DDR_SDQ57 AB13 AJ27
    <10,11> DDR_SBS1 SBA1 SDQ57 VSS67 VSS159
    AG28 DDR_SDQ58 AE13 AC28
    SDQ58 DDR_SDQ59 VSS68 VSS160
    SDQ59 AF28 J14 VSS69 VSS161 AE28
    1

    2 DDR_SDM0 AE5 AG26 DDR_SDQ60 P14 C29


    C577 R482 DDR_SDM1 SDM0 SDQ60 DDR_SDQ61 VSS70 VSS162
    AE6 SDM1 SDQ61 AF26 T14 VSS71 VSS163 E29
    60.4_0603_1% DDR_SDM2 AE9 AE27 DDR_SDQ62 AA14 G29
    0.1U_0402_16V4Z DDR_SDM3 SDM2 SDQ62 DDR_SDQ63 VSS72 VSS164
    AH12 SDM3 SDQ63 AD27 AC14 VSS73 VSS165 J29
    1 DDR_SDM4
    W=10mil AD19 SDM4 D15 VSS74 VSS166 L29
    2

    B SMRCOMP DDR_SDM5 AD21 H15 N29 B


    DDR_SDM6 SDM5 VSS75 VSS167
    (1.25V) AD24 SDM6 N15 VSS76 VSS168 U29
    1

    DDR_SDM7 AH28 AG14 R15 W29


    R478 SDM7 SDQ64 VSS77 VSS169
    AH15 SDM8 SDQ65 AE14 U15 VSS78 VSS170 AA29
    60.4_0603_1% AE17 AB15 AJ10
    SDQ66 +2.5V VSS79 VSS171
    SDQ67 AG16 AG15 VSS80 VSS172 AJ12
    DDR_SMA_B1 AD16 AH14 F16 AJ18
    <10,11> DDR_SMA_B1 SMA_B1 SDQ68 VSS81 VSS173
    2

    DDR_SMA_B2 AC12 AE15 J16 AJ20


    <10,11> DDR_SMA_B2 SMA_B2 SDQ69 VSS82 VSS174
    DDR_SMA_B4 AF11 AF16 P16 C22
    <10,11> DDR_SMA_B4 SMA_B4 SDQ70 VSS83 VSS176

    1
    DDR_SMA_B5 AD10 AF17 2 T16 D28
    <10,11> DDR_SMA_B5 SMA_B5 SDQ71 VSS84 VSS177
    +2.5V R166 AA16 E28
    C142 75_0603_1% VSS85 VSS178
    AC15 RCVENOUT# AE16 VSS86 VSS179 L6
    AC16 0.1U_0402_16V4Z A17 RG82855GME_uFCBGA732 T9
    RCVENIN# 1 VSS87 VSS180
    1

    D17 VSS88 VSS181 AJ26

    2
    R174 SMRCOMP AB1 AJ24 SMVREF0 H17
    SMRCOMP SMVREF0 VSS89
    604_0603_1% W=20mil N17 VSS90

    1
    W=10mil SMVSWINGL AJ22 2 2
    SMVSWINGH SMVSWINGL R168
    AJ19 SMVSWINGH
    2

    SMVSWINGL C148 C149 75_0603_1%


    (0.497V) RG82855GME_uFCBGA732 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    1 1
    1

    2
    R175 2
    150_0603_1% C154
    1
    0.1U_0402_16V4Z
    2

    +2.5V

    A A
    1

    R181
    150_0603_1%
    W=10mil
    2

    SMVSWINGH
    (2.002V) Compal Electronics, Inc.
    1

    2
    R185 Title

    604_0603_1%
    C171
    0.1U_0402_16V4Z
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    INTEL 855GME DDR(3/4)
    1 Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    2

    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 8 of 47


    5 4 3 2 1
    5 4 3 2 1

    U14E
    +1.35VS +VCCP +1.35VS

    J15
    Montara-GM(L) G15
    (1.8A) For VCC
    VCC0 VTTLF0
    P13 VCC1 VTTLF1 H16
    T13 VCC2 VTTLF2 H18 1
    N14 J19 C569 1 C539 2 2 2 2 2 2 2 2
    VCC3 VTTLF3 + C509 C496 C527 C538 C517 C524 C512 C553
    R14 VCC4 VTTLF4 H20
    U14 VCC5 VTTLF5 L21
    P15 N21 150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VCC6 VTTLF6 2 2
    10U_0805_10V4Z 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z
    T15 VCC7 VTTLF7 R21
    AA15 VCC8 VTTLF8 U21
    N16 VCC9 VTTLF9 H22
    D R16 VCC10 VTTLF10 M22 D
    U16 VCC11 VTTLF11 P22
    P17 VCC12 VTTLF12 T22
    T17 VCC13 VTTLF13 V22
    AA17 Y29 +1.35VS +1.35VS_PLLA +1.35VS +1.35VS_PLLB +1.35VS
    VCC14 VTTLF14
    AA19 VCC15 VTTLF15 K29 W=20mil (90mA) For VCCHL W=20mil (0.4A) W=20mil (0.4A)
    W21 VCC16 VTTLF16 F29 1 2 1 2
    H14 AB29 R159 1_0805_5% UMA@ R143 1_0805_5% UMA@
    +1.35VS VCC17 VTTLF17
    VTTLF18 A26 1 1
    VTTLF19 A20 1 2 2 2 2
    +
    2 For VCCADPLLA +
    2 For VCCADPLLB
    V1 A18 C526 C547 C544 C564 C92 C116 C115 C111 C112
    VCCHL0 VTTLF20
    Y1 VCCHL1
    W5 VCCHL2 VTTHF0 A22 2 1 C103 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z UMA@ 220U_D2_4VM_R12
    2 1 1 1 1 2 1 2 1
    U6 VCCHL3 VTTHF1 A24 2 1 C96 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z UMA@ 0.1U_0402_16V4Z UMA@
    U8 VCCHL4 VTTHF2 H29 2 1 C476 0.1U_0402_16V4Z 220U_D2_4VM_R12 UMA@
    W8 VCCHL5 VTTHF3 M29 2 1 C481 0.1U_0402_16V4Z
    V7 VCCHL6 VTTHF4 V29 2 1 C489 0.1U_0402_16V4Z Close to ball D29, Y2
    V9 VCCHL7
    VCCSM0 AC1
    D29 VCCAHPLL VCCSM1 AG1
    +1.35VS_PLLA Y2 AB3 +1.5VS +1.5VS +1.5VS
    +1.35VS_PLLB VCCAGPLL VCCSM2
    VCCSM3 AF3 W=40mil (90mA) For VCCDVO W=20mil (70mA) W=20mil (90mA)
    POWER

    A6 VCCADPLLA VCCSM4 Y4
    B16 AJ5 +2.5V For VCCADAC For VCCALVDS
    VCCADPLLB VCCSM5
    VCCSM6 AA6 1
    +1.5VS AB6
    VCCSM7 1 2 2 2 2 2 2
    E1 AF6 C550 + C531 C532 C500 C114
    VCCDVO_0 VCCSM8 C492 C513 C551
    J1 VCCDVO_1 VCCSM9 Y7
    N1 AA8 10U_0805_10V4Z 0.1U_0402_16V4Z UMA@ 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.01U_0402_16V7K
    VCCDVO_2 VCCSM10 2
    150U_D2_6.3VM 2 1
    0.1U_0402_16V4Z 1 1 1 UMA@ UMA@ 1 1 UMA@
    E4 VCCDVO_3 VCCSM11 AB8
    J4 Y9 0.1U_0402_16V4Z
    VCCDVO_4 VCCSM12
    M4 VCCDVO_5 VCCSM13 AF9
    C C
    E6 VCCDVO_6 VCCSM14 AJ9
    H7 VCCDVO_7 VCCSM15 AB10
    J8 VCCDVO_8 VCCSM16 AA11
    L8 VCCDVO_9 VCCSM17 AB12
    M8 AF12 +2.5V
    VCCDVO_10 VCCSM18
    N8 VCCDVO_11 VCCSM19 AA13
    +1.5VS
    W=20mil (90mA) For VCCTXLVDS
    R8 VCCDVO_12 VCCSM20 AJ13
    K9 VCCDVO_13 VCCSM21 AB14 W=20mil (70mA)
    M9 VCCDVO_14 VCCSM22 AF15
    +1.5VS
    P9 VCCDVO_15 VCCSM23 AB16 For VCCDLVDS 1 2 2 2
    AJ17 C542 C523 C545 C515
    VCCSM24
    VCCSM25 AB18 1 2
    A9 AF18 C503 0.1U_0402_16V4Z UMA@ 0.1U_0402_16V4Z
    VCCADAC0 VCCSM26 C529 UMA@ 2 UMA@ 1 1 1 UMA@
    B9 VCCADAC1 VCCSM27 AB20
    B8 AF21 22U_1206_16V4Z_V1 22U_1206_16V4Z_V1 0.1U_0402_16V4Z
    +1.5VS VSSADAC VCCSM28 2 1
    0.1U_0402_16V4Z
    VCCSM29 AJ21
    VCCSM30 AB22
    A11
    B11
    VCCALVDS
    VSSALVDS
    VCCSM31
    VCCSM32
    AF24
    AJ25 reserved for GMCH, no need when use external VGA
    +1.5VS AF27
    VCCSM33
    VCCSM34 AC29
    G13 VCCDLVDS0 VCCSM35 AF29
    B14 VCCDLVDS1 VCCSM36 AG29
    J13 +2.5V
    VCCDLVDS2
    B15 VCCDLVDS3 (1.9A)
    +2.5V
    +2.5V_QSM
    F9 VCCTXLVDS0 1
    B10 VCCTXLVDS1 VCCQSM0 AJ6 2 2 2 2 2 2 2 2 2 2 2 2
    D10 AJ8 + C558 C581 C573 C546 C566 C562 C534 C528 C508 C563 C543 C510
    +3VS VCCTXLVDS2 VCCQSM1 +1.35VS_ASM C189
    A12 VCCTXLVDS3
    B 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
    2
    150U_D2_6.3VM 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z
    VCCASM0 AD1
    A3 VCCGPIO_0 VCCASM1 AF1
    A4 VCCGPIO_1

    +3VS +VCCP +2.5V_QSM +2.5V +1.35VS_ASM +1.35VS


    For VCCGPIO (72mA) W=20mil W=20mil For VCCASM
    RG82855GME_uFCBGA732 1 2 1 2
    R483 0_0603_5% R506 0_0603_5%
    1 For VCCQSM
    1 2 2 2 2 2 1 1 1 2
    C495 + C499 C493 C497
    C501 C505 C584 C575 C591 C582 C590
    10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
    2 1
    0.1U_0402_16V4Z 2
    150U_D2_6.3VM 1 1
    0.1U_0402_16V4Z 1 1
    0.1U_0402_16V4Z 2 2
    10U_0805_10V4Z 2 0.1U_0402_16V4Z
    1
    R499 1 2 1_0603_1% 10U_0805_10V4Z

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    INTEL 855GME GMCH(4/4)
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 9 of 47


    5 4 3 2 1
    5 4 3 2 1

    1 R589 2 10_0804_8P4R_5% RP44


    +2.5V
    75_0603_1% DDR_SDQ62 4 5 DDR_DQ62 DDR_DQ60 8 1 DDR_SDQ60
    DDR_SDQ56 3 6 DDR_DQ56 DDR_DQ61 7 2 DDR_SDQ61
    +2.5V +2.5V +1.25VS_SDREF DDR_SDQS7 2 7 DDR_DQS7 DDR_DM7 6 3 DDR_SDM7
    JP24 DDR_SDQ58 1 8 DDR_DQ58 DDR_DQ57 5 4 DDR_SDQ57
    1 VREF VREF 2
    3 4 RP45 10_0804_8P4R_5%
    VSS VSS 10_0804_8P4R_5%

    1
    DDR_DQ0 DDR_DQ2 RP46

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    5 DQ0 DQ4 6 1 1
    DDR_DQ3 7 8 DDR_DQ7 C654 C655 R580 DDR_SDQ63 4 5 DDR_DQ63 DDR_DQ59 8 1 DDR_SDQ59
    DQ1 DQ5 DDR_SDQ50
    9 VDD VDD 10 75_0603_1% 3 6 DDR_DQ50 DDR_DQ51 7 2 DDR_SDQ51
    DDR_DQS0 11 12 DDR_DM0 DDR_SDQ55 2 7 DDR_DQ55 DDR_DQ54 6 3 DDR_SDQ54
    DDR_DQ5 DQS0 DM0 DDR_DQ4 2 2 DDR_SDQS6
    13 DQ2 DQ6 14 1 8 DDR_DQS6 DDR_DM6 5 4 DDR_SDM6

    2
    15 VSS VSS 16
    DDR_DQ1 17 18 DDR_DQ6 RP47 10_0804_8P4R_5%
    DDR_DQ8 DQ3 DQ7 DDR_DQ9 10_0804_8P4R_5% RP48
    D 19 DQ8 DQ12 20 D
    21 22 DDR_SDQ49 4 5 DDR_DQ49 DDR_DQ53 8 1 DDR_SDQ53
    DDR_DQ13 VDD VDD DDR_DQ12 DDR_SDQ52
    23 DQ9 DQ13 24 3 6 DDR_DQ52 DDR_DQ48 7 2 DDR_SDQ48
    DDR_DQS1 25 26 DDR_DM1 DDR_SDQ43 2 7 DDR_DQ43 DDR_DQ46 6 3 DDR_SDQ46
    DQS1 DM1 DDR_SDQ42
    27 VSS VSS 28 1 8 DDR_DQ42 DDR_DQ47 5 4 DDR_SDQ47
    DDR_DQ14 29 30 DDR_DQ11
    DDR_DQ15 DQ10 DQ14 DDR_DQ10 RP49 10_0804_8P4R_5%
    31 DQ11 DQ15 32
    33 34 10_0804_8P4R_5% RP51
    VDD VDD DDR_SDQS5
    <8> DDR_CLK0 A35 CK0_A VDD 36 4 5 DDR_DQS5 DDR_DM5 8 1 DDR_SDM5
    A37 38 DDR_SDQ40 3 6 DDR_DQ40 DDR_DQ45 7 2 DDR_SDQ45
    <8> DDR_CLK0# CK0#_A VSS
    39 40 DDR_SDQ44 2 7 DDR_DQ44 DDR_DQ41 6 3 DDR_SDQ41
    VSS VSS DDR_SDQ34 1 8 DDR_DQ34 DDR_DQ35 5 4 DDR_SDQ35

    DDR_DQ16 41 42 DDR_DQ17 RP52 10_0804_8P4R_5%


    DDR_DQ20 DQ16 DQ20 DDR_DQ21 10_0804_8P4R_5% RP53
    43 DQ17 DQ21 44
    45 46 DDR_SDQ38 4 5 DDR_DQ38 DDR_DQ39 8 1 DDR_SDQ39
    DDR_DQS2 VDD VDD DDR_DM2 DDR_SDQS4
    47 DQS2 DM2 48 3 6 DDR_DQS4 DDR_DM4 7 2 DDR_SDM4
    DDR_DQ22 49 50 DDR_DQ19 DDR_SDQ37 2 7 DDR_DQ37 DDR_DQ33 6 3 DDR_SDQ33
    DQ18 DQ22 DDR_SDQ32
    51 VSS VSS 52 1 8 DDR_DQ32 DDR_DQ36 5 4 DDR_SDQ36
    DDR_DQ18 53 54 DDR_DQ23
    DDR_DQ24 DQ19 DQ23 DDR_DQ28 RP54 10_0804_8P4R_5%
    55 DQ24 DQ28 56
    57 VDD VDD 58
    DDR_DQ25 59 60 DDR_DQ29
    DDR_DQS3 DQ25 DQ29 DDR_DM3
    61 DQS3 DM3 62
    63 VSS VSS 64
    DDR_DQ26 65 66 DDR_DQ30 RP16 RP55
    DDR_DQ27 DQ26 DQ30 DDR_DQ31 DDR_SWE# DDR_F_SWE# DDR_SCAS#
    67 DQ27 DQ31 68 1 8 1 8 DDR_F_SCAS#
    69 70 DDR_SMA10 2 7 DDR_F_SMA10 DDR_SRAS# 2 7 DDR_F_SRAS#
    VDD VDD DDR_SBS1 DDR_F_SBS1
    3 6 3 6
    DDR_SBS0 4 5 DDR_F_SBS0 DDR_SMA0 4 5 DDR_F_SMA0

    85 86 10_0804_8P4R_5% 10_0804_8P4R_5%
    C DU DU/RESET# C
    87 VSS VSS 88
    A89 CK2_A VSS 90
    A91 CK2#_A VDD 92
    93 VDD VDD 94
    DDR_CKE1 A95 A96 DDR_CKE0 RP19 RP56
    <8,11> DDR_CKE1 CKE1_A CKE0_A DDR_CKE0 <8,11>
    A97 98 DDR_SMA3 1 8 DDR_F_SMA3 DDR_SMA6 1 8 DDR_F_SMA6
    DDR_F_SMA12 DU/A13_A DU/BA2 DDR_F_SMA11 DDR_SMA7 DDR_F_SMA7
    A99 A12_A A11_A A100 2 7 2 7
    DDR_F_SMA9 A101 A102 DDR_F_SMA8 DDR_SMA9 3 6 DDR_F_SMA9 DDR_SMA8 3 6 DDR_F_SMA8
    A9_A A8_A DDR_SMA12 DDR_F_SMA12 DDR_SMA11 DDR_F_SMA11
    103 VSS VSS 104 4 5 4 5
    DDR_F_SMA7 A105 A106 DDR_F_SMA6
    DDR_SMA5 A7_A A6_A DDR_SMA4 10_0804_8P4R_5% 10_0804_8P4R_5%
    <8,11> DDR_SMA5 A107 A5_A A4_A A108 DDR_SMA4 <8,11>
    DDR_F_SMA3 A109 A110 DDR_SMA2
    A3_A A2_A DDR_SMA2 <8,11> 10_0804_8P4R_5%
    DDR_SMA1 A111 A112 DDR_F_SMA0 RP57
    <8,11> DDR_SMA1 A1_A A0_A
    113 114 DDR_SDQ27 4 5 DDR_DQ27 DDR_DQ31 8 1 DDR_SDQ31
    DDR_F_SMA10 VDD VDD DDR_F_SBS1 DDR_SDQ26
    A115 A10/AP_A BA1_A A116 3 6 DDR_DQ26 DDR_DQ30 7 2 DDR_SDQ30
    DDR_F_SBS0 A117 A118 DDR_F_SRAS# DDR_SDQS3 2 7 DDR_DQS3 DDR_DM3 6 3 DDR_SDM3
    DDR_F_SWE# BA0_A RAS#_A DDR_F_SCAS# DDR_SDQ25
    A119 WE#_A CAS#_A A120 1 8 DDR_DQ25 DDR_DQ29 5 4 DDR_SDQ29
    DDR_SCS#0 A121 A122 DDR_SCS#1
    <8,11> DDR_SCS#0 S0#_A S1#_A DDR_SCS#1 <8,11> RP58
    123 124 10_0804_8P4R_5%
    DU DU 10_0804_8P4R_5% RP59
    125 VSS VSS 126
    DDR_DQ32 127 128 DDR_DQ36 DDR_SDQ24 4 5 DDR_DQ24 DDR_DQ28 8 1 DDR_SDQ28
    DDR_DQ37 DQ32 DQ36 DDR_DQ33 DDR_SDQ18
    129 DQ33 DQ37 130 3 6 DDR_DQ18 DDR_DQ23 7 2 DDR_SDQ23
    131 132 DDR_SDQ22 2 7 DDR_DQ22 DDR_DQ19 6 3 DDR_SDQ19
    DDR_DQS4 VDD VDD DDR_DM4 DDR_SDQS2
    133 DQS4 DM4 134 1 8 DDR_DQS2 DDR_DM2 5 4 DDR_SDM2
    DDR_DQ38 135 136 DDR_DQ39
    DQ34 DQ38 RP60 10_0804_8P4R_5%
    137 VSS VSS 138
    DDR_DQ34 139 140 DDR_DQ35
    DDR_DQ44 DQ35 DQ39 DDR_DQ41 DDR_SDQ20
    141 DQ40 DQ44 142 1 2 DDR_DQ20 DDR_DQ21 2 1 DDR_SDQ21
    143 144 R537 10_0402_5% 10_0402_5% R536
    DDR_DQ40 VDD VDD DDR_DQ45 DDR_SDQ16 1
    145 DQ41 DQ45 146 2 DDR_DQ16 DDR_DQ17 2 1 DDR_SDQ17
    DDR_DQS5 147 148 DDR_DM5 R545 10_0402_5% 10_0402_5% R542
    DQS5 DM5 DDR_SDQ15 1
    B 149 VSS VSS 150 2 DDR_DQ15 DDR_DQ10 2 1 DDR_SDQ10 B
    DDR_DQ42 151 152 DDR_DQ47 R559 10_0402_5% 10_0402_5% R558
    DDR_DQ43 DQ42 DQ46 DDR_DQ46 DDR_SDQ14 1
    153 DQ43 DQ47 154 2 DDR_DQ14 DDR_DQ11 2 1 DDR_SDQ11
    155 156 R565 10_0402_5% 10_0402_5% R564
    VDD VDD
    157 VDD CK1#_A A158 DDR_CLK1# <8>
    159 VSS CK1_A A160 DDR_CLK1 <8>
    161 VSS VSS 162
    DDR_DQ52 163 164 DDR_DQ48
    DDR_DQ49 DQ48 DQ52 DDR_DQ53
    165 DQ49 DQ53 166
    167 VDD VDD 168
    DDR_DQS6 169 170 DDR_DM6
    DDR_DQ55 DQS6 DM6 DDR_DQ54
    171 DQ50 DQ54 172
    173 174 10_0804_8P4R_5% RP61
    DDR_DQ50 VSS VSS DDR_DQ51 DDR_SDQS1
    175 DQ51 DQ55 176 4 5 DDR_DQS1 DDR_DM1 8 1 DDR_SDM1
    DDR_DQ63 177 178 DDR_DQ59 DDR_SDQ13 3 6 DDR_DQ13 DDR_DQ12 7 2 DDR_SDQ12
    DQ56 DQ60 DDR_SDQ8
    179 VDD VDD 180 2 7 DDR_DQ8 DDR_DQ9 6 3 DDR_SDQ9
    DDR_DQ58 181 182 DDR_DQ57 DDR_SDQ1 1 8 DDR_DQ1 DDR_DQ6 5 4 DDR_SDQ6
    DDR_DQS7 DQ57 DQ61 DDR_DM7
    183 DQS7 DM7 184
    185 186 RP62 10_0804_8P4R_5%
    DDR_DQ56 VSS VSS DDR_DQ61 10_0804_8P4R_5%
    187 DQ58 DQ62 188
    DDR_DQ62 189 190 DDR_DQ60 DDR_SDQ5 4 5 DDR_DQ5 RP63
    DQ59 DQ63 DDR_SDQS0
    191 VDD VDD 192 3 6 DDR_DQS0 DDR_DQ4 8 1 DDR_SDQ4
    193 A194 DDR_SDQ3 2 7 DDR_DQ3 DDR_DM0 7 2 DDR_SDM0
    <12,22> SMB_DATA SDA SA0_A
    195 A196 DDR_SDQ0 1 8 DDR_DQ0 DDR_DQ7 6 3 DDR_SDQ7
    <12,22> SMB_CLK SCL SA1_A
    197 A198 DDR_DQ2 5 4 DDR_SDQ2
    +3VS VDD_SPD SA2_A RP64
    199 VDD_ID DU 200
    B35 B89 10_0804_8P4R_5%
    <8> DDR_CLK3 CK0_B CK2_B
    <8> DDR_CLK3# B37 CK0#_B CK2#_B B91
    DDR_CKE3 B95 B96 DDR_CKE2
    <8,11> DDR_CKE3 CKE1_B CKE0_B DDR_CKE2 <8,11>
    B97 B100 DDR_SMA11
    DU(A13)_B A11_B DDR_SMA11 <8,11>
    DDR_SMA12 B99 B102 DDR_SMA8
    <8,11> DDR_SMA12 A12_B A8_B DDR_SMA8 <8,11>
    A DDR_SMA9 B101 B106 DDR_SMA6 A
    <8,11> DDR_SMA9 A9_B A6_B DDR_SMA6 <8,11> DDR_SDQ[0..63] DDR_DQ[0..63]
    DDR_SMA7 B105 B108
    <8,11> DDR_SMA7 A7_B A4_B DDR_SMA_B4 <8,11> <8> DDR_SDQ[0..63] DDR_DQ[0..63] <11>
    <8,11> DDR_SMA_B5 B107 A5_B A2_B B110 DDR_SMA_B2 <8,11>
    DDR_SMA3 B109 B112 DDR_SMA0 DDR_SDM[0..7] DDR_DM[0..7]
    <8,11> DDR_SMA3 A3_B A0_B DDR_SMA0 <8,11> <8> DDR_SDM[0..7] DDR_DM[0..7] <11>
    B111 B116 DDR_SBS1
    <8,11> DDR_SMA_B1 A1_B BA1_B DDR_SBS1 <8,11> DDR_SDQS[0..7] DDR_DQS[0..7]
    DDR_SMA10 B115 B118 DDR_SRAS#
    <8,11> DDR_SMA10 A10/AP_B RAS#_B DDR_SRAS# <8,11> <8> DDR_SDQS[0..7] DDR_DQS[0..7] <11>
    DDR_SBS0 B117 B120 DDR_SCAS#
    <8,11> DDR_SBS0 BA0_B CAS#_B DDR_SCAS# <8,11>
    DDR_SWE# DDR_SCS#3
    <8,11> DDR_SWE#
    <8,11> DDR_SCS#2
    DDR_SCS#2
    B119
    B121
    WE#_B
    S0#_B
    S1#_B
    SA0_B
    B122
    B194 +3VS
    DDR_SCS#3 <8,11> Compal Electronics, Inc.
    B158 B196 Title
    <8> DDR_CLK4# CK1#_B SA1_B
    <8> DDR_CLK4 B160 CK1_B SA2_B B198
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR-SODIMM
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    QUASA_CA0184-218Y61
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL20 LA-2461 0.3

    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期三, 八月 04, 2004 Sheet 10 of 47
    5 4 3 2 1
    A B C D E

    +1.25VS
    RP5 RP4 DDR_SMA[6..12]
    DDR_SMA[6..12] <8,10>
    Layout note : DDR_DQ62 1 8 1 8 DDR_DQ60
    DDR_DQ56 2 7 2 7 DDR_DQ61 DDR_DQ[0..63]
    DDR_DQ[0..63] <10>
    Distribute as close as possible DDR_DQS7 3 6 3 6 DDR_DM7
    DDR_DQ58 4 5 4 5 DDR_DQ57 DDR_DQS[0..7]
    to DDR-SODIMM. DDR_DQS[0..7] <10>
    56_0804_8P4R_5% 56_0804_8P4R_5% DDR_DM[0..7]
    DDR_DM[0..7] <10>
    RP7 RP6
    DDR_DQ63 1 8 1 8 DDR_DQ59
    +2.5V DDR_DQ50 2 7 2 7 DDR_DQ51
    DDR_DQ55 3 6 3 6 DDR_DQ54
    DDR_DQS6 4 5 4 5 DDR_DM6
    1 1 1 1 1 1 1 1 1
    1 56_0804_8P4R_5% 56_0804_8P4R_5% 1
    C608 C633 C634 C570 C519 C502 C557 C574 C572
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z RP9 RP8
    2 2 2 2 2 2 2 2 2 DDR_DQ49 DDR_DQ53
    1 8 1 8
    DDR_DQ52 2 7 2 7 DDR_DQ48
    DDR_DQ43 3 6 3 6 DDR_DQ46
    DDR_DQ42 4 5 4 5 DDR_DQ47

    56_0804_8P4R_5% 56_0804_8P4R_5%
    +2.5V +2.5V
    RP11 RP10
    DDR_DQS5 1 8 1 8 DDR_DM5
    1 1 1 1 1 1 DDR_DQ40 2 7 2 7 DDR_DQ45
    DDR_DQ44 3 6 3 6 DDR_DQ41
    C593 C556 C594 C607 + + DDR_DQ34 4 5 4 5 DDR_DQ35
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C118 C215
    2 2 2 2 150U_D2_6.3VM 150U_D2_6.3VM 56_0804_8P4R_5% 56_0804_8P4R_5%
    2 2
    RP13 RP12
    DDR_DQ38 1 8 1 8 DDR_DQ39
    DDR_DQS4 2 7 2 7 DDR_DM4
    DDR_DQ37 3 6 3 6 DDR_DQ33
    DDR_DQ32 4 5 4 5 DDR_DQ36

    56_0804_8P4R_5% 56_0804_8P4R_5%
    Layout note :
    Place one cap close to every 2 pull up resistors termination to
    +1.25V DDR_SCS#2
    <8,10> DDR_SCS#2 1 2 1 2 DDR_SCS#1 DDR_SCS#1 <8,10>
    R173 56_0402_5% R169 56_0402_5%
    RP15 RP14
    2 DDR_SWE# DDR_SCS#0 2
    <8,10> DDR_SWE# 8 1 8 1 DDR_SCS#0 <8,10>
    DDR_SMA10 7 2 7 2 DDR_SCAS#
    +1.25VS DDR_SCAS# <8,10>
    DDR_SBS0 6 3 6 3 DDR_SCS#3
    <8,10> DDR_SBS0 DDR_SCS#3 <8,10>
    DDR_SMA_B1 5 4 5 4 DDR_SRAS#
    <8,10> DDR_SMA_B1 DDR_SRAS# <8,10>
    1 1 1 1 1 1 1 1 56_0804_8P4R_5% 56_0804_8P4R_5%

    C185 C202 C144 C141 C136 C200 C199 C175 RP18 RP17
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_SMA3 8 1 8 1 DDR_SBS1
    2 2 2 2 2 2 2 2 <8,10> DDR_SMA3 DDR_SBS1 <8,10>
    DDR_SMA_B5 7 2 7 2 DDR_SMA1
    <8,10> DDR_SMA_B5 DDR_SMA1 <8,10>
    DDR_SMA7 6 3 6 3 DDR_SMA0
    DDR_SMA0 <8,10>
    DDR_SMA9 5 4 5 4 DDR_SMA2
    DDR_SMA2 <8,10>
    56_0804_8P4R_5% 56_0804_8P4R_5%
    +1.25VS
    RP21 RP20
    DDR_SMA12 8 1 8 1 DDR_SMA4
    DDR_SMA4 <8,10>
    1 1 1 1 1 1 1 1 DDR_CKE3 7 2 7 2 DDR_SMA_B4
    <8,10> DDR_CKE3 DDR_SMA_B4 <8,10>
    DDR_CKE1 6 3 6 3 DDR_SMA6
    <8,10> DDR_CKE1
    C131 C157 C182 C128 C203 C201 C208 C220 DDR_SMA5 5 4 5 4 DDR_SMA_B2
    0.1U_0402_16V4Z <8,10> DDR_SMA5 DDR_SMA_B2 <8,10>
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2 2 2 2 2 56_0804_8P4R_5% 56_0804_8P4R_5%
    RP22
    8 1 DDR_SMA8
    7 2 DDR_SMA11
    6 3 DDR_CKE0
    +1.25VS DDR_CKE0 <8,10>
    5 4 DDR_CKE2
    DDR_CKE2 <8,10>
    56_0804_8P4R_5%
    1 1 1 1 1 1 1 1
    C213 C133 C198 C173 C223 C127 C155 C140 RP24 RP23
    3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_DQ27 1 8 1 8 DDR_DQ31 3
    2 2 2 2 2 2 2 2 DDR_DQ26 DDR_DQ30
    2 7 2 7
    DDR_DQS3 3 6 3 6 DDR_DM3
    DDR_DQ25 4 5 4 5 DDR_DQ29

    56_0804_8P4R_5% 56_0804_8P4R_5%
    +1.25VS RP26 RP25
    DDR_DQ24 1 8 1 8 DDR_DQ28
    DDR_DQ18 2 7 2 7 DDR_DQ23
    1 1 1 1 1 1 1 1 DDR_DQ22 3 6 3 6 DDR_DQ19
    DDR_DQS2 4 5 4 5 DDR_DM2
    C186 C219 C143 C137 C165 C120 C166 C225
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 56_0804_8P4R_5% 56_0804_8P4R_5%
    2 2 2 2 2 2 2 2 DDR_DQ20 DDR_DQ21
    1 2 1 2
    R197 56_0402_5% R196 56_0402_5%
    DDR_DQ16 1 2 1 2 DDR_DQ17
    R199 56_0402_5% R198 56_0402_5%
    DDR_DQ15 1 2 1 2 DDR_DQ10
    +1.25VS R206 56_0402_5% R205 56_0402_5%
    DDR_DQ14 1 2 1 2 DDR_DQ11
    R209 56_0402_5% R207 56_0402_5%
    1 1 1 1 1 1 1 1 RP28 RP27
    DDR_DQS1 1 8 1 8 DDR_DM1
    C150 C207 C178 C159 C123 C124 C121 C134 DDR_DQ13 2 7 2 7 DDR_DQ12
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_DQ8 3 6 3 6 DDR_DQ9
    2 2 2 2 2 2 2 2 DDR_DQ1 DDR_DQ6
    4 5 4 5

    56_0804_8P4R_5% 56_0804_8P4R_5%
    RP30 RP29
    DDR_DQ5 1 8 1 8 DDR_DQ4
    +1.25VS DDR_DQS0 2 7 2 7 DDR_DM0
    DDR_DQ3 3 6 3 6 DDR_DQ7
    4 DDR_DQ0 DDR_DQ2 4
    4 5 4 5
    1 1 1 1
    56_0804_8P4R_5% 56_0804_8P4R_5%
    C227 C230 C224 C228
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR SODIMM Decoupling
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 11 of 47


    A B C D E
    A B C D E F G H

    Clock Generator
    +3VS_CLK
    SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2]
    Width=40 mils
    0 0 0 166.67 166.67 +3VS 2
    0_0805_5%
    1
    L10
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

    0 0 1 100.00 100.00 * 2
    0_0805_5%
    1
    L35
    1 1 1 1 1 1 1 1 1 1 1

    0 1 0 200.00 200.00 C640


    10U_0805_10V4Z
    C625 C614 C605 C600 C602 C620 C627 C639 C205 C603
    2 2 2 2 2 2 2 2 2 2 2
    0 1 1 133.33 133.33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

    1 1

    14
    19
    32
    37
    46
    50
    1
    8
    U46

    VDD_REF
    VDD_PCI_0
    VDD_PCI_1
    VDD_3V66_0
    VDD_3V66_1
    VDD_48MHZ
    VDD_CPU_0
    VDD_CPU_1
    C637 +3VS
    10P_0402_50V8K
    +3VS +3VS 1 2 XTALIN 2 26 +3V_VDD 1 2
    XTAL_IN VDDA L25 0_0805_5%

    1
    1 1
    Y5

    1
    C599 C595
    R571 R573 10U_0805_10V4Z
    2 2

    2
    1K_0402_5% 1K_0402_5% 14.318MHZ_16PF_DSX840GA
    @ 1 2 XTALOUT 3 27
    C631 XTAL_OUT VSSA 0.1U_0402_16V4Z

    2
    10P_0402_50V8K 45 CLK_MCH 1 2
    CPUCLKT2 CLK_MCH_BCLK <6>
    54 R548
    SEL0 33_0402_5% R547
    55 SEL1 49.9_0402_1%
    40 SEL2 1 2
    2

    2
    1 2

    2
    R570 R572 R532 R539 R538 49.9_0402_1%
    @ 1K_0402_5% 33_0402_5%
    1K_0402_5% 25 44 CLK_MCH# 1 2
    +3VS <23,34> SLP_S1# PWR_DWN# CPU_CLKC2 CLK_MCH_BCLK# <6>
    <23> STP_PCI# 34 PCI_STOP#
    1

    1K_0402_5% 53 49 CLK_BCLK 1 2
    <23,45> STP_CPU# CPU_STOP# CPUCLKT1 CLK_CPU_BCLK <4>
    1
    R557
    33_0402_5% R556
    49.9_0402_1%
    2

    1 2
    +3VS 1 2 28 VTT_PWRGD# 1 2
    R498 R505 10K_0402_5% R554 R553 49.9_0402_1%
    10K_0402_5% 33_0402_5%
    2 CLK_BCLK# 2
    D CPUCLKC1 48 1 2 CLK_CPU_BCLK# <4>
    1

    +3VS 1 2 43 MULT0
    1 2 2 Q38 R530 10K_0402_5% 52 CLK_ITP 1 2
    <7,23,45> VGATE CPUCLKT0 CLK_CPU_ITP <4>
    R496 0_0402_5% G 2N7002_SOT23
    R569 R568
    S 49.9_0402_1%
    3

    +VCCP 1 2 29 33_0402_5% 1 2
    <10,22> SMB_DATA SDATA
    R497 30 1 2
    <10,22> SMB_CLK SCLK
    @ 56_0402_5% 1 R563 R562 49.9_0402_1%
    if pull high to +VCCP 33_0402_5%
    0.1U_0402_16V4Z

    51 CLK_ITP# 1 2
    CPUCLKC0 CLK_CPU_ITP# <4>
    Change to DTC124EK C671 33 3V66_0
    @ 2 1 2 SSC_66M 35 24
    <7> CLK_SSC_66M 3V66_1/VCH_CLK 3V66_5
    R508 33_0402_5%

    23 MCH_66M 1 2 R509 33_0402_5%


    3V66_4 CLK_MCH_66M <7>
    R531 1 2 475_0402_1% 42 22 AGP_66M 1 2 R514 33_0402_5% M11@
    IREF 3V66_3 CLK_AGP_66M <13>
    21 ICH_66M 1 2 R515 33_0402_5%
    3V66_2 CLK_ICH_66M <22>

    R525 1 2 10_0402_5% CLK_ICH48M 39 7 P CI_ICH 1 2 R560 33_0402_5%


    <23> CLK_ICH_48M 48MHZ_USB PCICLK_F2 CLK_PCI_ICH <22>
    R524 1 2 10_0402_5% 6
    <28> CLK_EXT_SD48 5IN1@ PCICLK_F1
    PCICLK_F0 5

    1 2 CLK_MCH48M 38
    <7> CLK_MCH_48M R526 33_0402_5% 48MHZ_DOT PCI_MINI
    PCICLK6 18 1 2 R529 33_0402_5% KS@ CLK_PCI_MINI <30>
    PCICLK5 17
    16 PCI_LPC 1 2 R534 33_0402_5%
    PCICLK4 CLK_PCI_LPC <34>
    <23> CLK_ICH_14M
    R576 1 2 10_0402_5% CLK_ICH14M 56 REF PCICLK3 13 PCI_SIO 1 2 R543 33_0402_5% SIO@
    CLK_PCI_SIO <33>
    R575 1 2 10_0402_5% SIO@ 12 PCI_LAN 1 2 R544 33_0402_5%
    <33> CLK_14M_SIO PCICLK2 CLK_PCI_LAN <26>
    GND_3V66_0
    GND_3V66_1
    R574 1 2 10_0402_5% @
    GND_48MHZ
    11 PCI_1394 1 2 R551 33_0402_5%
    GND_PCI_0
    GND_PCI_1

    <31> CLK_14M_CODEC GND_IREF PCICLK1 CLK_PCI_1394 <27>


    PCI_PCM R552 33_0402_5%
    GND_CPU
    10 1 2
    GND_REF

    3 PCICLK0 CLK_PCI_PCM <28> 3


    4
    9
    15
    20
    31
    36
    41
    47

    CY28346ZCT-2_TSSOP56

    4 4

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Clock Generator
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 12 of 47
    A B C D E F G H
    5 4 3 2 1

    U7A

    AGP_AD0 H29
    M10-P/(M9+X) AJ5 STRAP_G 4M32
    <7> AGP_AD0 AD0 GPIO0
    <7> AGP_AD1
    AGP_AD1
    DVOB_D1
    H28 AD1 (1/6) GPIO1 AH5 STRAP_H
    Samsung: K4D263238E-GC33
    J29 AD2 GPIO2 AJ4
    <7,19> DVOC_D[0..11]
    DVOC_D[0..11] DVOB_D0 J28 AD3 GPIO3 AK4 Hynix: HY5DU283222AF-33
    DVOB_D3 K29 AH4
    DVOB_D[0..11] DVOB_D2 AD4 GPIO4
    <7> DVOB_D[0..11] K28 AD5 GPIO5 AF4 8M32
    DVOB_D5 L29 AJ3
    AGP_SBA[0..7] DVOB_D4 L28
    AD6 GPIO6
    AK3
    Samsung: K4D553238E-JC33
    <7> AGP_SBA[0..7] AD7 GPIO7
    DVOB_D6 N28 AD8 GPIO8 AH3 Hynix: HY5DU573222AFM-33
    DVOB_D9 P29 AJ2
    DVOB_D8 AD9 GPIO9 GPIO10 +3VS
    P28 AD10 GPIO10 AH2
    DVOB_D11 R29 AH1 POWER_SEL
    CLK_AGP_66M DVOB_D10 AD11 GPIO11
    D
    <7,19> DVOBC_CLKINT
    R28
    DVOBC_CLKINT T29 AD12
    AD13
    GPIO12
    GPIO13
    AG3
    AG1
    High for 1.0V STRAP_G * R46 1 2 10K_0402_5% M11@
    D

    <7> AGP_AD14
    AGP_AD14 T28 AD14 GPIO14 AG2
    * Low for 1.2V R42 1 2 10K_0402_5% @
    1

    MDDCDATA POWER_SEL
    R383
    <7> MDDCDATA
    <7,19> DVOC_VSYNC
    U29
    DVOC_VSYNC N25 AD15
    AD16
    GPIO15
    GPIO16
    AF3
    AF2 MCLK_SPREAD
    POWER_SEL <43>
    STRAP_H * R35 1 2 10K_0402_5% M11@

    1
    10_0402_5% DVOC_HSYNC R26 R323 M11@ R41 1 2 10K_0402_5% @
    @ <7,19> DVOC_HSYNC AGP_AD18 AD17 VREFG R317
    P25 AG4 15mil 2 1

    ZV PORT / EXT TMDS / GPIO / ROM


    <7> AGP_AD18 AD18 VREFG/(NC) +3VS
    DVOC_D0 R27 1K_0402_1% 100K_0402_5%
    AD19
    2

    1
    1 DVOC_D1 R25 AF5 M11@
    DVOC_D2 AD20 ROMCS# R327
    T25 AD21 Memory Config.

    2
    C465 DVOC_D3 T26 AH6 STRAP_R 1K_0402_1%
    18P_0402_50V8K DVOC_D4 U25
    AD22 ZV_LCDDATA0
    AJ6 STRAP_S M11@ GPIO10=High, 128MB
    2 @ AD23 ZV_LCDDATA1
    DVOC_D7 V27 AD24 ZV_LCDDATA2 AK6 STRAP_T GPIO10=Low, 64MB GPIO10 R34 1 2 10K_0402_5% 128M@

    2
    DVOC_D6 W26 AH7 R36 1 2 10K_0402_5% 64M@
    DVOC_D9 AD25 ZV_LCDDATA3
    W25 AD26 ZV_LCDDATA4 AK7
    DVOC_D8 Y26 AJ7
    R120 2 STP_AGP# DVOC_D11 AD27 ZV_LCDDATA5 STRAP_R
    +3VS 1 10K_0402_5% Y25 AD28 ZV_LCDDATA6 AH8 R320 1 2 10K_0402_5% 128M@
    M11@ DVOC_D10 AA26 AJ8 R324 1 2 10K_0402_5% 64M@
    AGP_AD30 AD29 ZV_LCDDATA7
    <7> AGP_AD30 AA25 AD30 ZV_LCDDATA8 AH9
    AGP_AD31 AA27 AJ9 STRAP_S R48 1 2 10K_0402_5% M11@
    <7> AGP_AD31 AD31 ZV_LCDDATA9
    AK9 R49 1 2 10K_0402_5% @
    ZV_LCDDATA10
    ZV_LCDDATA11 AH10
    DVOB_D7 N29 AE6 STRAP_T R330 1 2 10K_0402_5% @
    AGP_CBE#1 C/BE#0 ZV_LCDDATA12 R328 1
    <7> AGP_CBE#1 U28 C/BE#1 ZV_LCDDATA13 AG6 2 10K_0402_5% M11@
    AGP_CBE#2 P26 AF6
    <7> AGP_CBE#2 C/BE#2 ZV_LCDDATA14
    DVOC_D5 U26 AE7
    C/BE#3 ZV_LCDDATA15
    <12> CLK_AGP_66M ZV_LCDDATA16 AF7
    CLK_AGP_66M AG30 AE8
    PCICLK ZV_LCDDATA17
    <7,19,22,25,27,28,30> PCIRST#
    R382 1 2 0_0805_5% (20mils) NB_PCIRST# AG28 RST# ZV_LCDDATA18 AG8 M11_LCD_DATA <20>
    M11@ AGP_REQ#
    <7>
    <7>
    AGP_REQ#
    AGP_GNT#
    AGP_GNT#
    AF28
    AD26
    REQ# ZV_LCDDATA19 AF8
    AE9
    M11_LCD_CLK <20> GPIO10 R S T
    AGP_PAR GNT# ZV_LCDDATA20
    C <7>
    <7>
    AGP_PAR
    MDDCCLK
    MDDCCLK
    M25
    N26
    PAR ZV_LCDDATA21 AF9
    AG10
    0 0 0 0 4Mx32 Samsung x4 C
    STOP# ZV_LCDDATA22
    <7,19>
    <7>
    MI2CDATA
    MDVICLK
    MI2CDATA
    MDVICLK
    V29
    V28
    DEVSEL# ZV_LCDDATA23 AF10 +3VS
    * 0 0 1 0 4Mx32 Hynix x4
    TRDY#

    PCI/AGP
    <7,19>
    <7>
    MI2CCLK
    MDVIDATA
    MI2CCLK
    MDVIDATA
    W29
    W28
    IRDY# ZV_LCDCNTL0 AJ10
    AK10
    ZV_LCDCNTL0
    ZV_LCDCNTL1
    R50
    R52
    1
    1
    2
    2
    10K_0402_5% @
    10K_0402_5% @ 1 1 0 0 8Mx32 Samsung x4
    FRAME# ZV_LCDCNTL1
    <22,28> PCI_PIRQA#
    PCI_PIRQA# AE26 INTA# ZV_LCDCNTL2 AJ11
    AH11
    ZV_LCDCNTL2
    ZV_LCDCNTL3
    R53
    R54
    1
    1
    2
    2
    10K_0402_5% @
    10K_0402_5% @ 1 1 1 0 8Mx32 Hynix x4
    ZV_LCDCNTL3
    <7> AGP_WBF#
    AGP_WBF# AC26 WBF#
    AE10
    0 0 0 1 4Mx32 Samsung x2 Ch. A
    DVOMODE
    <23> STP_AGP#
    STP_AGP# AH30
    AGP_BUSY# AH29 STP_AGP# 0 0 1 1 4Mx32 Hynix x2 Ch. A
    <7,23> AGP_BUSY# AGP_BUSY#
    AGP_RBF# AE29
    <7> AGP_RBF# RBF#
    AGP_ADSTB0 M28 AK16 M11_TXOUT0-
    <7> AGP_ADSTB0 AD_STBF_0 TXOUT_L0N M11_TXOUT0- <20>
    DVOC_CLK V25 AH16 M11_TXOUT0+
    <7,19> DVOC_CLK AD_STBF_1 TXOUT_L0P M11_TXOUT0+ <20>
    AGP_ADSTB0# M29 AH17 M11_TXOUT1-
    <7> AGP_ADSTB0# AD_STBS_0 TXOUT_L1N M11_TXOUT1- <20>
    DVOC_CLK# V26 AJ16 M11_TXOUT1+
    <7,19> DVOC_CLK# AD_STBS_1
    LVDS

    TXOUT_L1P M11_TXOUT2- M11_TXOUT1+ <20>


    TXOUT_L2N AH18 M11_TXOUT2- <20>
    AGP_SBA0 AD28 AJ17 M11_TXOUT2+
    AGP_SBA1 SBA0 TXOUT_L2P M11_TXOUT2+ <20>
    AD29 SBA1 TXOUT_L3N AK19
    AGP_SBA2 +3VS
    AGP8X

    AC28 SBA2 TXOUT_L3P AH19


    AGP_SBA3 AC29 AK18 M11_TXCLK- X1 M11@
    AGP_SBA4 SBA3 TXCLK_LN M11_TXCLK+ M11_TXCLK- <20> FREQOUT 1 VGA_XTALIN
    AA28 SBA4 TXCLK_LP AJ18 M11_TXCLK+ <20> 4 VDD OUT 3 2
    AGP_SBA5 AA29 AG16 M11_TZOUT0- R99 M11@ R119 261_0603_1%
    SBA5 TXOUT_U0N M11_TZOUT0- <20>

    1
    AGP_SBA6 Y28 AF16 M11_TZOUT0+ 1 2 1 2
    AGP_SBA7 SBA6 TXOUT_U0P M11_TZOUT1- M11_TZOUT0+ <20> 10K_0402_5% OE GND
    Y29 SBA7 TXOUT_U1N AG17 M11_TZOUT1- <20> 1
    AF17 M11_TZOUT1+ 27MHZ_15P M11@ R118 C87
    AGP_ST0 TXOUT_U1P M11_TZOUT2- M11_TZOUT1+ <20> C61 150_0402_1% @
    <7> AGP_ST0 AF29 ST0 TXOUT_U2N AF18 M11_TZOUT2- <20>
    AGP_ST1 AD27 AE18 M11_TZOUT2+ 0.1U_0402_16V4Z M11@ 15P_0402_50V8J
    <7> AGP_ST1 ST1 TXOUT_U2P M11_TZOUT2+ <20> 2

    2
    AGP_ST2 AE28 AH20 M11@
    <7> AGP_ST2 ST2 TXOUT_U3N
    TXOUT_U3P AG20
    AGP_SBSTB AB29 AF19 M11_TZCLK-
    <7> AGP_SBSTB SB_STBF TXCLK_UN M11_TZCLK- <20>
    B AGP_SBSTB# AB28 AG19 M11_TZCLK+ B
    <7> AGP_SBSTB# SB_STBS TXCLK_UP M11_TZCLK+ <20>
    +AGP_VREF M26 AE12 ENVDD
    AGPREF DIGON ENVDD <20>
    1 +1.5VS 1 2 AGPTEST15mil M27 AG12 ENBKL
    C440 R380 M11@ 47_0402_1% AGPTEST BLON/(BLON#) ENBKL <34>
    M11@ AGP_DBIHI AB25
    0.1U_0402_16V4Z AGP_DBILO DBI_HI
    AB26 DBI_LO TX0M AJ13
    2
    TX0P AH14
    +3VS R369 2 M11@ 1 10K_0402_5% AC25 AJ14
    AGP8X_DET# TX1M
    TX1P AH15
    TX2M AJ15
    AE11 DMINUS TX2P AK15
    R368 1 M11@ 2 1K_0402_5% AGP_DBIHI
    +1.5VS
    R377 1 M11@ 2 1K_0402_5% AGP_DBILO
    AF11 DPLUS THRM TXCM AH13
    AK13
    TXCP
    TMDS

    DDC2CLK AE13
    1 M11@ 2 R2SET15mil AK21 AE14
    R359 715_0603_1% R2SET DDC2DATA
    R345 1 M11@ 2 100K_0402_5% +3VS
    <21> M11_TV_CRMA AJ23 C_R HPD1 AF12 DDR SPREAD SPECTRUM
    AJ22 Y_G
    <21> M11_TV_LUMA C358 1
    AK22 COMP_B 2 0.1U_0402_16V4Z M11@
    75_0402_1% R603 AJ24
    M11P H2SYNC U33
    AK24 V2SYNC R AK27 M11_CRT_R <21>
    75_0402_1% R604 AJ27 7 5
    G M11_CRT_G <21> VDD REF
    SSC DAC2

    M11P AG23 AJ26


    75_0402_1% R365 DDC3CLK B M11_CRT_B <21> FREQOUT MCLK_SPREAD
    AG24 DDC3DATA HSYNC AG25 M11_CRT_HSYNC <21> 1 XIN MODOUT 1 4 2
    M11P AH25 R321 22_0402_5% M11@
    VSYNC M11_CRT_VSYNC <21>
    8 XOUT NC 1 3 2
    AK25 AH26 RSET 1 2 R370 R325 10K_0402_5% @
    SSIN RSET M11@ 499_0603_1%
    15mil 2 VSS PD# 6 1 2 +3VS
    AJ25 AF25 R343 10K_0402_5% @
    SSOUT DDC1DATA M11_CRT_DDC_DATA <21> ASM3P1819-SR_SO8 M11@
    A AF24 A
    DAC1

    DDC1CLK M11_CRT_DDC_CLK <21>


    Pin3 : Reserved for P1819 Spread Rate selection.
    AF26 R372 1 2 10K_0402_5% +3VS
    VGA_XTALIN AUXWIN M11@
    AH28 XTALIN
    CLK

    AJ29 XTALOUT TEST_MCLK/(NC) B6

    TEST_YCLK/(NC) E8

    1
    15mil
    2 TESTEN AH27 TESTEN PLLTEST/(NC) AE25 Title Compal Electronics, Inc.
    <23,35> SUS_STAT#
    R379 M11@ 1K_0402_5%
    SUS_STAT# AG26 AG29
    ATI M10-P/M11-AGP/DISPLAY(1/4)
    SUS_STAT# RSTB_MSK/(NC) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    +3VS 2
    R373
    1
    M11@ 10K_0402_5% M11P_BGA708 M11@ R381 2 1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    1K_0402_5% M11@ Date: 星期三, 八月 04, 2004 Sheet 13 of 47


    5 4 3 2 1
    5 4 3 2 1

    NMDA[0..63] NMDB[0..63]
    <17> NMDA[0..63] <18> NMDB[0..63]
    NMAA[0..13] NMAB[0..13]
    <17> NMAA[0..13] <18> NMAB[0..13]
    NDQMA[0..7] NDQMB[0..7]
    <17> NDQMA[0..7] <18> NDQMB[0..7]
    NDQSA[0..7] NDQSB[0..7]
    <17> NDQSA[0..7] <18> NDQSB[0..7]

    D D

    U7B U7C

    NMDA0 L25
    M10-P/(M9+X) E22 NMAA0 NMDB0 D7
    M10-P/(M9+X) N5 NMAB0
    DQA0 AA0 DQB0 AB0
    NMDA1
    NMDA2
    L26 DQA1 (2/6) AA1 B22 NMAA1
    NMAA2
    NMDB1
    NMDB2
    F7 DQB1 (3/6) AB1 M1 NMAB1
    NMAB2
    K25 DQA2 AA2 B23 E7 DQB2 AB2 M3
    NMDA3 K26 B24 NMAA3 NMDB3 G6 L3 NMAB3
    NMDA4 DQA3 AA3 NMAA4 NMDB4 DQB3 AB3 NMAB4
    J26 DQA4 AA4 C23 G5 DQB4 AB4 L2
    NMDA5 H25 C22 NMAA5 NMDB5 F5 M2 NMAB5
    NMDA6 DQA5 AA5 NMAA6 NMDB6 DQB5 AB5 NMAB6
    H26 DQA6 AA6 F22 E5 DQB6 AB6 M5
    NMDA7 G26 F21 NMAA7 NMDB7 C4 P6 NMAB7
    NMDA8 DQA7 AA7 NMAA8 NMDB8 DQB7 AB7 NMAB8
    G30 DQA8 AA8 C21 B5 DQB8 AB8 N3
    NMDA9 D29 A24 NMAA9 NMDB9 C5 K2 NMAB9
    NMDA10 DQA9 AA9 NMAA10 NMDB10 DQB9 AB9 NMAB10
    D28 DQA10 AA10 C24 A4 DQB10 AB10 K3
    NMDA11 E28 A25 NMAA11 NMDB11 B4 J2 NMAB11
    NMDA12 DQA11 AA11 NMAA12 NMDB12 DQB11 AB11 NMAB12
    E29 DQA12 AA12/(AA13) E21 C2 DQB12 AB12/(AB13) P5
    NMDA13 G29 B20 NMAA13 NMDB13 D3 P3 NMAB13
    NMDA14 DQA13 AA13/(AA12) NMDB14 DQB13 AB13/(AB12)
    G28 DQA14 AA14/(NC) C19 D1 DQB14 AB14/(NC) P2
    NMDA15 F28 NMDB15 D2
    NMDA16 DQA15 NDQMA0 NMDB16 DQB15 NDQMB0
    G25 DQA16 DQMA#0 J25 G4 DQB16 DQMB#0 E6
    NMDA17 F26 F29 NDQMA1 NMDB17 H6 B2 NDQMB1
    NMDA18 DQA17 DQMA#1 NDQMA2 NMDB18 DQB17 DQMB#1 NDQMB2
    MEMORY INTERFACE
    E26 DQA18 DQMA#2 E25 H5 DQB18 DQMB#2 J5

    MEMORY INTERFACE B
    NMDA19 F25 A27 NDQMA3 NMDB19 J6 G3 NDQMB3
    NMDA20 DQA19 DQMA#3 NDQMA4 NMDB20 DQB19 DQMB#3 NDQMB4
    E24 DQA20 DQMA#4 F15 K5 DQB20 DQMB#4 W6
    NMDA21 F23 C15 NDQMA5 NMDB21 K4 W2 NDQMB5
    NMDA22 DQA21 DQMA#5 NDQMA6 NMDB22 DQB21 DQMB#5 NDQMB6
    E23 DQA22 DQMA#6 C11 L6 DQB22 DQMB#6 AC6
    NMDA23 D22 E11 NDQMA7 NMDB23 L5 AD2 NDQMB7
    NMDA24 DQA23 DQMA#7 NMDB24 DQB23 DQMB#7
    B29 DQA24 G2 DQB24
    NMDA25 C29 NMDB25 F3 F6 NDQSB0
    NMDA26 DQA25 NDQSA0 NMDB26 DQB25 QSB0 NDQSB1
    C25 DQA26 QSA0 J27 H2 DQB26 QSB1 B3
    C NMDA27 NDQSA1 NMDB27 NDQSB2 C
    C27 DQA27 QSA1 F30 E2 DQB27 QSB2 K6
    NMDA28 B28 F24 NDQSA2 NMDB28 F2 G1 NDQSB3
    NMDA29 DQA28 QSA2 NDQSA3 NMDB29 DQB28 QSB3 NDQSB4
    B25 DQA29 QSA3 B27 J3 DQB29 QSB4 V5
    NMDA30 C26 E16 NDQSA4 NMDB30 F1 W1 NDQSB5
    NMDA31 DQA30 QSA4 NDQSA5 NMDB31 DQB30 QSB5 NDQSB6
    B26 DQA31 QSA5 B16 H3 DQB31 QSB6 AC5
    NMDA32 F17 B11 NDQSA6 NMDB32 U6 AD1 NDQSB7
    NMDA33 DQA32 QSA6 NDQSA7 NMDB33 DQB32 QSB7
    E17 F10 U5
    A

    NMDA34 DQA33 QSA7 NMDB34 DQB33 NMRASB#


    D16 DQA34 U3 DQB34 RASB# R2 NMRASB# <18>
    NMDA35 F16 NMDB35 V6
    NMDA36 DQA35 NMDB36 DQB35 NMCASB#
    E15 DQA36 W5 DQB36 CASB# T5 NMCASB# <18>
    NMDA37 F14 A19 NMRASA# NMDB37 W4
    NMDA38 DQA37 RASA# NMRASA# <17> NMDB38 DQB37 NMWEB#
    E14 DQA38 Y6 DQB38 WEB# T6 NMWEB# <18>
    NMDA39 F13 E18 NMCASA# NMDB39 Y5
    NMDA40 DQA39 CASA# NMCASA# <17> NMDB40 DQB39 NMCSB0#
    C17 DQA40 U2 DQB40 CSB0# R5 NMCSB0# <18>
    NMDA41 B18 E19 NMWEA# NMDB41 V2
    NMDA42 DQA41 WEA# NMWEA# <17> NMDB42 DQB41 NMCSB1#
    B17 DQA42 V1 DQB42 CSB1# R6 NMCSB1# <18>
    NMDA43 B15 E20 NMCSA0# NMDB43 V3
    NMDA44 DQA43 CSA0# NMCSA0# <17> NMDB44 DQB43 NMCKEB
    C13 DQA44 W3 DQB44 CKEB R3 NMCKEB <18>
    NMDA45 B14 F20 NMCSA1# NMDB45 Y2
    NMDA46 DQA45 CSA1# NMCSA1# <17> NMDB46 DQB45 CLKB0 R39 NMCLKB0
    C14 DQA46 Y3 DQB46 CLKB0 N1 1 M11@ 2 10_0402_5% NMCLKB0 <18>
    NMDA47 C16 B19 NMCKEA NMDB47 AA2 N2 CLKB0# R40 1 M11@ 2 10_0402_5% NMCLKB0#
    DQA47 CKEA NMCKEA <17> DQB47 CLKB0# NMCLKB0# <18>
    NMDA48 A13 NMDB48 AA6
    NMDA49 DQA48 NMDB49 DQB48 CLKB1 R38 NMCLKB1
    A12 DQA49 AA5 DQB49 CLKB1 T2 1 M11@ 2 10_0402_5% NMCLKB1 <18>
    NMDA50 C12 B21 CLKA0 R77 1 M11@ 2 10_0402_5% NMCLKA0 NMDB50 AB6 T3 CLKB1# R37 1 M11@ 2 10_0402_5% NMCLKB1#
    DQA50 CLKA0 NMCLKA0 <17> DQB50 CLKB1# NMCLKB1# <18>
    NMDA51 B12 C20 CLKA0# R71 1 M11@ 2 10_0402_5% NMCLKA0# NMDB51 AB5
    DQA51 CLKA0# NMCLKA0# <17> DQB51
    NMDA52 C10 NMDB52 AD6
    NMDA53 DQA52 DQB52 +1.8VS
    C9 DQA53 CLKA1 C18 CLKA1 R64 1 M11@ 2 10_0402_5% NMCLKA1 NMCLKA1 <17>
    NMDB53 AD5 DQB53
    NMDA54 B9 A18 CLKA1# R68 1 M11@ 2 10_0402_5% NMCLKA1# NMDB54 AE5 15mil
    DQA54 CLKA1# NMCLKA1# <17> DQB54
    NMDA55 B10 NMDB55 AE4 C6 MEMVMODE0 R329 1 M11@ 2 4.7K_0402_5%
    NMDA56 DQA55 NMDB56 DQB55 MEMVMODE0 MEMVMODE1 R333 1 M11@
    E13 DQA56 DIMA0 D30 AB2 DQB56 MEMVMODE1 C7 2 4.7K_0402_5%
    NMDA57 E12 B13 NMDB57 AB3 15mil
    B NMDA58 DQA57 DIMA1 NMDB58 DQB57 B
    E10 DQA58 AC2 DQB58 DIMB0 E3
    NMDA59 F12 NMDB59 AC3 AA3
    NMDA60 DQA59 MVREFD NMDB60 DQB59 DIMB1
    F11 DQA60 MVREFD B7 AD3 DQB60
    NMDA61 E9 NMDB61 AE1
    NMDA62 DQA61 MVREFS NMDB62 DQB61 MEMTEST R338 1 M11@
    F9 DQA62 MVREFS/(NC) B8 AE2 DQB62 MEMTEST C8 2 47_0402_1%
    NMDA63 F8 NMDB63 AE3 15mil
    DQA63 DQB63
    M11P_BGA708 M11@
    M11P_BGA708 M11@

    +2.5VS +2.5VS
    NMCKEA 1 M11@ 2
    R352 10K_0402_5%
    1

    NMCKEB 1 M11@ 2
    R341 R347 R315 10K_0402_5%
    M11@ M11@
    1K_0402_1% 1K_0402_1%
    2

    MVREFD MVREFS
    20mil 20mil
    1

    1 1
    C362 R339 C368 R349
    M11@ M11@
    M11@ 1K_0402_1% M11@ 1K_0402_1%
    2 2
    2

    0.1U_0402_16V4Z 0.1U_0402_16V4Z

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ATI M10-P/M11-MEMORY(2/4)
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 14 of 47


    5 4 3 2 1
    5 4 3 2 1

    +2.5VS U7D +1.5VS


    +2.5VS
    B1
    M10-P/(M9+X)
    VDDR1
    B30 VDDR1 (4/6)
    A15 VDDR1 VDDRH0 F18 1 1 1 1 1 1 1
    A21 N6 C418 C420 C431 C430 C459 C458 C461
    VDDR1 VDDRH1 M11@ M11@ M11@ M11@ M11@ M11@ M11@
    A28 VDDR1
    A3 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.01U_0402_16V7K
    VDDR1 2 2 2 2 2 2 2
    0.01U_0402_16V7K
    A9 VDDR1 VSSRH0 F19
    AA1 M6 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.01U_0402_16V7K
    VDDR1 VSSRH1
    AA4 VDDR1
    AA7 VDDR1
    D AA8 VDDR1 ATI: 22Ux1, 0.1Ux2, 0.01Ux1, 1000Px1 D
    AD4 VDDR1 MPVDD A7 +VDD_MEMPLL1.8
    D5 VDDR1 MPVSS A6
    D8 VDDR1
    D11 +3VS +2.5VS
    VDDR1
    D13 VDDR1 PVDD AK28 +VDD_PLL1.8 20mil
    D14 VDDR1 PVSS AJ28
    D17 VDDR1
    D20 VDDR1 1 1 1 1 1 1 1
    D23 C403 C421 C366 C357 C363 C355 C426
    VDDR1 M11@ M11@ M11@ M11@ M11@ M11@ M11@
    D26 VDDR1 VDDR3 AC19 +3VS
    E27 AC21 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z
    VDDR1 VDDR3 2 2 2 2 2 2 2
    F4 VDDR1 VDDR3 AC22
    G7 AC8 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z
    VDDR1 VDDR3
    G10 VDDR1 VDDR3 AD19
    G13 VDDR1 VDDR3 AD21
    G15 VDDR1 VDDR3 AD22
    G19 VDDR1 VDDR3 AD7
    G22 VDDR1
    G27 +VDD_DAC2.5
    VDDR1 L21
    H10 VDDR1 20mil, 120mA
    H13 VDDR1 VDDR4 AC10 1 2 +2.5VS

    I/O POWER
    H15 AC9 M11@ CHB1608B121_0603
    VDDR1 VDDR4
    H17 VDDR1 VDDR4 AD10 1 1
    H19 AD9 C429 C423
    VDDR1 VDDR4 M11@ M11@
    H22 VDDR1 VDDR4 AG7
    J1 0.1U_0402_16V4Z
    VDDR1 2 2
    J23 VDDR1
    J24 10U_0805_10V4Z
    VDDR1
    J4 VDDR1 VDDP AA23 +1.5VS
    J7 VDDR1 VDDP AA24
    J8 VDDR1 VDDP AB30
    C C
    L27 VDDR1 VDDP AC23
    L8 VDDR1 VDDP AC27
    M4 AE30 +VDD_PNLIO1.8 +VDD_PLL1.8
    VDDR1 VDDP L19 L22
    N4 VDDR1 VDDP AF27 20mil, 30mA 20mil, 22mA
    N7 VDDR1 VDDP J30 1 2 +1.8VS 1 2 +1.8VS
    N8 M23 M11@ CHB1608B121_0603 M11@ CHB1608B121_0603
    VDDR1 VDDP
    R1 VDDR1 VDDP M24 1 1 1 1 1 1
    T4 N30 C395 C379 C389 C422 C455 C452
    VDDR1 VDDP M11@ M11@ M11@ M11@ M11@ M11@
    T7 VDDR1 VDDP P23
    T8 P27 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDDR1 VDDP 2 2 2 2 2 2
    V4 VDDR1 VDDP T23
    V7 T24 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
    VDDR1 VDDP
    V8 VDDR1 VDDP T30
    D19 VDDR1/(CLKAFB) VDDP U27
    R4 VDDR1/(CLKBFB) VDDP V23
    VDDP V24
    +1.5VS AC11 VDDC15/(VDDC18) VDDP W30
    AC20 Y27 +VDD_PNLPLL1.8 +VDD_DAC1.8
    VDDC15/(VDDC18) VDDP L7 L20
    H11 VDDC15/(VDDC18) change to +2.8V (max:350mA) 20mil, 6mA 20mil, 74mA
    H20 VDDC15/(VDDC18) 1 2 +1.8VS 1 2 +1.8VS
    L23 AE20 +LVDDR25 M11@ CHB1608B121_0603 M11@ CHB1608B121_0603
    VDDC15/(VDDC18) LVDDR_25/(LVDDR_18_25)
    P8 VDDC15/(VDDC18) LVDDR_25/(LVDDR_18_25) AE17 1 1 1 1 1
    Y23 AF21 +VDD_PNLIO1.8 C33 C57 C36 C432 C435
    VDDC15/(VDDC18) LVDDR_18 M11@ M11@ M11@ M11@ M11@
    Y8 VDDC15/(VDDC18) LVDDR_18 AE15
    AJ20 +VDD_PNLPLL1.8 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    LPVDD 2 2 2 2 2
    10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
    +VDD_PNLPLL1.8 AK12 TPVDD LVSSR AF20
    AJ12 TPVSS LVSSR AF15
    LVSSR AE19
    LVSSR AE16
    B AJ19 B
    LPVSS +VDD_MEMPLL1.8
    +VDD_DAC1.8 AH24 AVDD
    +VDD_DAC2.5 AG21 20mil, 6mA L6
    A2VDD +LVDDR25
    AH21 A2VDD VDD1DI AE24 +VDD_DAC1.8 1 2 +1.8VS
    AF22 A2VDDQ VDD2DI AE22 20mil, 83mAL18 M11@ CHB1608B121_0603
    1 2 +2.5VS 1 1
    @ CHB1608B121_0603 C28 C27
    AE23 U36 M11@ M11@
    VSS1DI 0.1U_0402_16V4Z
    AH22 A2VSSN VSS2DI AE21
    2 2
    AJ21 A2VSSN 5 VOUT VIN 1 +3VS
    AF23 10U_0805_10V4Z
    A2VSSQ
    TXVDDR AF13 1 1 PG 4
    AF14 C388 C396
    TXVDDR M11@ M11@ 2 GND EN 3
    AH23 10U_0805_10V4Z
    AVSSN 2 2
    0.1U_0402_16V4Z
    AD24 AVSSQ TXVSSR AG13
    AG14 MIC5205-2.8BM5_SOT23-5 M11@
    TXVSSR
    TXVSSR AH12

    SA052050010(MIC5205-2.8BM5), max:150mA

    M11P_BGA708 M11@

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ATI M10-P/M11-POWER(3/4)
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 15 of 47


    5 4 3 2 1
    5 4 3 2 1

    U7E U7F
    +VGA_CORE +VGA_CORE
    M10-P/(M9+X) M10-P/(M9+X) (+VGA_CORE = 1.2V)
    +VGA_CORE
    (5/6) M12 VDDC (6/6) VDDC AD15
    A10 VSS M13 VDDC VDDC AD13
    A16 VSS VSS H4 M14 VDDC
    M10-P&M9+X VDDC AC17
    A2 VSS VSS H8 M17 VDDC COMMON VDDC AC15
    +VDDCI

    22U_1206_16V4Z_V1

    22U_1206_16V4Z_V1

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.01U_0402_16V7K

    0.01U_0402_16V7K
    D A22 VSS VSS H9 M18 VDDC VDDC AC13 1 1 1 1 1 1 1 1 D
    A29 H12 M19 L17 C405 C369 C377 C398 C378 C390 C407 C402
    VSS VSS VDDC M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@
    AA30 VSS VSS H14 N12 VDDC VDDCI T12 1 2 +VGA_CORE
    AB1 H18 N13 M15 M11@ CHB1608B121_0603
    VSS VSS VDDC VDDCI 2 2 2 2 2 2 2 2
    AB23 VSS VSS H21 N14 VDDC VDDCI W16
    AB24 H23 N17 R19

    CORE POWER
    VSS VSS VDDC VDDCI
    AB27 VSS VSS H27 N18 VDDC
    AB4 VSS VSS K1 N19 VDDC
    AB7 VSS VSS K23 P12 VDDC VSS R12
    AB8 VSS VSS K24 P13 VDDC VSS R13
    AC12 VSS VSS K27 P14 VDDC VSS T13
    AC14 VSS VSS K30 P17 VDDC VSS R14
    AC16 VSS VSS K7 P18 VDDC VSS T14
    AC18 VSS VSS K8 P19 VDDC VSS N15
    AC4 L4 U12 P15 +VGA_CORE
    VSS VSS VDDC VSS +VDDCI
    CORE POWER

    AD12 VSS VSS M30 U13 VDDC VSS R15


    AD16 VSS VSS M7 U14 VDDC VSS T15 20mil
    AD18 VSS VSS M8 U17 VDDC VSS U15
    AD25 VSS VSS N23 U18 VDDC VSS V15 1 1

    10U_0805_10V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    AD30 VSS VSS N24 U19 VDDC VSS W15 1 1 1
    C370 C401 C394 C701 + + C321
    AE27
    AG11
    VSS VSS N27
    P4
    V12
    V13
    VDDC M10-P VSS H16
    M16 M11@ M11@ M11@ 470U_D2_2.5VM 470U_D2_2.5VM
    VSS VSS VDDC VSS
    AG15 VSS VSS R23 V14 VDDC ONLY VSS N16
    2 2 2
    @
    2 2
    M11@
    AG18 VSS VSS R24 V17 VDDC VSS P16
    AG22 VSS VSS R30 V18 VDDC VSS R16
    AG27 VSS VSS R7 V19 VDDC VSS T16
    AG5 VSS VSS R8 W12 VDDC VSS U16
    AG9 VSS VSS T1 W13 VDDC VSS V16
    AJ1 VSS VSS T27 W14 VDDC VSS R17
    AJ30 VSS VSS U23 W17 VDDC VSS T17
    AK2 VSS VSS U4 W18 VDDC VSS R18
    AK29 VSS VSS U8 W19 VDDC VSS T18
    C C
    C1 VSS VSS V30 VSS T19
    C28 W23 +2.5VS
    VSS VSS
    C3 VSS VSS W24
    C30 VSS VSS W27
    D10 VSS VSS W7

    22U_1206_16V4Z_V1

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.01U_0402_16V7K

    0.01U_0402_16V7K
    D12 VSS VSS W8 AB22 VDDC
    D15 VSS VSS Y4 AB9 VDDC 1 1 1 1 1 1
    D18 G9 J10 C391 C349 C359 C380 C365 C450
    VSS VSS VDDC M11@ M11@ M11@ M11@ M11@
    D21 VSS VSS G12 J12 VDDC
    D24 G16 J14 M11@
    VSS VSS VDDC 2 2 2 2 2 2
    D25 VSS VSS G18 J15 VDDC
    D27 VSS VSS G21 J16 VDDC VSS AA22
    D4 VSS VSS G24 J17 VDDC VSS AA9
    D6
    D9
    VSS J19
    J21
    VDDC M9+X VSS J11
    J13
    VSS VDDC VSS
    E4 VSS K22 VDDC ONLY VSS J18
    F27 VSS K9 VDDC VSS J20
    M22 VDDC VSS J22
    M9 J9 +2.5VS
    VDDC VSS
    P22 VDDC VSS L22
    M11P_BGA708 M11@ P9 L9
    VDDC VSS
    R22 VDDC VSS N22

    22U_1206_16V4Z_V1

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.01U_0402_16V7K

    0.01U_0402_16V7K
    R9 VDDC VSS N9
    T22 VDDC VSS W22 1 1 1 1 1 1
    T9 W9 C337 C453 C393 C451 C338 C406
    VDDC VSS M11@ M11@ M11@ M11@ M11@ M11@
    U22 VDDC
    U9 VDDC 2 2 2 2 2 2
    V22 VDDC
    V9 VDDC
    Y22 VDDC
    Y9 VDDC
    B B

    M11@ M11P_BGA708

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ATI M10-P/M11-POWER/GND(4/4)
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 16 of 47


    5 4 3 2 1
    5 4 3 2 1

    +2.5VS +2.5VS

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    C436 C414 C416 C447 C438 C449 C428 C448 C415 C350 C343 C354 C340 C341 C361 C360 C351 C339
    M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@
    22U_1206_16V4Z_V1
    22U_1206_16V4Z_V12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    D
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z D

    NMDA[0..63]
    <14> NMDA[0..63]
    NMAA[0..13]
    <14> NMAA[0..13]

    G10

    G10
    D10
    D11

    H10

    D10
    D11

    H10
    B11

    K10

    B11

    K10
    F10

    F10
    J10

    J10
    G5

    G5
    D4
    D5
    D6
    D9

    H5

    D4
    D5
    D6
    D9

    H5
    B4

    E6
    E9

    K5

    B4

    E6
    E9

    K5
    F5

    F5
    J5

    J5
    NDQMA[0..7] U10 U5
    <14> NDQMA[0..7]

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    NDQSA[0..7]
    <14> NDQSA[0..7]

    NMAA0 N5 B7 NMDA9 NMAA0 N5 B7 NMDA39


    NMAA1 A0 DQ0 NMDA10 NMAA1 A0 DQ0 NMDA38
    N6 A1 DQ1 C6 N6 A1 DQ1 C6
    NMAA2 M6 B6 NMDA12 NMAA2 M6 B6 NMDA37
    NMAA3 A2 DQ2 NMDA11 NMAA3 A2 DQ2 NMDA36
    N7 A3 DQ3 B5 N7 A3 DQ3 B5
    NMAA4 N8 C2 NMDA15 NMAA4 N8 C2 NMDA35
    NMAA5 A4 DQ4 NMDA8 NMAA5 A4 DQ4 NMDA34
    M9 A5 DQ5 D3 M9 A5 DQ5 D3
    NMAA6 N9 D2 NMDA13 NMAA6 N9 D2 NMDA33
    NMAA7 A6 DQ6 NMDA14 NMAA7 A6 DQ6 NMDA32
    N10 A7 DQ7 E2 N10 A7 DQ7 E2
    NMAA8 N11 K13 NMDA22 NMAA8 N11 K13 NMDA51
    NMAA9 A8/AP DQ8 NMDA23 NMAA9 A8/AP DQ8 NMDA49
    M8 A9 DQ9 K12 M8 A9 DQ9 K12
    NMAA10 L6 J13 NMDA21 NMAA10 L6 J13 NMDA50
    NMAA11 A10 DQ10 NMDA20 NMAA11 A10 DQ10 NMDA48
    M7 A11 DQ11 J12 M7 A11 DQ11 J12
    NMAA12 N4 G13 NMDA18 NMAA12 N4 G13 NMDA54
    NMAA13 BA0 DQ12 NMDA17 NMAA13 BA0 DQ12 NMDA55
    M5 BA1 DQ13 G12 M5 BA1 DQ13 G12
    F13 NMDA19 F13 NMDA53
    NDQMA1 DQ14 NMDA16 NDQMA4 DQ14 NMDA52
    B3 DM0 DQ15 F12 B3 DM0 DQ15 F12
    C NDQMA2 NMDA29 NDQMA6 NMDA44 C
    H12 DM1 DQ16 F3 H12 DM1 DQ16 F3
    +2.5VS NDQMA3 H3 F2 NMDA26 +2.5VS NDQMA5 H3 F2 NMDA46
    NDQMA0 DM2 DQ17 NMDA30 NDQMA7 DM2 DQ17 NMDA43
    B12 DM3 DQ18 G3 B12 DM3 DQ18 G3
    G2 NMDA31 G2 NMDA45
    DQ19 DQ19
    1

    1
    R80 NDQSA1 B2 J3 NMDA27 NDQSA4 B2 J3 NMDA42
    NDQSA2 DQS0 DQ20 NMDA28 R43 NDQSA6 DQS0 DQ20 NMDA47
    H13 DQS1 DQ21 J2 H13 DQS1 DQ21 J2
    M11@ NDQSA3 H2 K2 NMDA24 M11@ NDQSA5 H2 K2 NMDA41
    1K_0402_1% NDQSA0 DQS2 DQ22 NMDA25 1K_0402_1% NDQSA7 DQS2 DQ22 NMDA40
    B13 DQS3 DQ23 K3 B13 DQS3 DQ23 K3
    20mil E13 NMDA0 20mil E13 NMDA63
    DQ24 DQ24
    2

    2
    VR_VREF_1 N13 D13 NMDA1 VR_VREF_2 N13 D13 NMDA61
    VREF DQ25 NMDA2 VREF DQ25 NMDA62
    M13 MCL DQ26 D12 M13 MCL DQ26 D12
    1

    1
    NMDA3 NMDA58
    1K_0402_1%

    R74

    1K_0402_1%
    2 L9 C13 R47 2 L9 C13
    C50 RFU1 DQ27 NMDA5 C24 RFU1 DQ27 NMDA57
    M10 RFU2 DQ28 B10 M10 RFU2 DQ28 B10
    M11@ M11@ B9 NMDA4 M11@ M11@ B9 NMDA60
    NMRASA# DQ29 NMDA6 NMRASA# DQ29 NMDA56
    <14> NMRASA# M2 RAS# DQ30 C9 M2 RAS# DQ30 C9
    1 NMCASA# NMDA7 1 NMCASA# NMDA59
    <14> NMCASA# L2 CAS# DQ31 B8 L2 CAS# DQ31 B8
    2

    2
    NMWEA# L3 NMWEA# L3
    0.1U_0402_16V4Z <14> NMWEA# NMCSA0# WE# 0.1U_0402_16V4Z NMCSA0# WE#
    <14> NMCSA0# N2 CS# N2 CS#
    VDDQ C3 +2.5VS VDDQ C3 +2.5VS
    NMCKEA N12 C5 NMCKEA N12 C5
    <14> NMCKEA CKE VDDQ CKE VDDQ
    VDDQ C7 VDDQ C7
    NMCLKA0 M11 C8 NMCLKA1 M11 C8
    <14> NMCLKA0 CK VDDQ <14> NMCLKA1 CK VDDQ
    M12 CK# VDDQ C10 M12 CK# VDDQ C10
    VDDQ C12 VDDQ C12
    C411 R360 1 M11@ 2 56.2_0402_1% C4 E3 C342 R322 1 M11@ 2 56.2_0402_1% C4 E3
    NC VDDQ NC VDDQ
    1 2 C11 NC VDDQ E12 1 2 C11 NC VDDQ E12
    M11@ R355 1 M11@ 2 56.2_0402_1% H4 F4 M11@ R319 1 M11@ 2 56.2_0402_1% H4 F4
    0.1U_0402_16V4Z NC VDDQ 0.1U_0402_16V4Z NC VDDQ
    H11 NC VDDQ F11 H11 NC VDDQ F11
    L12 NC VDDQ G4 L12 NC VDDQ G4
    NMCLKA0# L13 G11 NMCLKA1# L13 G11
    <14> NMCLKA0# NC VDDQ <14> NMCLKA1# NC VDDQ
    M3 NC VDDQ J4 M3 NC VDDQ J4
    B NMCSA1# M4 J11 NMCSA1# M4 J11 B
    <14> NMCSA1# NC VDDQ NC VDDQ
    N3 NC VDDQ K4 N3 NC VDDQ K4
    VDDQ K11 VDDQ K11
    E7 VSS E7 VSS
    E8 VSS VDD D7 E8 VSS VDD D7
    E10 VSS VDD D8 E10 VSS VDD D8
    K6 VSS VDD E4 K6 VSS VDD E4
    K7 VSS VDD E11 K7 VSS VDD E11
    K8 VSS VDD L4 K8 VSS VDD L4
    K9 VSS VDD L7 K9 VSS VDD L7
    L5 VSS VDD L8 L5 VSS VDD L8
    L10 VSS VDD L11 L10 VSS VDD L11
    E5 VSS E5 VSS
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH

    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    HY5DU573222AFM-33_FBGA144 HY5DU573222AFM-33_FBGA144
    F6
    F7
    F8
    F9
    G6
    G7
    G8
    G9
    H6
    H7
    H8
    H9
    J6
    J7
    J8
    J9

    F6
    F7
    F8
    F9
    G6
    G7
    G8
    G9
    H6
    H7
    H8
    H9
    J6
    J7
    J8
    J9
    M11@ M11@

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VGA DDR CHANNEL A
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 17 of 47


    5 4 3 2 1
    5 4 3 2 1

    +2.5VS
    +2.5VS

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z

    22U_1206_16V4Z_V1

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.01U_0402_16V7K

    0.01U_0402_16V7K

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    C292 C298 C317 C304 C318 C308 C297 C319 C315 C293 C314 C300 C306 C316 C305 C299 C312 C303
    M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@
    22U_1206_16V4Z_V1
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z


    D D

    G10

    G10
    D10
    D11

    H10

    D10
    D11

    H10
    B11

    K10

    B11

    K10
    F10

    F10
    J10

    J10
    G5

    G5
    D4
    D5
    D6
    D9

    H5

    D4
    D5
    D6
    D9

    H5
    B4

    E6
    E9

    K5

    B4

    E6
    E9

    K5
    F5

    F5
    J5

    J5
    U2 U1

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    NMDB[0..63]
    <14> NMDB[0..63]
    NMAB[0..13]
    <14> NMAB[0..13]
    NMAB0 N5 B7 NMDB7 NMAB0 N5 B7 NMDB38
    NDQMB[0..7] NMAB1 A0 DQ0 NMDB4 NMAB1 A0 DQ0 NMDB39
    <14> NDQMB[0..7] N6 A1 DQ1 C6 N6 A1 DQ1 C6
    NMAB2 M6 B6 NMDB6 NMAB2 M6 B6 NMDB37
    NDQSB[0..7] NMAB3 A2 DQ2 NMDB5 NMAB3 A2 DQ2 NMDB36
    <14> NDQSB[0..7] N7 A3 DQ3 B5 N7 A3 DQ3 B5
    NMAB4 N8 C2 NMDB0 NMAB4 N8 C2 NMDB34
    NMAB5 A4 DQ4 NMDB1 NMAB5 A4 DQ4 NMDB35
    M9 A5 DQ5 D3 M9 A5 DQ5 D3
    NMAB6 N9 D2 NMDB2 NMAB6 N9 D2 NMDB33
    NMAB7 A6 DQ6 NMDB3 NMAB7 A6 DQ6 NMDB32
    N10 A7 DQ7 E2 N10 A7 DQ7 E2
    NMAB8 N11 K13 NMDB24 NMAB8 N11 K13 NMDB63
    NMAB9 A8/AP DQ8 NMDB26 NMAB9 A8/AP DQ8 NMDB62
    M8 A9 DQ9 K12 M8 A9 DQ9 K12
    NMAB10 L6 J13 NMDB29 NMAB10 L6 J13 NMDB60
    NMAB11 A10 DQ10 NMDB31 NMAB11 A10 DQ10 NMDB61
    M7 A11 DQ11 J12 M7 A11 DQ11 J12
    NMAB12 N4 G13 NMDB30 NMAB12 N4 G13 NMDB56
    NMAB13 BA0 DQ12 NMDB28 NMAB13 BA0 DQ12 NMDB58
    M5 BA1 DQ13 G12 M5 BA1 DQ13 G12
    F13 NMDB25 F13 NMDB59
    NDQMB0 DQ14 NMDB27 NDQMB4 DQ14 NMDB57
    B3 DM0 DQ15 F12 B3 DM0 DQ15 F12
    C NDQMB3 NMDB14 NDQMB7 NMDB47 C
    H12 DM1 DQ16 F3 H12 DM1 DQ16 F3
    +2.5VS NDQMB1 H3 F2 NMDB15 +2.5VS NDQMB5 H3 F2 NMDB45
    NDQMB2 DM2 DQ17 NMDB13 NDQMB6 DM2 DQ17 NMDB46
    B12 DM3 DQ18 G3 B12 DM3 DQ18 G3
    G2 NMDB12 G2 NMDB44
    DQ19 DQ19
    1

    1
    NDQSB0 B2 J3 NMDB9 NDQSB4 B2 J3 NMDB40
    R13 NDQSB3 DQS0 DQ20 NMDB11 R15 NDQSB7 DQS0 DQ20 NMDB43
    H13 DQS1 DQ21 J2 H13 DQS1 DQ21 J2
    M11@ NDQSB1 H2 K2 NMDB8 M11@ NDQSB5 H2 K2 NMDB41
    1K_0402_1% NDQSB2 DQS2 DQ22 NMDB10 1K_0402_1% NDQSB6 DQS2 DQ22 NMDB42
    B13 DQS3 DQ23 K3 B13 DQS3 DQ23 K3
    E13 NMDB21 E13 NMDB52
    DQ24 DQ24
    2

    2
    20mil VR_VREF_3 N13 D13 NMDB23 20mil VR_VREF_4 N13 D13 NMDB54
    VREF DQ25 NMDB22 VREF DQ25 NMDB55
    M13 MCL DQ26 D12 M13 MCL DQ26 D12
    1

    1
    NMDB20 NMDB53
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    2 L9 RFU1 DQ27 C13 2 L9 RFU1 DQ27 C13
    R17 C9 M10 B10 NMDB16 R16 C8 M10 B10 NMDB51
    M11@ M11@ RFU2 DQ28 NMDB18 M11@ M11@ RFU2 DQ28 NMDB50
    DQ29 B9 DQ29 B9
    1K_0402_1% NMRASB# M2 C9 NMDB17 1K_0402_1% NMRASB# M2 C9 NMDB48
    1 <14> NMRASB# NMCASB# RAS# DQ30 NMDB19 1 NMCASB# RAS# DQ30 NMDB49
    <14> NMCASB# L2 CAS# DQ31 B8 L2 CAS# DQ31 B8
    2

    2
    NMWEB# L3 NMWEB# L3
    <14> NMWEB# NMCSB0# WE# NMCSB0# WE#
    <14> NMCSB0# N2 CS# N2 CS#
    VDDQ C3 +2.5VS VDDQ C3 +2.5VS
    NMCKEB N12 C5 NMCKEB N12 C5
    <14> NMCKEB CKE VDDQ CKE VDDQ
    VDDQ C7 VDDQ C7
    NMCLKB0 M11 C8 NMCLKB1 M11 C8
    <14> NMCLKB0 CK VDDQ <14> NMCLKB1 CK VDDQ
    M12 CK# VDDQ C10 M12 CK# VDDQ C10
    56.2_0402_1% C12 56.2_0402_1% C12
    C283 R271 1 M11@ 2 VDDQ C282 R274 1 M11@ 2 VDDQ
    C4 NC VDDQ E3 C4 NC VDDQ E3
    1 2 C11 NC VDDQ E12 1 2 C11 NC VDDQ E12
    M11@ 1 M11@ 2 H4 F4 M11@ 1 M11@ 2 H4 F4
    0.1U_0402_16V4Z R272 56.2_0402_1% NC VDDQ 0.1U_0402_16V4Z R275 56.2_0402_1% NC VDDQ
    H11 NC VDDQ F11 H11 NC VDDQ F11
    L12 NC VDDQ G4 L12 NC VDDQ G4
    NMCLKB0# L13 G11 NMCLKB1# L13 G11
    <14> NMCLKB0# NC VDDQ <14> NMCLKB1# NC VDDQ
    M3 NC VDDQ J4 M3 NC VDDQ J4
    B NMCSB1# M4 J11 NMCSB1# M4 J11 B
    <14> NMCSB1# NC VDDQ NC VDDQ
    N3 NC VDDQ K4 N3 NC VDDQ K4
    VDDQ K11 VDDQ K11
    E7 VSS E7 VSS
    E8 VSS VDD D7 E8 VSS VDD D7
    E10 VSS VDD D8 E10 VSS VDD D8
    K6 VSS VDD E4 K6 VSS VDD E4
    K7 VSS VDD E11 K7 VSS VDD E11
    K8 VSS VDD L4 K8 VSS VDD L4
    K9 VSS VDD L7 K9 VSS VDD L7
    L5 VSS VDD L8 L5 VSS VDD L8
    L10 VSS VDD L11 L10 VSS VDD L11
    E5 VSS E5 VSS
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH

    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    VSS TH
    HY5DU573222AFM-33_FBGA144 HY5DU573222AFM-33_FBGA144
    F6
    F7
    F8
    F9
    G6
    G7
    G8
    G9
    H6
    H7
    H8
    H9
    J6
    J7
    J8
    J9

    F6
    F7
    F8
    F9
    G6
    G7
    G8
    G9
    H6
    H7
    H8
    H9
    J6
    J7
    J8
    J9
    M11@ M11@

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VGA DDR CHANNEL B
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 18 of 47


    5 4 3 2 1
    A B C D E

    TV Encoder
    remove this page when use M11P
    DVOC_D[0..11]
    1 <7,13> DVOC_D[0..11] 1

    21
    22
    24
    25
    27
    28
    30
    31
    U37
    DVOC_D11 50 9

    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    DVOC_D10 D11 NC
    51 D10
    DVOC_D9 52 47
    DVOC_D8 D9 BCO
    53 D8
    DVOC_D7 54 48
    DVOC_D6 D7 C/H Sync
    55 D6
    DVOC_D5 58 36 R397 75_0402_1% R605 75_0402_1%
    DVOC_D4 D5 CVBS UMA@ UMA@
    59 D4
    DVOC_D3 60 37 7011_TV_LUMA
    D3 Y/G 7011_TV_LUMA <21>
    DVOC_D2 61
    DVOC_D1 D2 7011_TV_CRMA
    62 D1 C/R/V 38 7011_TV_CRMA <21>
    DVOC_D0 63 D0 R396 75_0402_1% R606 75_0402_1%
    CVBS/B/U 39
    56 UMA@ UMA@
    <7,13> DVOC_CLK# XCLK*
    <7,13> DVOC_CLK 57 XCLK DVDD0 1 +3VS
    DVDD1 12
    2 NC DVDD2 49

    R386 UMA@ 0_0402_5% 46 6


    <7,13> DVOBC_CLKINT Pout/DET# DGND0 +3VS
    DGND1 11
    <7,13> DVOC_HSYNC 4 H DGND2 64
    5 V
    Q34 <7,13> DVOC_VSYNC
    DVDDV 45
    2N7002_SOT23 13
    <7,13,22,25,27,28,30> PCIRST# RESET* +1.5VS
    23 C468 C487 C480 C470 C485 C464
    2 NC UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ 2
    S

    <7,13> MI2CDATA 3 1 14 SD NC 29
    UMA@ 15 20 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    Q33 SC NC 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    NC 26
    2N7002_SOT23 GPIO1 7 32
    G

    GPIO1 NC
    2

    +3VS GPIO0
    S

    <7,13> MI2CCLK 3 1 8 GPIO0


    UMA@ R393 I2C Address = 1110110X 18
    AVDD0 +3VS
    @ 10 44
    +3VS R410 AS AVDD1
    16
    G

    AGND0
    2

    UMA@ 10K_0402_5% ISET 35 17


    10K_0402_5% With Wide & Short Trace ISET AGND1
    AGND2 41
    R395 19 33
    NC VDD

    XI/FIN
    1.5K_0402_5% R391 R398 34
    UMA@ UMA@ 140_0402_1% GND0
    3 40

    XO
    330_0402_5% UMA@ VREF GND1
    R404 CH7011A-T_LQFP64

    42

    43
    10K_0402_5% UMA@
    UMA@
    R394
    4.7K_0402_5% +1.5VS
    UMA@
    Y4
    +3VS
    1 2
    R384 UMA@
    10K_0402_1%
    UMA@ 14.318MHZ_16PF_DSX840GA
    UMA@
    C477 UMA@ C471
    CH7011_VREF 22P_0402_50V8J 22P_0402_50V8J
    +3VS

    R385
    3 UMA@C469 10K_0402_1% 3
    0.1U_0402_16V4Z UMA@ R389
    10K_0402_5%
    @

    GPIO1 GPIO0 Pull High: PAL


    Pull Low: NTSC*
    UMA@
    C472 R388
    0.1U_0402_16V4Z 330_0402_5%
    UMA@

    4 4

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TV Encoder CH7011A
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL20 LA-2461 0.3

    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期三, 八月 04, 2004 Sheet 19 of 47
    A B C D E
    5 4 3 2 1

    +12VALW
    +3VS
    LCD CONN.
    LCD POWER CIRCUIT VGS(th)= 0.95V,
    ID(max)=2.1A, Width: 40mils

    2
    1 JP6
    RDS(on)= 0.07OHm D30 INVPWR_B+ 16 1
    +LCDVDD R20 +3VS 16 1 INVPWR_B+
    100K_0402_5%
    C10 2DAC_BRIG <34> DAC_BRIG
    DAC_BRIG 17 17 2 2 DISPOFF#
    +5VALWP 4.7U_0805_10V4Z INVT_PWM +LCDVDD_LCD
    D 1 <34> INVT_PWM 18 18 3 3 1 2 +LCDVDD
    2

    1
    3INVT_PWM 1 2 +3VS_LCD 19 19 4 4 R19 0_1206_5%

    1
    2 Q2 R294 0_0805_5% LCD_CLK 20 5 LCD_DATA
    20 5

    2
    G SI2302DS_SOT23 SM05_SOT23 1 21 6
    21 6

    2
    R14 R293 1 S TZCLK- 22 7 TXCLK+
    22 7

    3
    100_0402_5% 100K_0402_5% C301 TZCLK+ 23 8 TXCLK-
    R18 C15 +LCDVDD 0.1U_0402_16V4Z 23 8
    24 24 9 9
    0.047U_0402_16V7K 2 TZOUT1- TXOUT2+
    D
    150K_0402_5% 2
    width = 80mil 25 25 10 10 D

    1 2

    1
    TZOUT1+ 26 11 TXOUT2-
    D D 26 11

    1
    1
    TZOUT2+ 27 12 TXOUT1-
    TZOUT2- 27 12 TXOUT1+
    2 Q24 2 Q1 1 1 28 28 13 13
    G 2N7002_SOT23 G 2N7002_SOT23 TZOUT0+ 29 14 TXOUT0-
    C11 C14 TZOUT0- 29 14 TXOUT0+
    S S 30 15
    30 15
    3

    3
    4.7U_0805_10V4Z
    2
    0.1U_0402_16V4Z 2 ACES_87216-3002

    1
    Q3
    DTC124EK_SC59

    ENVDD 2 M11_TXOUT0- R266 1 M11@ 2 0_0402_5% TXOUT0-


    <13> ENVDD <13> M11_TXOUT0-
    M11_TXOUT0+ R267 1 M11@ 2 0_0402_5% TXOUT0+
    <13> M11_TXOUT0+
    1 2 M11_TXOUT1- R264 1 M11@ 2 0_0402_5% TXOUT1-
    <7> GMCH_ENVDD <13> M11_TXOUT1-
    R22 UMA@ 0_0402_5% M11_TXOUT1+ R265 1 M11@ 2 0_0402_5% TXOUT1+
    <13> M11_TXOUT1+
    M11_TXOUT2- R263 1 M11@ 2 0_0402_5% TXOUT2-
    <13> M11_TXOUT2-
    3

    M11_TXOUT2+ R262 1 M11@ 2 0_0402_5% TXOUT2+


    <13> M11_TXOUT2+
    M11_TXCLK- R261 1 M11@ 2 0_0402_5% TXCLK-
    <13> M11_TXCLK-
    M11_TXCLK+ R260 M11@ 0_0402_5% TXCLK+
    reserved for GMCH <13>
    <13>
    M11_TXCLK+
    M11_TZOUT0-
    M11_TZOUT0- R24
    1
    1 M11@
    2
    2 0_0402_5% TZOUT0-
    M11_TZOUT0+ R25 1 M11@ 2 0_0402_5% TZOUT0+
    INVPWR_B+ +LCDVDD <13> M11_TZOUT0+
    M11_TZOUT1- R29 1 M11@ 2 0_0402_5% TZOUT1-
    +3VS <13> M11_TZOUT1-
    width = 60mil M11_TZOUT1+ R28 1 M11@ 2 0_0402_5% TZOUT1+
    <13> M11_TZOUT1+
    M11_TZOUT2- R26 1 M11@ 2 0_0402_5% TZOUT2-
    <13> M11_TZOUT2-
    1 2 M11_TZOUT2+ R27 1 M11@ 2 0_0402_5% TZOUT2+
    B+ <13> M11_TZOUT2+

    1
    L5 CHB2012U170_0805 M11_TZCLK- R31 1 M11@ 2 0_0402_5% TZCLK-
    <13> M11_TZCLK-
    R21 1 2 1 M11_TZCLK+ R30 1 M11@ 2 0_0402_5% TZCLK+
    <13> M11_TZCLK+
    4.7K_0402_5% 1 L4 CHB2012U170_0805 C17 C18
    From EC C16 0.1U_0402_16V4Z
    <13> M11_LCD_DATA
    R259 1 M11@ 2 0_0402_5% LCD_DATA
    2

    2
    1 2 DISPOFF# 68P_0402_50V8K 10U_0805_10V4Z R32 1 M11@ 2 0_0402_5% LCD_CLK
    C <34> BKOFF# 2 <13> M11_LCD_CLK C
    D6 RB751V_SOD323

    For ATI M11P

    GMCH_TXOUT0- R289 1 UMA@ 2 0_0402_5% TXOUT0-


    <7> GMCH_TXOUT0-
    GMCH_TXOUT0+ R290 1 UMA@ 2 0_0402_5% TXOUT0+
    <7> GMCH_TXOUT0+
    GMCH_TXOUT1- R287 1 UMA@ 2 0_0402_5% TXOUT1-
    <7> GMCH_TXOUT1-
    GMCH_TXOUT1+ R288 1 UMA@ 2 0_0402_5% TXOUT1+
    <7> GMCH_TXOUT1+
    GMCH_TXOUT2- R286 1 UMA@ 2 0_0402_5% TXOUT2-
    <7> GMCH_TXOUT2-
    GMCH_TXOUT2+ R285 1 UMA@ 2 0_0402_5% TXOUT2+
    <7> GMCH_TXOUT2+
    GMCH_TXCLK- R284 1 UMA@ 2 0_0402_5% TXCLK-
    <7> GMCH_TXCLK-
    GMCH_TXCLK+ R283 1 UMA@ 2 0_0402_5% TXCLK+
    <7> GMCH_TXCLK+
    GMCH_TZOUT0- R309 1 UMA@ 2 0_0402_5% TZOUT0-
    <7> GMCH_TZOUT0-
    GMCH_TZOUT0+ R308 1 UMA@ 2 0_0402_5% TZOUT0+
    <7> GMCH_TZOUT0+
    GMCH_TZOUT1- R304 1 UMA@ 2 0_0402_5% TZOUT1-
    <7> GMCH_TZOUT1-
    GMCH_TZOUT1+ R305 1 UMA@ 2 0_0402_5% TZOUT1+
    <7> GMCH_TZOUT1+
    GMCH_TZOUT2- R307 1 UMA@ 2 0_0402_5% TZOUT2-
    <7> GMCH_TZOUT2-
    GMCH_TZOUT2+ R306 1 UMA@ 2 0_0402_5% TZOUT2+
    <7> GMCH_TZOUT2+
    GMCH_TZCLK- R302 1 UMA@ 2 0_0402_5% TZCLK-
    <7> GMCH_TZCLK-
    GMCH_TZCLK+ R303 1 UMA@ 2 0_0402_5% TZCLK+
    <7> GMCH_TZCLK+

    R282 1 UMA@ 2 0_0402_5% LCD_DATA


    <7> GMCH_LCD_DATA
    R301 1 UMA@ 2 0_0402_5% LCD_CLK
    <7> GMCH_LCD_CLK
    B B

    For GMCH

    +3VS

    LCD_DATA R424 1 2 2.2K_0402_5%


    LCD_CLK R299 1 2 2.2K_0402_5%

    A A

    Compal Electronics, Inc.


    Title
    LCD CONN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 20 of 47
    5 4 3 2 1
    A B C D E

    CRT Connector +5VS +R_CRT_VCC +CRT_VCC


    R3,R5,R6,R9,R23,R291 D4
    reserved for GMCH W=40mils

    1
    D1 @ D2 @ D3 @ 2 1 F1
    +3VS 1 M11@
    2
    R11 0_0603_5% RB411D_SOT23 POLYSWITCH_1A
    +1.5VS 1 UMA@ 2 1
    R4 1 M11@ 2 R12 0_0603_5%
    <13> M11_CRT_R
    R8 2 M11@ 1 0_0402_5% DAN217_SC59 DAN217_SC59 DAN217_SC59 C2

    3
    75_0402_1% 0.1U_0402_16V4Z
    R5 CRT_R
    R12 reserved for GMCH 2
    <7> GMCH_CRT_R 1 UMA@ 2
    1
    R9 2 UMA@ 1 0_0402_5% JP2 1
    75_0402_1% FOX_DZ11A91-L7

    R7 1 M11@ 2 6
    <13> M11_CRT_G
    R1 2 M11@ 1 0_0402_5% 11
    75_0402_1% 1 2 CRT_R_L 1
    R6 1 UMA@ 2 CRT_G L2 7
    <7> GMCH_CRT_G
    R23 2 UMA@ 1 0_0402_5% FCM2012C-800_0805 12
    75_0402_1% 1 2 CRT_G_L 2
    L1 +3VS
    8
    R2 1 M11@ 2 FCM2012C-800_0805 13 +CRT_VCC
    <13> M11_CRT_B +3VS
    R10 2 M11@ 1 0_0402_5% CRT_B 1 2 CRT_B_L 3
    75_0402_1% L3 9
    R3 1 UMA@ 2 FCM2012C-800_0805 3.3P for GMCH 14 R241 R240 R243 R257
    <7> GMCH_CRT_B DDC_MD2
    R291 2 UMA@ 1 0_0402_5% 1 1 1 1 1 1 4

    1
    75_0402_1%

    2.2K_0402_5%

    2.2K_0402_5%

    4.7K_0402_5%

    4.7K_0402_5%
    10
    C1 C7 C3 C4 C5 C6 15
    5
    2 2 2 2 2 2
    ATi suggest use precision termination

    2
    2
    8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K

    G
    8P_0402_50V8K 8P_0402_50V8K
    1 2 HSYNC_L 1 3 CRT_DDC_DATA 2 M11@ 1
    L12 FCM1608C-121T_0603 0_0402_5% R234 M11_CRT_DDC_DATA <13>

    S
    +CRT_VCC Q22 2 UMA@ 1
    GMCH_CRT_DATA <7>

    2
    C265 1 2 VSYNC_L 2N7002_SOT23 0_0402_5% R242

    G
    1 2 2 1 L13 FCM1608C-121T_0603
    0.1U_0402_16V4Z R250 10K_0402_5% 1 3 CRT_DDC_CLK 2 M11@ 1
    0_0402_5% R248 M11_CRT_DDC_CLK <13>
    1 1 1 1 1

    S
    5
    1
    U25 C262 C261 C260 C263 C259 Q23 2 UMA@ 1
    2N7002_SOT23 0_0402_5% R252 GMCH_CRT_CLK <7>
    OE#
    P

    CRT_HSYNC2 HS YNC

    10P_0402_50V8K

    10P_0402_50V8K

    68P_0402_50V8K

    68P_0402_50V8K
    1 M11@ 2

    100P_0402_50V8J
    <13> M11_CRT_HSYNC A Y 4
    2 R246 0_0402_5% 2 2 2 2 2 2
    R242,R252 reserved for GMCH
    G

    <7> GMCH_CRT_HSYNC 1 UMA@ 2 SN74AHCT1G125GW_SOT353-5 33P for GMCH


    R247 0_0402_5%
    3

    +CRT_VCC

    1 2
    C266
    5
    1

    0.1U_0402_16V4Z
    OE#
    P

    1 M11@ 2 CRT_VSYNC 2 4 VS YNC


    <13> M11_CRT_VSYNC A Y
    R245 0_0402_5%
    G

    <7> GMCH_CRT_VSYNC 1 UMA@ 2 U24


    R244 0_0402_5% SN74AHCT1G125GW_SOT353-5
    3

    R247,R244 reserved for GMCH

    TV-Out Connector

    DAN217_SC59

    DAN217_SC59
    1

    1
    D18 @ D17 @

    +3VS

    3
    3 3

    R256,R253 reserved for TV encoder


    1 2 @ 47P_0402_50V8J S-Video
    C272
    <13> M11_TV_LUMA 1 M11@ 2 TV_LUMA 1 2 LUMA_L 4P Normal Type
    R255 0_0402_5% L15 FCM1608C-121T_0603 JP3
    <19> 7011_TV_LUMA 1 UMA@ 2 1 1
    R256 0_0402_5% 1 2 @ 47P_0402_50V8J 2 5
    C271 2 GND
    3 3 GND 6
    1 M11@ 2 TV_CRMA 1 2 CRMA_L 4
    <13> M11_TV_CRMA 4
    R254 0_0402_5% L14 FCM1608C-121T_0603
    <19> 7011_TV_CRMA 1 UMA@ 2
    R253 0_0402_5% SUYIN_030336FR004T115ZU

    82P_0402_50V8J

    82P_0402_50V8J
    1

    1
    75_0402_1%

    75_0402_1%

    82P_0402_50V8J

    82P_0402_50V8J

    R251 R249 1 1 1 1
    @ @ C274 C273 C269 C268

    2 2 2 2
    2

    For M11P, Capacitance is 82pF For M11P, Capacitance is 82pF


    For CH7011A, Capacitance is 100pF For CH7011A, Capacitance is 270pF

    4 4

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CRT & TV-OUT Connector
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 21 of 47
    A B C D E
    A B C D

    U34A

    PCI_AD0 H5 AD0
    ICH4 INTRUDER# W6 INTRUDER#
    PCI_AD[0..31] PCI_AD1 J3 AC3 SMLINK0
    <26,27,28,30> PCI_AD[0..31] AD1 SMLINK0
    PCI_AD2 H3 AB1 SMLINK1
    AD2 SMLINK1
    PCI_AD3
    PCI_AD4
    K1
    G5
    AD3 SM I/F SMB_CLK AC4
    AB4
    SMB_CLK
    SMB_DATA
    SMB_CLK <10,12>
    AD4 SMB_DATA SMB_DATA <10,12>
    PCI_AD5 J4 AA5 2 1
    AD5 SMB_ALERT#/GPI11 ACIN <34,36,38>
    PCI_AD6 H4 RB751V_SOD323 D29
    PCI_AD7 AD6
    J5 AD7 1 2 +3VALW
    1 PCI_AD8 R101 100K_0402_5% 1
    K2 AD8
    PCI_AD9 G2 Y22
    AD9 A20GATE GATEA20 <34>
    CLK_PCI_ICH PCI_AD10 L1 AB23
    AD10 A20M# H_A20M# <4>
    PCI_AD11 G4 U23
    AD11 DPSLP# H_DPSLP# <4,7>
    1

    PCI_AD12 L2 AA21 1 R133 2 H_FERR#


    AD12 FERR# H_FERR# <4>
    R86 PCI_AD13 H2 W21 56_0402_5%
    AD13 IGNNE# H_IGNNE# <4>
    PCI_AD14 L3 V22
    AD14 INIT# H_INIT# <4>
    @ 10_0402_5% PCI_AD15
    PCI_AD16
    F5
    F4
    AD15 CPU I/F INTR AB22
    V21
    H_INTR <4>
    AD16 NMI H_NMI <4>
    2

    1 PCI_AD17 N1 Y23
    AD17 CPU_PWRGOOD H_CPUPWRGD <4>
    C59 PCI_AD18 E5 U22 +1.5VS
    AD18 RCIN# RC# <34>
    PCI_AD19 N2 U21
    AD19 SLP# H_CPUSLP# <4>
    @ 15P_0402_50V8J PCI_AD20 E3 W23
    2 AD20 SMI# H_SMI# <4>
    PCI_AD21 N3 V23 HUB_RCOMP_ICH 1 2
    AD21 STPCLK# H_STPCLK# <4>
    PCI_AD22 E4 R399 48.7_0402_1%
    PCI_AD23 AD22
    M5 AD23
    PCI_AD24 E2
    CLK_ICH_66M PCI_AD25 AD24 HUB_PD0
    P1 AD25 HI0 L19
    PCI_AD26 E1 L20 HUB_PD1 HUB_PD[0..10]
    AD26 HI1 HUB_PD[0..10] <6>
    1

    PCI_AD27 P2 M19 HUB_PD2


    R132 PCI_AD28 AD27 HI2 HUB_PD3 HUB_VREF
    D3 AD28 HI3 M21 1 2
    @ 22_0402_5% PCI_AD29 R1 P19 HUB_PD4 C484 0.01U_0402_16V7K
    PCI_AD30 AD29 HI4 HUB_PD5 HUB_VSW ING 1
    D2 AD30 HI5 R19 2
    PCI_AD31 P4 T20 HUB_PD6 C482 0.01U_0402_16V7K

    PCI I/F
    AD31 HI6
    2

    1 R20 HUB_PD7
    HI7 HUB_PD8
    HI8 P23
    C95 PCI_CBE#0 J2 L22 HUB_PD9
    <26,27,28,30> PCI_CBE#0 C/BE#0 HI9
    @10P_0402_50V8K
    2 <26,27,28,30> PCI_CBE#1
    PCI_CBE#1
    PCI_CBE#2
    K4
    M4
    C/BE#1 HUB I/F HI10 N22
    K21
    HUB_PD10
    1
    R130
    2 56_0402_5%
    <26,27,28,30> PCI_CBE#2 C/BE#2 HI11
    PCI_CBE#3 N4
    <26,27,28,30> PCI_CBE#3 C/BE#3
    T21 CLK_ICH_66M
    CLK66 CLK_ICH_66M <12>
    PCI_REQ#0 B1 +3VS
    2 <27> PCI_REQ#0 REQ#0
    PCI_REQ#1 A2 P21 2
    <26> PCI_REQ#1 REQ#1 HI_STB HUB_PSTRB <6>
    PCI_REQ#2 B3 N20
    <28> PCI_REQ#2 REQ#2 HI_STB# HUB_PSTRB# <6>
    PCI_REQ#3 C7 SMB_CLK 1 2
    <30> PCI_REQ#3 REQ#3
    PCI_REQ#4 B6 R23 HUB_RCOMP_ICH R69
    <30> PCI_REQ#4 REQ#4 HICOMP
    M23 HUB_VREF 10K_0402_5%
    HUB_VREF HUB_VREF
    PCI_GNT#0 C1 R22 HUB_VSW ING SMB_DATA 1 2
    <27> PCI_GNT#0 GNT#0 HUB_VSWING HUB_VSWING
    PCI_GNT#1 E6 R73
    <26> PCI_GNT#1 GNT#1
    PCI_GNT#2 A7 10K_0402_5%
    <28> PCI_GNT#2 GNT#2
    PCI_GNT#3 B7 J19 APICCLK
    <30> PCI_GNT#3 GNT#3 APICCLK
    PCI_GNT#4 APICD0
    PCI Pullups <30> PCI_GNT#4 D6 GNT#4 APICD0 H19
    K20 APICD1
    CLK_PCI_ICH APICD1 PCI_PIRQA#

    Interrupt I/F
    <12> CLK_PCI_ICH P5 PCICLK PIRQA# D5 PCI_PIRQA# <13,28>
    C2 PCI_PIRQB#
    +3VS PIRQB# PCI_PIRQB# <28>
    PCI_FRAME# F1 B4 PCI_PIRQC#
    8.2K_1206_8P4R_5% <26,27,28,30> PCI_FRAME# FRAME# PIRQC#
    PCI_DEVSEL# M3 A3 PCI_PIRQD#
    <26,27,28,30> PCI_DEVSEL# DEVSEL# PIRQD#
    4 5 PCI_REQ#2 PCI _IRDY# L5 C8 PCI_PIRQE#
    <26,27,28,30> PCI_IRDY# IRDY# PIRQE#/GPI2 PCI_PIRQE# <27>
    3 6 PCI_PIRQD# G1 D7 PCI_PIRQF#
    <26,27,28,30> PCI_PAR PAR PIRQF#/GPI3 PCI_PIRQF# <26>
    4 2
    1
    7
    8
    PCI_PIRQH#
    PCI_PIRQC#
    <26,27,28,30> PCI_PERR#
    PCI_PERR#
    PCI_LOCK#
    L4
    M2
    PERR# PIRQG#/GPI4 C3
    C4
    PCI_PIRQG#
    PCI_PIRQH#
    PCI_PIRQG# <30>
    LOCK# PIRQH#/GPI5 PCI_PIRQH# <30>
    W2 AC13 PD_IRQ14
    RP40 PME# IRQ14 PD_IRQ14 <25>
    PCIRST# U5 AA19 SD_IRQ15
    <7,13,19,25,27,28,30> PCIRST# PCIRST# IRQ15 SD_IRQ15 <25>
    PCI_SERR# K5 J22 SIRQ
    8.2K_1206_8P4R_5% <26,28,30> PCI_SERR# SERR# SERIRQ SIRQ <28,33,34>
    PCI_STOP# F3
    <26,27,28,30> PCI_STOP# STOP#
    4 5 PCI_LOCK# PCI_TRDY# F2
    <26,27,28,30> PCI_TRDY# TRDY#
    3 6 PCI_DEVSEL# D10
    EE_CS
    1 2
    1
    7
    8
    PCI_PERR#
    PCI _IRDY#
    PCI_REQA#
    PCI_REQB#
    B5
    A6
    REQA#/GPI0 EEPROM I/F EE_IN D11
    A8 1 2
    PIDERST# REQB#/GPI1/REQ5# EE_OUT
    <25> PIDERST# E8 GNTA#/GPO16 EE_SHCLK C12
    RP37 SIDERST# C5 R96
    <25> SIDERST# GNTB#/GPO17/GNT5# @ 1K_0402_5%
    8.2K_1206_8P4R_5% A10
    PCI_PIRQF# LAN_RXD0
    4 5 LAN_RXD1 A9
    3 PCI_REQ#3 3
    3 6 LAN_RXD2 A11
    6 2
    1
    7
    8
    PCI_PIRQE#
    LAN_TXD0 B10
    C10 +RTCVCC
    RP42
    LAN I/F LAN_TXD1
    LAN_TXD2 A12
    C11 INTRUDER# 1 2
    LAN_CLK
    B11 R85
    8.2K_1206_8P4R_5% LAN_RSTSYNC 330K_0402_5%
    LAN_RST# Y5 1 2
    4 5 PCI_SERR#
    3 6 PCI_FRAME# R72
    2 2
    1
    7
    8
    PCI_TRDY#
    PCI_STOP#
    10K_0402_5%
    FW82801DBM_BGA421
    +VCCP
    RP38
    H_FERR# 1 2
    8.2K_1206_8P4R_5%
    R126
    4 5 PCI_PIRQG# 56_0402_5%
    3 6 PCI_PIRQB#
    +3VS
    3 2
    1
    7
    8
    PCI_REQ#0
    PCI_REQ#1

    RP39 +3VALW
    5

    2 1 PD_IRQ14 U32
    R376 SMLINK0 R87
    1 2
    P

    OE#

    8.2K_0402_5% PCIRST# 2 4 APICCLK 4.7K_0402_5%


    I O B_PCIRST# <26,33,34>
    2 1 SD_IRQ15 APICD0
    R83
    G

    R129 APICD1 SMLINK1 1 2


    8.2K_0402_5% @ 74LVC1G125GW_SOT3535 4.7K_0402_5%
    3

    2
    RP41
    8 1 PCI_PIRQA# R124 R122 R123
    7 2 PCI_REQA# 10K_0402_5% 10K_0402_5% 0_0402_5%
    5 6 3 PCI_REQ#4

    1
    4 PCI_REQB# 4
    5 4
    1 2
    8.2K_1206_8P4R_5% R331 0_0402_5%
    2 1 SIRQ
    R400
    8.2K_0402_5%
    Compal Electronics, Inc.
    Title
    1
    R97
    2 PIDERST#
    @ 1K_0402_5%
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ICH4-M(1/3) PCI/HUB/CPU/INT
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 22 of 47
    A B C D
    A B C D

    +3VS

    1
    R337

    10K_0402_5%
    1 2 PM_DPRSLPVR
    U34B

    2
    R131 100K_0402_5%

    <7,13> AGP_BUSY#
    AGP_BUSY# R2 AGPBUSY#
    ICH4 GPI7 R3
    1 SYSRST# EC_SMI# 1
    <4> ITP_DBRESET# Y3 SYSRST# GPI8 V4 EC_SMI# <34>
    +3VS PM_BATLOW# AB2 V5 SCI# +3VALW
    <34> PM_BATLOW# BATLOW# GPI12 SCI# <34>
    C3_STAT# T3 W3 EC_LID_OUT#
    <13> STP_AGP# C3_STAT# GPI13 EC_LID_OUT# <34>
    PM_CLKRUN# AC2
    GPIO V2

    14
    <26,30,33,34> PM_CLKRUN# CLKRUN# GPIO25 EC_FLASH# <35>
    2 1 LPC_DRQ#0 <45> PM_DPRSLPVR PM_DPRSLPVR V20 W1 U16D
    R63 10K_0402_5% DPRSLPVR GPIO27 SLP_S4#
    <34> PWRBTN_OUT# AA1 W4 12

    P
    +3VS PWRBTN# GPIO28 A
    <36> PM_POK AB6 PWROK O 11 PM_SLP_S5# <34>
    EC_RIOUT# Y1 SLP_S5# 13
    <34> EC_RIOUT# RI# B

    G
    2 1 PM_CLKRUN# <34> PM_RSMRST#
    PM_RSMRST# AA6
    W18
    RSMRST# PM AA13 PD_A0
    <12,34> SLP_S1# SLP_S1# PDA0 PD_A0 <25>

    7
    R67 10K_0402_5% <34> SLP_S3# Y4 AB13 PD_A1 SN74LVC08APW_TSSOP14
    SLP_S3# PDA1 PD_A1 <25>
    SLP_S4# Y2 W13 PD_A2
    SLP_S4# PDA2 PD_A2 <25>
    SLP_S5# AA2 Y13 PD_CS#1
    SLP_S5# PDCS1# PD_CS#1 <25>
    2 1 PM_RSMRST# W19 AB14 PD_CS#3
    <12,45> STP_CPU# STP_CPU# PDCS3# PD_CS#3 <25>
    R78 10K_0402_5% Y21
    <12> STP_PCI# RTCCLK STP_PCI# PD_DREQ
    <7> RTCCLK AA4 SUS_CLK PDDREQ AA11 PD_DREQ <25>
    SUS_STAT# AB3 Y12 PD_DACK#
    <13,35> SUS_STAT# SUS_STAT#/LPCPD# PDDACK# PD_DACK# <25> PD_D[0..15]
    1 2 RTCCLK EC_THRM# V1 AC12 PD_IOR#
    <34> EC_THRM# THRM# PDIOR# PD_IOR# <25> PD_D[0..15] <25>
    R70 @ 10K_0402_5% W12 PD_IOW#
    PDIOW# PD_IOW# <25>
    1 2 AB12 PD_PIORDY
    +3VS PIORDY PD_PIORDY <25> SD_D[0..15]
    R335 8.2K_0402_5%
    SD_D[0..15] <25>
    J21 AB11 PD_D0
    SSMUXSEL PDD0
    CPUPERF# Y20
    V19
    CPUPERF# IST PDD1 AC11
    Y10
    PD_D1
    PD_D2
    <7,12,45> VGATE VGATE/VRMPWRGD PDD2 PD_D3
    PDD3 AA10
    +VCCP
    AC97_BITCLK B8
    AC97 I/F PDD4 AA7
    AB8
    PD_D4
    PD_D5
    <31> AC97_BITCLK AC_BITCLK PDD5 PD_D6 CLK_ICH_14M
    <31> AC97_RST# C13 AC_RST# PDD6 Y8
    1 2 CPUPERF#
    <31> AC97_SDIN0
    AC97_SDIN0 D13 AC_SDATAIN0 IDE I/F PDD7 AA8 PD_D7

    1
    R125 AC97_SDIN1 A13 AB9 PD_D8
    8.2K_0402_5% <31> AC97_SDIN1 AC_SDATAIN1 PDD8 PD_D9
    B13 AC_SDATAIN2 PDD9 Y9
    ICH_AC_SDOUT D9 AC9 PD_D10 R402
    2 IC H_AC_SYNC AC_SDATAOUT PDD10 PD_D11 @ 22_0402_5% 2
    C9 AC_SYNC PDD11 W9
    AB10 PD_D12
    PDD12

    2
    +3VS W10 PD_D13 1
    LPC_AD0 PDD13 PD_D14
    <33,34> LPC_AD0 T2 LPC_AD0 PDD14 W11
    LPC_AD1 R4 Y11 PD_D15 C486
    <33,34> LPC_AD1 LPC_AD1 PDD15 10P_0402_50V8K
    R408 LPC_AD2 T4 @
    <33,34> LPC_AD2 LPC_AD2 2
    1 2
    @ 1K_0402_5%
    SB_SPKR
    <33,34> LPC_AD3
    LPC_AD3
    LPC_DRQ#0
    U2
    U3
    LPC_AD3 LPC I/F SDA0 AA20
    AC20
    SD_A0
    SD_A1
    SD_A0 <25>
    LPC_DRQ#0 SDA1 SD_A1 <25>
    +3VS <33> LPC_DRQ#1 LPC_DRQ#1 U4 AC21 SD_A2
    LPC_DRQ#1 SDA2 SD_A2 <25>
    LPC_FRAME# T5 AB21 SD_CS#1
    <33,34> LPC_FRAME# LPC_FRAME# SDCS1# SD_CS#1 <25>
    AC22 SD_CS#3
    SDCS3# SD_CS#3 <25>
    CLK_ICH_48M
    2 R100 1 ICH_AC_SDOUT
    SDDREQ AB18 SD_DREQ
    SD_DREQ <25>

    1
    @ 10K_0402_5% C20 AB19 SD_DACK#
    +3VS USBP0+ SDDACK# SD_DACK# <25>
    D20 Y18 SD_IOR# R128
    USBP0- SDIOR# SD_IOR# <25>
    A21 AA18 SD_IOW# 22_0402_5%
    USBP1+ SDIOW# SD_IOW# <25>
    B21 AC19 SD_SIORDY @
    USBP1- SIORDY SD_SIORDY <25>
    <35> USB20P2+ C18 USBP2+

    2
    2 R336 1 AGP_BUSY# D18 W17 SD_D0 1
    <35> USB20P2- USBP2- SDD0
    10K_0402_5% A19 AB17 SD_D1
    <35> USB20P3+ USBP3+ SDD1
    B19 W16 SD_D2 C101
    <35> USB20P3- USBP3- SDD2 10P_0402_50V8K
    C16 AC16 SD_D3 @
    <35> USB20P4+ USBP4+ SDD3 2
    +3VALW D16 W15 SD_D4
    <35> USB20P4- USBP4- SDD4
    A17 AB15 SD_D5
    USBP5+ SDD5
    RP43 B17 USBP5- USB I/F SDD6 W14
    AA14
    SD_D6
    SD_D7
    OVCUR#1 SDD7 SD_D8
    1 8 SDD8 Y14
    2 7 OVCUR#0 OVCUR#0 B15 AC15 SD_D9
    OVCUR#5 OVCUR#1 OC#0 SDD9 SD_D10
    3 6 C14 OC#1 SDD10 AA15
    4 5 OVCUR#2 A15 Y15 SD_D11
    <35> OVCUR#2 OC#2 SDD11
    OVCUR#3 B14 AB16 SD_D12
    <35> OVCUR#3 OC#3 SDD12
    10K_1206_8P4R_5% OVCUR#4 A14 Y16 SD_D13 +RTCVCC
    3 <35> OVCUR#4 OC#4 SDD13 3
    OVCUR#5 D14 AA17 SD_D14
    OC#5 SDD14
    1 2 EC_LID_OUT# SDD15 Y17 SD_D15
    R89 10K_0402_5% USB_RBIAS A23
    R403 USB_RBIAS
    1 2 PM_BATLOW# 2 1 B23 USB_RBIAS# 1 2
    R90 10K_0402_5% 1 R91
    22.6_0402_1%
    1 2 SCI# CLK14 J23 CLK_ICH_14M
    CLK_ICH_14M <12>
    R579 180K_0402_5%
    R98 10K_0402_5% F19 CLK_ICH_48M 2 1 2 1 C55
    CLK48 CLK_ICH_48M <12>
    J20 0.1U_0402_16V4Z
    GPIO32 RTC_RST# J1 1K_0402_5% 2
    G22 GPIO33 RTCRST# W7
    F20 JOPEN
    GPIO34
    G20
    F21
    GPIO35 CLOCK VBIAS Y6 VBIAS 1 2R_VBIAS 1
    R79
    2
    GPIO36 RTCX1 C381 1K_0402_5%
    H20 GPIO37 RTCX1 AC7
    F23 0.047U_0603_16V7K
    GPIO38
    H22
    G23
    GPIO39 GPIO RTCX2 AC6 RTCX2 1
    R354
    2
    GPIO40 10M_0402_5%
    H21 GPIO41
    F22 GPIO42 SPKR H23 SB_SPKR SB_SPKR <31>
    10M_0402_5%
    E23 GPIO43 1 2 2 1
    MISC THRMTRIP# W20 THRMTRIP# THRMTRIP# <4>
    R351 R350

    2
    1 1 @ 22M_0603_5%

    1
    C400 C417 R346
    15P_0402_50V8J 15P_0402_50V8J @ 2.4M_0603_1%

    IN
    OUT
    FW82801DBM_BGA421 2 2

    1
    NC

    NC
    R102
    0_0402_5%
    3

    2
    1 2 IC H_AC_SYNC Y3
    <31> AC97_SYNC
    32.768KHZ_12.5P_1TJS125DJ2A073
    4 ICH_AC_SDOUT 4
    <31> AC97_SDOUT 1 2
    1 1 R107
    0_0402_5%
    C66 C70
    22P_0402_50V8J @ @ 22P_0402_50V8J
    2 2

    Compal Electronics, Inc.


    Title

    ICH4-M(2/3) PM/AC97/USB/IDE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 23 of 47
    A B C D
    A B C D E F G H

    U34C +3VS

    D22 VSS0
    ICH4 VCC3.3_0 A5
    E10 AC17 +3VS +1.5VALW +3VS
    VSS1 VCC3.3_1
    E14 VSS2 VCC3.3_2 AC8
    E16 B2 10U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VSS3 VCC3.3_3
    E17 VSS4 VCC3.3_4 H18
    E18 VSS5 VCC3.3_5 H6 1 1 1 1 1 1 1 1 1 1 1 1 1
    E19 J1 C466 C353 C352 C99 C65 C49 C35 C46 C91
    VSS6 VCC3.3_6 C72 C98 C90 C48
    E21 VSS7 VCC3.3_7 J18

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    E22 VSS8 VCC3.3_8 K6
    1 2 2 2 2 2 2 2 2 2 2 2 2 2 1
    F8 VSS9 VCC3.3_9 M10
    G19 VSS10 VCC3.3_10 P12
    G21 P6 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VSS11 VCC3.3_11
    G3 VSS12 VCC3.3_12 U1
    G6 VSS13 VCC3.3_13 V10
    H1 VSS14 VCC3.3_14 V16
    J6 VSS15 VCC3.3_15 V18
    K11 +3VALW
    VSS16 +1.5VS +1.5VS +1.5VS
    K13 VSS17
    K19 VSS18 VCCSUS3.3_0 E11
    K23 VSS19 VCCSUS3.3_1 F10
    K3 VSS20 VCCSUS3.3_2 F15
    L10 VSS21 VCCSUS3.3_3 F16 1 1 1 1 1 1
    L11 VSS22 VCCSUS3.3_4 F17
    L12 F18 C84 C73 C68 C56 C67 C85
    VSS23 VCCSUS3.3_5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
    L13 VSS24 VCCSUS3.3_6 K14
    2 2 2 2 2 2
    L14 VSS25 VCCSUS3.3_7 V7
    L21 VSS26 VCCSUS3.3_8 V8
    M1 VSS27 VCCSUS3.3_9 V9
    M11 VSS28 +1.5VS
    VCC1.5 power place VCCLAN1.5 power place VCCPLL power place
    M12 VSS29
    M13
    M20
    VSS30 GND POWER K10
    VSS31 VCC1.5_0
    M22 VSS32 VCC1.5_1 K12
    N10 VSS33 VCC1.5_2 K18
    N11 K22 +3VALW +1.5VS
    VSS34 VCC1.5_3 +VCCP
    N12 VSS35 VCC1.5_4 P10
    N13 T18 1U_0603_10V4Z 0.1U_0402_16V4Z
    VSS36 VCC1.5_5
    N14 VSS37 VCC1.5_6 U19
    N19 VSS38 VCC1.5_7 V14 1 1 1 1 1 1 1
    N21 +1.5VALW
    VSS39 C483 C100 C82
    N23 C460 C89 C83 C60 0.1U_0402_16V4Z
    2 VSS40 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
    N5 VSS41 VCCSUS1.5_0 E12
    2 2 2 2 2 2 2
    P11 VSS42 VCCSUS1.5_1 E13
    P13 VSS43 VCCSUS1.5_2 E20
    P20 F14 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VSS44 VCCSUS1.5_3
    P22 VSS45 VCCSUS1.5_4 G18 VCCHI power place
    P3 VSS46 VCCSUS1.5_5 R6
    R18 VSS47 VCCSUS1.5_6 T6
    R21 VSS48 VCCSUS1.5_7 U6
    R5 VSS49
    T1 VSS50
    T19 E7 VCC5REF
    VSS51 VCC5REF1 +3VALW +5VALW +3VS +5VS +5VCD
    T23 VSS52 VCC5REF2 V6
    U20 VSS53
    V15 E15 VCC5REFSUS
    VSS54 VCC5REFSUS1

    1
    V17 +1.5VS
    VSS55 D23 R116 D22 R84 R182
    V3 VSS56
    W22 L23 1SS355_SOD323 1K_0402_5% 1SS355_SOD323 @ 1K_0402_5% 1K_0402_5%
    VSS57 VCCHI_0
    W5 VSS58 VCCHI_1 M14
    W8 VSS59 VCCHI_2 P18

    2
    Y19 T22 VCC5REFSUS VCC5REF
    VSS60 VCCHI_3 +VCCP
    Y7 VSS61
    A16 VSS62 1 1
    A18 VSS63 VCC_CPU_IO_0 AA23
    A20 P14 C86 C54
    VSS64 VCC_CPU_IO_1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    A22 VSS65 VCC_CPU_IO_2 U18
    2 2
    A4 VSS66
    AA12 VSS67
    AA16 VSS68 VCCPLL C22 +1.5VS
    AA22 VSS69
    AA3 VSS70
    AA9 VSS71 VCCRTC AB5 +RTCVCC
    AB20 VSS72
    3 3
    AB7 VSS73
    AC1 VSS74
    AC10 VSS75 VCCLAN3.3_0 E9 +3VS
    AC14 VSS76 VCCLAN3.3_1 F9
    AC18 VSS77
    AC23 VSS78
    AC5 VSS79 VCCLAN1.5_0 F6 +1.5VS
    B12
    B16
    B18
    VSS80
    VSS81
    VCCLAN1.5_1 F7
    RTC Battery
    VSS82 +RTCPWR
    B20 VSS83
    B22 VSS84
    B9
    C15
    C17
    VSS85
    VSS86
    VSS87
    -2
    BATT1
    + 1 1
    C488
    2
    C19 VSS88
    C21 0.1U_0402_16V4Z
    VSS89

    1
    C23 VSS90
    C6 ML1220T13RE
    VSS91
    D1 VSS92 BAS40-04_SOT23
    D12 VSS93
    D15 D24
    VSS94 +RTCVCC
    D17 VSS95

    2
    D19 VSS96
    D21 VSS97
    D23 VSS98
    D4 VSS99 +CHGRTC
    D8 VSS100
    A1 VSS101

    4 4

    FW82801DBM_BGA421

    Compal Electronics, Inc.


    Title

    ICH4-M(3/3) PWR/GND
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 24 of 47
    A B C D E F G H
    5 4 3 2 1

    HDD Connector <23> PD_D[0..15]


    PD_D[0..15]

    Q6
    SUYIN_20125A-44G5T-01-C_NORMAL SI3443DV_TSOP6
    PIDE_RST#
    1 2

    D
    PD_D7 PD_D8 6

    S
    PD_D6 3 4 PD_D9
    PD_D5 5 6 PD_D10
    +5VALW 4 5 +5VCD Placea caps. near HDD
    2 1
    PD_D4 7 8 PD_D11 1 1 CONN.
    D PD_D3 9 10 PD_D12 C168 +5VS D

    G
    PD_D2 11 12 PD_D13 C177 0.1U_0402_16V4Z
    13 14 2

    3
    PD_D1 PD_D14 10U_0805_10V4Z 10U_1206_16V4Z 1U_0603_10V4Z
    PD_D0 15 16 PD_D15 2
    17 18 1 1
    R601 R184 1 1 1
    4.7K_0402_5% PD_DREQ 19 20 C475 C479 C473
    <23> PD_DREQ 21 22 +5VALW 1 2
    1 2 R103 240K_0402_5% C478 C474
    +3VS <23> PD_IOW# 23 24 2 2
    470_0402_5%
    <23> PD_IOR# 25 26
    PD_PIORDY PCSEL 1 2 C172 R186 10K_0402_5% 1000P_0402_50V7K 2 2 2
    <23> PD_PIORDY 27 28
    1 2 2 1 10U_1206_16V4Z 0.1U_0402_16V4Z
    <23> PD_DACK# 29 30 R117
    <22> PD_IRQ14 31 32

    1
    1 2 10K_0402_5% 1U_0603_10V4Z
    <23> PD_A1 33 34
    <23> PD_A0 35 36 PD_A2 <23>
    <23> PD_CS#1 37 38 PD_CS#3 <23>
    PHDD_LED#
    <34> PHDD_LED# 39 40
    +5VS 2 CD_PLAY
    +5VS 41 42 CD_PLAY <32,34>
    43 44 Q7
    +5VS 1 2
    R127 100K_0402_5% JP8 DTC124EK_SC59

    3
    +3VALW +5VCD

    This is reverse type conn, PIDE_RST# connect to pin44.

    1
    G_PCI_RST#
    After connector library ready, R176
    10K_0402_5%

    14
    correct connection is PIDE_RST# connect to pin1!

    1
    U15A
    <31,34> EC_IDERST

    OE#

    2
    SD_CS#3 2 3 SW_SD_CS#3 +3VALW C138
    <23> SD_CS#3 I O 0.1U_0402_16V4Z

    G
    1 2
    C SN74LVC125APWLE_TSSOP14 +3VALW C

    14
    U16A

    14
    +5VCD U16B 1

    P
    PCIRST# A PIDE_RST#
    4 3

    P
    A O
    O 6 2 B

    G
    G_PCI_RST# 5
    <22> PIDERST# B

    G
    R178 SN74LVC08APW_TSSOP14

    7
    10K_0402_5% SN74LVC08APW_TSSOP14

    7
    4
    U15B

    OE#

    2
    SD_CS#1 5 6 SW_SD_CS#1
    <23> SD_CS#1 I O

    SN74LVC125APWLE_TSSOP14

    SD_D[0..15]
    CDROM CONN <23> SD_D[0..15]

    C162
    2 1 CD_AGND
    CD_AGND <31>

    10U_0805_10V4Z <34> PCMRST# +5VCD

    JP11
    +3VALW

    1
    INT_CD_L 1 2 INT_CD_R
    <31> INT_CD_L INT_CD_R <31>
    3 4
    SIDE_RST# 5 6 SD_D8 1 2 R179

    14

    10
    B SD_D7 SD_D9 R167 @ 0_0603_5% U16C U15C 10K_0402_5% B
    7 8
    SD_D6 9 10 SD_D10 PCIRST# 9

    OE#
    A

    2
    SD_D5 11 12 SD_D11 8 9 8 SIDE_RST#
    SD_D4 SD_D12 O I O
    13 14 <22> SIDERST# 10 B

    G
    SD_D3 15 16 SD_D13

    2
    SD_D2 17 18 SD_D14

    7
    R484 SD_D1 19 20 SD_D15 SN74LVC125APWLE_TSSOP14
    4.7K_0402_5% SD_D0 21 22 SD_DREQ SN74LVC08APW_TSSOP14
    SD_DREQ <23> R165
    1 2 23 24 SD_IOR#
    +3VS SD_IOR# <23>
    SD_IOW# 25 26 10K_0402_5%
    <23> SD_IOW#

    1
    SD_SIORDY 27 28 SD_DACK#
    <23> SD_SIORDY SD_DACK# <23>
    SD_IRQ15 29 30
    <22> SD_IRQ15 100K_0402_5%
    31 32 PDIAG# 1 R490 2
    <23> SD_A1 +5VCD
    <23> SD_A0 33 34 SD_A2 <23>
    SW_SD_CS#1 35 36 SW_SD_CS#3
    SHDD_LED# 37 38 W=80mils +3VALW
    <34> SHDD_LED# +5VCD
    39 40
    1 2 +5VCD 41 42
    +5VCD

    1
    R504 100K_0402_5% 43 44
    45 46 R177
    SD_CSEL 47 48 10K_0402_5%
    49 50 1 2 +5VCD
    2

    51 52 R541 @ 100K_0402_5%

    2
    R533 ALLTOP_C12431-1-5001 G_PCI_RST#
    470_0402_5% D

    1
    PCIRST# 2 2N7002_SOT23
    1

    <7,13,19,22,27,28,30> PCIRST# G Q5
    S

    3
    A +5VCD
    Placea caps. near CDROM A
    CONN.

    1 1 1 1
    C596 C601 C606
    C598
    1000P_0402_50V7K 2 2 2
    1U_0603_10V4Z
    2
    10U_1206_16V4Z
    Compal Electronics, Inc.
    Title
    0.1U_0402_16V4Z
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDD & CDROM Connector & Direct CD
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 25 of 47
    5 4 3 2 1
    5 4 3 2 1

    U26 +3V
    <22,27,28,30> PCI_AD[0..31]
    PCI_AD[0..31] PCI_AD0
    PCI_AD1
    PCI_AD2
    104
    103
    AD0
    AD1
    EEDO
    AUX/EEDI
    108
    109
    LAN_EEDO
    LAN_EEDI
    LAN_EECLK
    1
    R314
    2 +3V
    LAN_EECS
    LAN_EECLK
    1
    U30
    CS VCC 8
    LAN RTL8100C(L)
    102 AD2 EESK 111 2 SK NC 7 1
    PCI_AD3 98 106 LAN_EECS 5.6K_0402_5% LAN_EEDI 3 6
    PCI_AD4 AD3 EECS LAN_EEDO DI NC C348
    97 AD4 4 DO GND 5
    PCI_AD5 96 117 ACTIVITY# 0.1U_0402_16V4Z
    PCI_AD6 AD5 LED0 LINK10_100# AT93C46-10SI-2.7_SO8 2
    95 AD6 LED1 115
    PCI_AD7 93 114
    PCI_AD8 AD7 LED2
    D 90 AD8 NC/LED3 113 D

    CLK_PCI_LAN
    PCI_AD9
    PCI_AD10
    89
    87
    AD9
    1 LAN_TD+
    H=1.98mm
    PCI_AD11 AD10 TXD+/MDI0+ LAN_TD- U28
    86 AD11 TXD-/MDI0- 2
    1

    PCI_AD12 85 5 LAN_RD+
    PCI_AD13 AD12 RXIN+/MDI1+ LAN_RD- LAN_RD+ RJ45_RX+
    83 AD13 RXIN-/MDI1- 6 1 RD+ RX+ 16
    R279 PCI_AD14 82 LAN_RD- 2 15 RJ45_RX-
    10_0402_5% PCI_AD15 AD14 RD- RX-
    79 AD15 NC/MDI2+ 14 3 CT CT 14
    PCI_AD16 59 15
    AD16 NC/MDI2-
    2

    1 PCI_AD17 58 18
    PCI_AD18 AD17 NC/MDI3+
    57 AD18 NC/MDI3- 19 6 CT CT 11
    C284 PCI_AD19 55 LAN_TD+ 7 10 RJ45_TX+
    AD19 TD+ TX+

    1
    15P_0402_50V8J PCI_AD20 53 121 LAN_X1 LAN_TD- 8 9 RJ45_TX-
    2 PCI_AD21 AD20 X1 LAN_X2 R312 R313 TD- TX-
    50 AD21 X2 122

    1
    PCI_AD22 49.9_0402_1% 49.9_0402_1%

    PCI I/F
    49 AD22 10mil
    PCI_AD23 47 105 R280 1 2 1K_0402_5% +3VS R310 R311 NS0013_16P
    AD23 LWAKE

    1
    PCI_AD24 43 23 LAN_ISOLATE# R281 1 2 15K_0402_5% 49.9_0402_1% 49.9_0402_1%
    AD24 ISOLATE#

    2
    PCI_AD25 42 127 LOAN_RTSET R292 1 2 5.36K_0603_1%
    PCI_AD26 AD25 RTSET R278 R277
    40 AD26 NC/SMBCLK 72 10mil

    2
    PCI_AD27 39 74 75_0402_1% 75_0402_1%
    PCI_AD28 AD27 NC/SMBDATA
    37 AD28

    2
    PCI_AD29 36 88 1 1 1
    PCI_AD30 AD29 NC/M66EN
    34 AD30
    PCI_AD31 33 10 C328 C326 C325 RJ45_GND
    AD31 NC/AVDDH 0.01U_0402_25V7Z 0.01U_0402_25V7Z 0.1U_0402_16V4Z
    NC/HV 120
    PCI_CBE#0 2 2 2
    <22,27,28,30> PCI_CBE#0 92 C/BE#0
    PCI_CBE#1 77 11
    <22,27,28,30> PCI_CBE#1 C/BE#1 NC/HSDAC+
    PCI_CBE#2 60 123
    <22,27,28,30> PCI_CBE#2 C/BE#2 NC/HG
    PCI_CBE#3 44 124
    <22,27,28,30> PCI_CBE#3 C/BE#3 NC/LG2
    126 +LAN_DVDD
    PCI_AD17 NC/LV2
    1 2 LAN_IDSEL 46 IDSEL
    R300 100_0402_5%
    C
    LAN I/F +3V C
    <22,27,28,30> PCI_PAR 76 PAR
    <22,27,28,30> PCI_FRAME# 61 FRAME# NC/VSS 9
    <22,27,28,30> PCI_IRDY# 63 IRDY# NC/VSS 13
    <22,27,28,30> PCI_TRDY# 67 TRDY#

    3
    68 E
    <22,27,28,30> PCI_DEVSEL# DEVSEL#
    69 22 CTRL25 2 Q27
    <22,27,28,30> PCI_STOP# STOP# NC/GND B
    48 2SB1197K_SOT23 Q25
    NC/GND C DTA114YKA_SOT23 JP4
    <22,27,28,30> PCI_PERR# 70 62 40mil

    E
    PERR# NC/GND

    1
    <22,28,30> PCI_SERR# 75 SERR# NC/GND 73 +2.5V_LAN +3V 3 1 1 2 10mil 12 Amber LED+

    47K
    112 1 1 R268

    C
    NC/GND 300_0402_5%
    <22> PCI_REQ#1 30 REQ# NC/GND 118 11 Amber LED-

    10K
    29 C294 C288 16
    <22> PCI_GNT#1

    B
    GNT# 10U_0805_10V4Z 0.1U_0402_16V4Z SHLD4
    8 PR4-
    2 2
    <22> PCI_PIRQF# 25 INTA# SHLD3 15

    2
    8 CTRL25 7
    CTRL25 ACTIVITY# PR4+
    <28,30,34> ONBD_LAN_PME# 31 PME#
    125 RJ45_RX- 6
    RTT3/CRTL18 PR2-
    <22,33,34> B_PCIRST# 27 RST#
    VDD33 26 +3V 5 PR3-
    CLK_PCI_LAN 28 41
    <12> CLK_PCI_LAN CLK VDD33
    PM_CLKRUN# 65 56 4
    <23,30,33,34> PM_CLKRUN# CLKRUN# VDD33 PR3+
    VDD33 71
    84 RJ45_RX+ 3
    VDD33 PR2+
    VDD33 94
    107 RJ45_TX- 2
    VDD33 PR1-
    4 GND/VSS SHLD2 14
    17 RJ45_TX+ 1
    GND/VSS PR1+
    128 GND/VSS SHLD1 13
    3 +LAN_AVDDL 1 2 +3V 10
    AVDD33/AVDDL L16 0_0805_5% Green LED-
    7 40mil

    E
    AVDD33/AVDDL
    21 GND/VSSPST AVDD33/AVDDL 20 1 1 1 +3V 3 1 1 2 10mil 9 Green LED+

    47K
    B 38 16 C286 0.1U_0402_16V4Z C291 R258 B

    C
    GND/VSSPST NC/AVDDL

    1
    51 300_0402_5% AMP RJ45/RJ11 with LED
    GND/VSSPST

    10K
    66 0.1U_0402_16V4Z C290 0.1U_0402_16V4Z

    B
    GND/VSSPST 2 2 2 Q26 R270 R269
    Y1 81 32
    LAN_X1 LAN_X2 GND/VSSPST VDD25/VDD18 DTA114YKA_SOT23 75_0402_1% 75_0402_1%
    91 GND/VSSPST VDD25/VDD18 54

    2
    101 GND/VSSPST VDD25/VDD18 78

    2
    119 99 +LAN_DVDD 1 2 +2.5V_LAN LINK10_100#
    25MHZ_20P_1BX25000CK1A GND/VSSPST VDD25/VDD18 R273 0_0805_5%
    1 1 40mil
    Power

    1 1 1
    C320 C311 35 24 0.1U_0402_16V4Z RJ45_GND 1 2 LANGND
    27P_0402_50V8J 27P_0402_50V8J GND NC/VDD18 C345
    2 2
    52 GND NC/VDD18 45 20mil 1 1
    80 64 C331 C3220.1U_0402_16V4Z C275
    GND NC/VDD18 2 2 2 1000P_1206_2KV7K C267 C270
    100 GND NC/VDD18 110
    116 0.1U_0402_16V4Z 4.7U_0805_10V4Z
    NC/VDD18 2 2
    +3V
    12 +2.5V_LAN_VDD 1 2 +2.5V_LAN 0.1U_0402_16V4Z
    AVDD25/HSDAC- R276 0_0805_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    20mil 1 1
    RTL8100C_QFP128 1 1 1 1 1 1 Termination plane should be closed
    C289 C287
    0.1U_0402_16V4Z 10U_0805_10V4Z C324 C302 C347 C344 C346 C285 to chassis ground and also depends
    2 2 0.1U_0402_16V4Z on safety concern
    2 2 2 2 2 2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

    A A

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LAN RTL8100CL
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 26 of 47


    5 4 3 2 1
    A B C D E

    +3VS

    +3VS
    C580 C583 C571 C555 C549 C521 C579 C537 U43
    1 A0 VCC 8
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 7 1 2
    A1 WC EECK_1394 R470
    3 A2 SCL 6
    4 5 EEDI_1394 560_0402_5%
    GND SDA
    AT24C02N-10SC-2.7_SO8
    +3VS Use 24C02 D Version :SA024020310

    1 1
    C522 C535 C520 C568 C540

    1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K

    +3VS

    +3VS
    PCI_AD[0..31]
    <22,26,28,30> PCI_AD[0..31]

    2
    L24
    FCM2012C-800_0805

    110
    122

    111

    100
    108
    118
    126

    112
    46
    36
    99

    17
    32

    21
    30

    31
    47
    91

    13
    23
    33

    22
    38
    5

    6
    U41

    PVD
    PVD
    VCC
    VCC
    VCC
    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND

    1
    PCI_AD0 25
    PCI_AD1 AD0 +3V_1394
    24 AD1
    PCI_AD2 20
    PCI_AD3 AD2
    19 AD3
    PCI_AD4 18 59 0.1U_0402_16V4Z
    PCI_AD5 AD4 PVA

    Power
    16 AD5 PVA 62 2 2 2 2
    PCI_AD6 15 72
    PCI_AD7 AD6 PVA C586 C559 C548C560
    14 AD7 PVA 73
    PCI_AD8 11 86 0.1U_0402_16V4Z
    PCI_AD9 AD8 PVA 1 1 1 1
    10 AD9 PVA 87
    PCI_AD10 9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 PCI_AD11 AD10 2
    8 AD11
    PCI_AD12 7
    PCI_AD13 AD12
    4 AD13 GND 61
    PCI_AD14 3 65
    PCI_AD15 AD14 GND
    2 AD15 GND 66
    PCI_AD16 117 79
    PCI_AD17 AD16 GND
    116 AD17 GND 80
    PCI_AD18 115 AD18 GND 56 W/ EEPROM Pop R467
    PCI_AD19 114
    PCI_AD20 113
    AD19 W/O EEPROM Unpop 467
    PCI_AD21 AD20

    IEEE 1394
    109 AD21
    PCI_AD22 107 26 R467 1 2
    AD22 EECS +3VS
    PCI_AD23
    PCI_AD24
    106
    103
    AD23 EEPROM EEDO 27
    28 EEDI_1394 @ 4.7K_0402_5%
    AD24 EEDI/SDA
    PCI_AD25
    PCI_AD26
    102 AD25 I/F EECK/SCL 29 EECK_1394

    VT6301S
    101
    PCI Bus

    PCI_AD27 AD26
    98
    PCI_AD28 97
    AD27
    AD28
    PM & Test
    PCI_AD29 96 34
    PCI_AD30 AD29 PME#
    IDSEL:PCI_AD16 95 AD30
    PCI_AD31 94 60 R491 1K_0402_5% R503 6.34K_0402_1%
    AD31 XCPS
    12 63 C587 2 1 47P_0402_50V8J
    <22,26,28,30> PCI_CBE#0 CBE0# XREXT FOX_UV31413-4R1-TR

    Differential Pairs
    <22,26,28,30> PCI_CBE#1 1 CBE1#
    <22,26,28,30> PCI_CBE#2 119 CBE2# TPB0M 67 XTPB0- XTPA0+ 4 4 Connect To
    104 68 XTPB0+ XTPA0- 3 6
    <22,26,28,30> PCI_CBE#3 CBE3# TPB0P
    69 XTPA0- XTPB0+ 2
    3 6
    5
    Shielding
    PCI_AD16 TPA0M XTPA0+ XTPB0- 2 5 GND
    1 R428 2 100_0402_5%105 IDSEL TPA0P 70 1 1
    120 71 XTPBIAS0
    <22,26,28,30> PCI_FRAME# FRAME# TPBIAS0 JP18

    54.9_0402_1%

    54.9_0402_1%

    54.9_0402_1%

    4.99K_0603_1% 54.9_0402_1%
    <22,26,28,30> PCI_IRDY# 121 IRDY#

    1
    <22,26,28,30> PCI_TRDY# 123 TRDY#
    3 124 R472 R475 R479 R481 3
    <22,26,28,30> PCI_DEVSEL# DEVSEL#
    <22,26,28,30> PCI_STOP# 125 STOP#
    <22,26,28,30> PCI_PERR# 127 PERR#
    <22,26,28,30> PCI_PAR 128 PAR

    2
    <22> PCI_REQ#0 93 REQ#
    <22> PCI_GNT#0 92 GNT#
    NC

    1
    270P_0402_25V8K
    0.33U_0603_16V4Z
    <22> PCI_PIRQE# 88 INTA# 1 1
    C567 C576 R486
    <7,13,19,22,25,28,30> PCIRST#
    <12> CLK_PCI_1394
    89
    CLK_PCI_1394 90 PCIRST#
    PCICLK OSC PHYRESET# 55
    CARDEN

    2 2
    1

    I2CEN

    2
    R446
    1394
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC
    NC

    XO
    XI

    @ 10_0402_5% 2
    VT6301S-CD_LQFP128 C578
    41
    42
    45
    48
    49
    50
    37
    51
    52
    53
    54
    40
    39
    35
    74
    75
    76
    77
    78
    64
    81
    82
    83
    84
    85

    43
    44

    57

    58

    Note:These components
    2

    1 0.1U_0402_16V4Z
    1 need to close to chip pins.
    C541
    @18P_0402_50V8K
    2
    X2
    XI 2 1XO
    +3VS
    R487
    4.7K_0402_5%
    24.576MHz_16P_3XG-24576-43E1
    If use 93C46, Delete R649
    2 2
    R485
    C588 1M_0402_5% C589
    10P_0402_50V8K 10P_0402_50V8K
    1 1
    4 4

    Compal Electronics, Inc.


    Title
    IEEE1394a VIA VT6301S
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
    PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE CustomEAL20 LA-2461 0.3
    USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期三, 八月 04, 2004 Sheet 27 of 47
    A B C D E
    A B C D E

    +3VS
    <29> VPPD0 +S1_VCC
    <29> VPPD1 +3VS
    <29> VCCD0#
    <29> VCCD1# 1 1 1 2
    1 1

    M13

    M12

    G13
    N13

    N12

    D12
    H11
    C153 C164 C167 C181

    G1
    C8

    N4
    A7

    B4

    K2

    F3
    L9
    L6
    U42 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    S1_A[0..25] 2 2 2 1
    S1_A[0..25] <29>

    VCCD1#
    VCCD0#

    VPPD1
    VPPD0

    VCCA2
    VCCA1

    VCC10
    VCC9
    VCC8
    VCC7
    VCC6
    VCC5
    VCC4
    VCC3
    VCC2
    VCC1
    S1_D[0..15]
    PCI_AD[0..31] S1_D[0..15] <29>
    <22,26,27,30> PCI_AD[0..31] +3VS
    PCI_AD31 C2 B2 S1_D10
    PCI_AD30 AD31 CAD31/D10 S1_D9
    C1 AD30 CAD30/D9 C3
    PCI_AD29 D4 B3 S1_D1 1 1 1 1
    CLK_EXT_SD48 CLK_PCI_PCM PCI_AD28 AD29 CAD29/D1 S1_D8
    D2 AD28 CAD28/D8 A3
    PCI_AD27 D1 C4 S1_D0 C156 C151 C180 C174
    AD27 CAD27/D0
    1

    PCI_AD26 E4 A6 S1_A0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


    R183 R464 PCI_AD25 AD26 CAD26/A0 S1_A1 2 2 2 2
    E3 AD25 CAD25/A1 D7
    10_0402_5% 10_0402_5% PCI_AD24 E2 C7 S1_A2
    @ @ PCI_AD23 AD24 CAD24/A2 S1_A3
    F2 AD23 CAD23/A3 A8
    PCI_AD22 F1 D8 S1_A4
    AD22 CAD22/A4
    2

    1 1 PCI_AD21 G2 A9 S1_A5
    PCI_AD20 AD21 CAD21/A5 S1_A6
    G3 AD20 CAD20/A6 C9
    C158 C561 PCI_AD19 H3 A10 S1_A25 +S1_VCC
    15P_0402_50V8J 15P_0402_50V8J PCI_AD18 AD19 CAD19/A25 S1_A7
    H4 AD18 CAD18/A7 B10
    2 @ 2 @ PCI_AD17 S1_A24
    J1 AD17 CAD17/A24 D10
    PCI_AD16 J2 E12 S1_A17 1 1 1 1
    PCI_AD15 AD16 CAD16/A17 S1_IOWR#
    N2 AD15 CAD15/IOWR# F10 S1_IOWR# <29>
    PCI_AD14 M3 E13 S1_A9 C152 C161 C147 C160
    PCI_AD13 AD14 CAD14/A9 S1_IORD# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    N3 AD13 CAD13/IORD# F13 S1_IORD# <29> 0.1U_0402_16V4Z
    PCI_AD12 S1_A11 2 2 2 2
    K4 AD12 CAD12/A11 F11
    +VCC_5IN1 PCI_AD11 M4 G10 S1_OE#
    AD11 CAD11/OE# S1_OE# <29>
    PCI_AD10 K5 G11 S1_CE2#
    AD10 CAD10/CE2# S1_CE2# <29>
    PCI_AD9 L5 G12 S1_A10
    PCI_AD8 AD9 CAD9/A10 S1_D15
    M5 AD8 CAD8/D15 H12
    2

    2 PCI_AD7 S1_D7 2
    K6 AD7 CAD7/D7 H10
    R435 PCI_AD6 M6 J11 S1_D13
    PCI_AD5 AD6 CAD6/D13 S1_D6
    0_0805_5% N6 AD5 CAD5/D6 J12
    @ PCI_AD4 M7 K13 S1_D12
    PCI_AD3 AD4 CAD4/D12 S1_D5
    N7 AD3 CAD3/D5 J10
    1

    PCI Interface
    2 5IN1@ 1 SD_PULLHIGH PCI_AD2 L7 K10 S1_D11
    AD2 CAD2/D11

    CARDBUS
    R495 0_0805_5% PCI_AD1 K7 K12 S1_D4
    AD1 CAD1/D4
    1 5IN1@ 2 SDCM_XDALE PCI_AD0 N8 AD0 CAD0/D3 L13 S1_D3
    R440 43K_0402_5%
    1 5IN1@ 2 SDDA0_XDD7
    <22,26,27,30> PCI_CBE#3 E1 CBE3# CCBE3#/REG# B7 S1_REG#
    S1_REG# <29>
    R438 43K_0402_5% J3 A11 S1_A12 S1_CD1# S1_CD2#
    <22,26,27,30> PCI_CBE#2 CBE2# CCBE2#/A12
    1 5IN1@ 2 SDDA1_XDD0
    <22,26,27,30> PCI_CBE#1 N1 CBE1# CCBE1#/A8 E11 S1_A8
    R456 43K_0402_5% N5 H13 S1_CE1# 1 1
    <22,26,27,30> PCI_CBE#0 CBE0# CCBE0#/CE1# S1_CE1# <29>
    1 5IN1@ 2 SDDA2_XDCL C179 C530
    R443 43K_0402_5% G4 B9 S1_RST
    <7,13,19,22,25,27,30> PCIRST# PCIRST# CRST#/RESET S1_RST <29>
    1 5IN1@ 2 SDDA3_XDD4 J4 B11 S1_A23 10P_0402_50V8K 10P_0402_50V8K
    <22,26,27,30> PCI_FRAME# FRAME# CFRAME#/A23 2 2
    R447 43K_0402_5% K1 A12 S1_A15
    +3VS <22,26,27,30> PCI_IRDY# IRDY# CIRDY#/A15
    K3 A13 S1_A22
    <22,26,27,30> PCI_TRDY# TRDY# CTRDY#/A22
    L1 B13 S1_A21
    <22,26,27,30> PCI_DEVSEL# DEVSEL# CDEVSEL#/A21
    L2 C12 S1_A20 Closed to Pin L12 Closed to Pin A4
    <22,26,27,30> PCI_STOP# STOP# CSTOP#/A20
    L3 C13 S1_A14
    <22,26,27,30> PCI_PERR# PERR# CPERR#/A14
    1 2 SDCD# M1 A5 S1_WAIT#
    <22,26,30> PCI_SERR# SERR# CSERR#/WAIT# S1_WAIT# <29>
    R468 @ 43K_0402_5% M2 D13 S1_A13
    <22,26,27,30> PCI_PAR PAR CPAR/A13
    1 2 SDWP A1 B8 S1_INPACK#
    <22> PCI_REQ#2 PCIREQ# CREQ#/INPACK# S1_INPACK# <29>
    R452 @ 43K_0402_5% B1 C11 S1_WE#
    <22> PCI_GNT#2 PCIGNT# CGNT#/WE# S1_WE# <29>
    1 2 MSINS# CLK_PCI_PCM H1 B12 A16_CLK 1 2 S1_A16 Close chip termenal
    <12> CLK_PCI_PCM PCICLK CCLK/A16
    R473 @ 43K_0402_5% R444 33_0402_5%
    <26,30,34> PCM_PME# R500 1 2 @ 0_0402_5% L8 C5 S1_BVD1
    R477 1 RIOUT#_PME# CSTSCHG/BVD1_STSCHG# S1_BVD1 <29>
    2 10K_0402_5% L11 D5 S1_WP
    +3VS SUSPEND# CCLKRUN#/WP_IOIS16# S1_WP <29>

    IDSEL: PCI_AD20 1 2 PCM_ID F4 D11 S1_A19


    R460 100_0402_5% IDSEL CBLOCK#/A19 MSD0_XDD2 1 2
    3 PCI_AD20 PCI_PIRQA# K8 D6 S1_RDY# R462 @ 43K_0402_5% 3
    <13,22> PCI_PIRQA# MFUNC0 CINT#/READY_IREQ# S1_RDY# <29>
    R501 SD_PULLHIGH N9 MSD1_XDD6 1 2
    PCI_PIRQB# MFUNC1 PCM_SPK# R465 @ 43K_0402_5%
    +3VS 2 1 <22> PCI_PIRQB# K9 MFUNC2 SPKROUT M9 PCM_SPK# <31>
    5IN1@ 43K_0402_5% N10 B5 S1_BVD2 MSD2_XDD5 1 2
    <22,33,34> SIRQ MFUNC3 CAUDIO/BVD2_SPKR# S1_BVD2 <29>
    <29> SM_CD# L10 R457 @ 43K_0402_5%
    5IN1_LED# MFUNC4 S1_CD2# MSD3_XDD3
    N11 MFUNC5 CCD2#/CD2# A4 S1_CD2# <29> 1 2
    M11 L12 S1_CD1# R453 @ 43K_0402_5%
    MFUNC6 CCD1#/CD1# S1_CD1# <29>
    One memory card controller use MFUNC7 as OC#, SDOC# J9 D9 S1_VS2 MSBS_XDD1 1 2
    <29> SDOC# MFUNC7 CVS2/VS2# S1_VS2 <29>
    C6 S1_VS1 R471 @ 43K_0402_5%
    Another one use MFUNC6 as OC#. CVS1/VS1
    A2 S1_D2
    S1_VS1 <29>
    CRSV3/D2
    Connect 2 pin together to assert over current even to 2 PCIRST# M10 GRST# CRSV2/A18 E10 S1_A18
    J13 S1_D14
    controller at the same time. CRSV1/D14
    This is ENE suggestion.

    +VCC_5IN1 E7
    SD/MMC/MS/SM H7
    VCC_SD MSINS# MSINS# <29>
    J8 XD_MS_PWREN#
    MSPWREN#/SMPWREN# XD_MS_PWREN# <29>
    SDCD# E8 H8 MSBS_XDD1
    <29> SDCD# SDCD# MSBS/SMDATA1 MSBS_XDD1 <29>
    SDWP F8 E9 1 2 5IN1@
    <29> SDWP SDWP/SMWPD# MSCLK/SMRE# MSCLK_XDRE# <29>
    SDPWREN# G7 G9 MSD0_XDD2 R448 33_0402_5%
    <29> SDPWREN# SDPWREN33# MSDATA0/SMDATA2 MSD0_XDD2 <29>
    H9 MSD1_XDD6
    MSDATA1/SMDATA6 MSD1_XDD6 <29>
    H5 G8 MSD2_XDD5
    <12> CLK_EXT_SD48 SDCLKI MSDATA2/SMDATA5 MSD2_XDD5 <29>
    R458 5IN1@ F9 MSD3_XDD3
    MSDATA3/SMDATA3 MSD3_XDD3 <29>
    <29> SD_CLK 1 2 22_0402_5% F6 SDCLK/SMWE#
    SDCM_XDALE E5
    <29> SDCM_XDALE SDCMD/SMALE
    <29> XDWE# 1 2 22_0402_5% <29> SDDA0_XDD7
    SDDA0_XDD7 E6 SDDAT0/SMDATA7 SMBSY# H6 XDBSY# <29>
    SDDA1_XDD0 F7 J7
    <29> SDDA1_XDD0 SDDAT1/SMDATA0 SMCD# XDCD# <29>
    R628 5IN1@ SDDA2_XDCL F5 J6
    <29> SDDA2_XDCL SDDAT2/SMCLE SMWP# XDWP# <29>
    SDDA3_XDD4 G6 J5
    <29> SDDA3_XDD4 SDDAT3/SMDATA4 SMCE# XDCE# <29>
    2
    GND1
    GND2
    GND3
    GND4
    GND5
    GND6
    GND7
    GND8

    G5 GND_SD R474
    4 4
    2.2K_0402_5%
    CB714_LFBGA169 5IN1@
    D3
    H2
    L4
    M8
    K11
    F12
    C10
    B6

    +3VS
    5IN1 LED Side View
    5IN1@ D12 5IN1@
    1 2 2 1 5IN1_LED#
    Compal Electronics, Inc.
    R217 HT-110UYG-CT_YEL/GRN Title
    120_0402_5%
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CardBus Controller CB714
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 28 of 47
    A B C D E
    5 4 3 2 1

    JP12
    PCMCIA Power Controller CardBus Socket 1 35
    U18 +S1_VCC S1_D3 GND GND S1_CD1#
    1 2 2 D3 / CAD0 CD1# / CCD1# 36 S1_CD1# <28>
    13 40mil C195 0.1U_0402_16V4Z S1_D4 3 37 S1_D11
    VCC S1_D5 D4 / CAD1 D11 / CAD2 S1_D12
    VCC 12 4 D5 / CAD3 D12 / CAD4 38
    9 11 C196 0.1U_0402_16V4Z S1_D6 5 39 S1_D13
    12V VCC S1_D7 D6 / CAD5 D13/ CAD6 S1_D14
    1 2 6 D7 / CAD7 D14/ RFU 40
    C192 1U_0603_10V4Z S1_CE1# 7 41 S1_D15
    +S1_VPP <28> S1_CE1# S1_A10 CE1# / CCBE0# D15 / CAD8 S1_CE2#
    1 2 8 A10 / CAD9 CE2# / CAD10 42 S1_CE2# <28>
    20mil C197 @ 0.01U_0402_25V4Z S1_OE# 9 43 S1_VS1
    +5VS <28> S1_OE# S1_A11 OE# / CAD11 VS1# / CVS1 S1_IORD# S1_VS1 <28>
    VPP 10 1 2 10 A11 / CAD12 IORD# / CAD13 44 S1_IORD# <28>
    C190 @ 1U_0603_10V4Z S1_A9 11 45 S1_IOWR#
    0.1U_0402_16V4Z C217 S1_A8 A9 / CAD14 IOWR# /CAD15 S1_A17 S1_IOWR# <28>
    5 5V 12 A8 / CCBE1# A17 / CAD16 46
    6 S1_A13 13 47 S1_A18
    4.7U_0805_10V4Z C222 5V S1_A14 A13 / CPAR A18 / RFU S1_A19
    D 14 A14 / CPERR# A19 / CBLOCK# 48 D
    1 S1_WE# 15 49 S1_A20
    VCCD0 VCCD0# <28> <28> S1_WE# WE# / CGNT# A20 / CSTOP#
    2 S1_RDY# 16 50 S1_A21
    VCCD1 VCCD1# <28> <28> S1_RDY# IREQ# / CINT# A21 / CDEVSEL#
    VPPD0 15 VPPD0 <28> +S1_VCC 17 VCC VCC 51 +S1_VCC
    +3VS 14 18 52
    VPPD1 VPPD1 <28> +S1_VPP VPP1 VPP2 +S1_VPP
    S1_A16 19 53 S1_A22
    0.1U_0402_16V4Z C216 S1_A15 A16 / CCLK A22 / CTRDY# S1_A23
    3 3.3V 20 A15 / CIRDY# A23 / CFRAME# 54
    4 8 S1_A12 21 55 S1_A24
    3.3V OC A12 / CCBE2# A24 / CAD17

    SHDN
    4.7U_0805_10V4Z C221 S1_A7 22 56 S1_A25

    GND
    S1_A6 A7 / CAD18 A25 / CAD19 S1_VS2
    23 A6 / CAD20 VS2# / CVS2 57 S1_VS2 <28>
    2

    S1_A5 24 58 S1_RST
    R195 CP2211D3_SSOP16 S1_A4 A5 / CAD21 RESET / CRST# S1_WAIT# S1_RST <28>
    25 A4 / CAD22 WAIT# / CSERR# 59 S1_WAIT# <28>
    7

    10K_0402_5% 16 S1_A3 26 A3 / CAD23 INPACK# / CREQ# 60 S1_INPACK#


    S1_INPACK# <28>
    S1_A2 27 61 S1_REG#
    S1_A1 A2 / CAD24 REG# / CCBE3# S1_BVD2 S1_REG# <28>
    28 A1 / CAD25 SPKR# / CAUDIO 62 S1_BVD2 <28>
    1

    S1_A0 29 63 S1_BVD1
    S1_D0 A0 / CAD26 STSCHG# / CSTSCHG S1_D8 S1_BVD1 <28>
    30 D0 / CAD27 D8 / CAD28 64
    S1_D1 31 65 S1_D9
    S1_D2 D1 / CAD29 D9 / CAD30 S1_D10
    32 D2 / RFU D10 / CAD31 66
    S1_WP 33 67 S1_CD2#
    <28> S1_WP IOIS16# / CCLKRUN# CD2# / CCD2# S1_CD2# <28>
    34 GND GND 68
    +3VS
    +3VS
    SD PWR Control
    69 GND GND 70
    +VCC_5IN1
    2

    S1_A[0..25] 71 72
    +3VS <28> S1_A[0..25] GND GND

    2
    R502 U44 5IN1@ 73 74
    10K_0402_5% R520 S1_D[0..15] GND GND
    <28> S1_D[0..15] 75 GND GND 76
    5IN1@ 1 8 10K_0402_5% 77 78
    GND OUT 5IN1@ GND GND
    2 IN OUT 7 79 GND GND 80
    1

    <28> SDPWREN# 3 IN OUT 6 81 GND GND 82

    1
    <28> XD_MS_PWREN# 4 EN# OC# 5 1 5IN1@ 2 SDOC# <28> 83 GND GND 84
    1 R528 0_0402_5% 85 86
    C C592 GND GND C
    87 GND GND 88
    TPS2041ADR_SO8 +VCC_5IN1
    0.1U_0402_16V4Z

    5IN1@ FOX_WZ21131-G2-P4_RT
    2
    10U_0805_10V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    1 1 1 0.1U_0402_16V4Z 1
    C518 C585 C618
    C617
    5IN1@ 5IN1@ 5IN1@ 5IN1@
    2 2 2 2

    5in1 Socket

    +3VS
    xD PU and PD. Close to Socket
    2 1 XDCD#
    XDCD# <28>
    R493 @ 43K_0402_5%
    +S1_VCC
    +VCC_5IN1
    Reserve for Debug.
    S1_WP 2 1
    43K_0402_5% R436
    2 5IN1@ 1 XDBSY# S1_OE# 2 1
    XDBSY# <28>
    R492 10K_0402_5% 47K_0402_5% R480 JP13
    1 5IN1@ 2 S1_RST 2 1 SDDA1_XDD0 34 11 SDDA3_XDD4
    XDCE# <28> <28> SDDA1_XDD0 SM-D0 / XD-D0 SD-DAT3
    R494 2.2K_0402_5% 47K_0402_5% R433 MSBS_XDD1 33 12 SDDA2_XDCL
    <28> MSBS_XDD1 SM-D1 / XD-D1 SD-DAT2 SDDA2_XDCL <28>
    1 5IN1@ 2 MSCLK_XDRE# S1_CE1# 2 1 <28> MSD0_XDD2
    MSD0_XDD2 32 SM-D2 / XD-D2 SD-DAT1 6 SDDA1_XDD0
    B R449 10K_0402_5% 47K_0402_5% R463 MSD3_XDD3 31 5 IN 1 CONN SD-DAT0 7 SDDA0_XDD7 B
    <28> MSD3_XDD3 SM-D3 / XD-D3
    1 5IN1@ 2 XDWE# S1_CE2# 2 1 <28> SDDA3_XDD4
    SDDA3_XDD4 21 SM-D4 / XD-D4 SD-WP-SW 5 SDWP
    SDWP <28>
    R455 10K_0402_5% 47K_0402_5% R459 MSD2_XDD5 22 10 SDCM_XDALE
    <28> MSD2_XDD5 SM-D5 / XD-D5 SD-CMD
    MSD1_XDD6 23 8 SD_CLK
    <28> MSD1_XDD6 SM-D6 / XD-D6 SD_CLK
    SDDA0_XDD7 24 9 +VCC_5IN1
    <28> SDDA0_XDD7 SM-D7 / XD-D7 SD-VCC
    N/C 4
    XDWP# 35 42 SDCD#
    <28> XDWP# SM_WP-IN / XD_WP-IN SD-CD-SW SDCD# <28>
    SDWP 43 41
    XDWE# SM-WP-SW SD-CD-COM
    <28> XDWE# 36 #SM_-WE / XD_-WE
    SDCM_XDALE 37 15 MSD0_XDD2
    <28> SDCM_XDALE #SM-ALE / XD-ALE MS-DATA0
    SD CLK Close to 14 MSD1_XDD6
    SD_CLK +S1_VCC MS-DATA1 MSD2_XDD5
    25 16
    <28> SD_CLK CardBus Conn. SM_CD# 3
    SM-LVD MS-DATA2
    18 MSD3_XDD3
    <28> SM_CD# SM-CD-SW MS-DATA3
    1

    +VCC_5IN1 29 19 MSCLK_XDRE#
    R450 XDBSY# SM_-VCC / XD_-VCC MS-SCLK MSINS#
    1 1 26 #SM_R/-B / XD_R/-B MS-INS 17 MSINS# <28>
    0_0402_5% @ MSCLK_XDRE# 27 13 MSBS_XDD1
    C194 C193 XDCE# #SM_-RE / XD_-RE MS-BS
    28 #SM_-CE / XD_-CE MS-VCC 20 +VCC_5IN1
    10U_0805_10V4Z 0.1U_0402_16V4Z XDCD# 30
    2 2 #SM_-CD
    2

    1 2 SM-CD-COM XD-VCC 40 +VCC_5IN1


    C536 SDDA2_XDCL 38 39 XDCD#
    10P_0402_50V8K @ SM-CLE / XD-CLE XD-CD
    GND 1
    GND 44
    2
    TAITW_R007-010-N3 5IN1@
    +S1_VPP

    MS CLK 1 1
    MSCLK_XDRE#
    <28> MSCLK_XDRE#
    C187 C188
    1

    4.7U_0805_10V4Z@ 0.01U_0402_25V7Z@
    R454 2 2
    A A
    0_0402_5% @
    2

    1
    C552
    10P_0402_50V8K @
    2 Compal Electronics, Inc.
    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cardbus Slot & 5in1 Socket
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom
    EAL20 LA-2461 0.3

    Date: 星期三, 八月 04, 2004 Sheet 29 of 47


    5 4 3 2 1
    A B C D E

    +3V
    +5VS +3VS +3VS

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

    1 1 1 1 1 1 1 1 1 1 1 1
    C597 C126 C623 KS@ C135 C129 C163 KS@ C139 C191 C176 KS@ C504 C511 C514 KS@
    KS@ KS@ 10U_0805_10V4Z KS@ KS@ 4.7U_0805_10V4Z KS@ KS@ 4.7U_0805_10V4Z KS@ KS@
    2 2 2 2 2 2 2 2 2 2 2 2
    4.7U_0805_10V4Z
    1 1
    1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
    1000P_0402_50V7K

    +3V PCI_AD[0..31]
    PCI_AD[0..31] <22,26,27,28>
    C117 0.1U_0402_16V4Z
    KS@

    5
    U13 JP10
    1 TIP 1 2 RING
    <34> WL_OFF#

    P
    B 1 2
    Y 4 KEY KEY
    <32,34> KILL_SW# 2 A 3 3 4 4

    G
    KS@ 5 6
    5 6
    7 7 8 8

    3
    TC7SH08FU_SSOP5 9 10
    D7 9 10
    11 11 12 12
    KS@ 1 2 13 14
    RB751V_SOD323 13 14
    15 15 16 16
    <22> PCI_PIRQH# 17 17 18 18 W=40mils +5VS
    +3VS W=40mils 19 19 20 20 PCI_PIRQG# <22>
    21 22 PCI_GNT#4
    <22> PCI_REQ#4 21 22 PCI_GNT#4 <22>
    23 23 24 24 W=40mils +3V
    CLK_PCI_MINI 25 26
    2 <12> CLK_PCI_MINI 25 26 PCIRST# <7,13,19,22,25,27,28> 2
    27 27 28 28 W=40mils +3VS
    PCI_REQ#3 29 30 PCI_GNT#3
    <22> PCI_REQ#3 29 30 PCI_GNT#3 <22>
    31 31 32 32
    PCI_AD31 33 34
    PCI_AD29 33 34 MINI_PME# <26,28,34>
    35 35 36 36
    37 38 PCI_AD30
    PCI_AD27 37 38
    39 39 40 40
    PCI_AD25 41 42 PCI_AD28
    41 42 PCI_AD26
    43 43 44 44
    45 46 PCI_AD24
    <22,26,27,28> PCI_CBE#3 45 46
    CLK_PCI_MINI PCI_AD23 47 48 MINI_IDSEL 1 2 R170 PCI_AD18
    47 48 KS@ 100_0402_5%
    49 49 50 50
    PCI_AD21 51 52 PCI_AD22
    51 52
    1

    PCI_AD19 53 54 PCI_AD20
    R164 53 54
    55 55 56 56 PCI_PAR <22,26,27,28>
    PCI_AD17 57 58 PCI_AD18
    @ 10_0402_5% PCI_CBE#2 57 58 PCI_AD16
    <22,26,27,28> PCI_CBE#2 59 59 60 60
    PCI_IRDY# 61 62
    <22,26,27,28> PCI_IRDY# 61 62
    2

    1 63 64 PCI_FRAME#
    63 64 PCI_FRAME# <22,26,27,28>
    C132 65 66 PCI_TRDY#
    <23,26,33,34> PM_CLKRUN# 65 66 PCI_TRDY# <22,26,27,28>
    PCI_SERR# 67 68 PCI_STOP#
    <22,26,28> PCI_SERR# 67 68 PCI_STOP# <22,26,27,28>
    @ 10P_0402_50V8K 69 70
    2 PCI_PERR# 69 70 PCI_DEVSEL#
    <22,26,27,28> PCI_PERR# 71 71 72 72 PCI_DEVSEL# <22,26,27,28>
    PCI_CBE#1 73 74
    <22,26,27,28> PCI_CBE#1 PCI_AD14 73 74 PCI_AD15
    75 75 76 76
    77 78 PCI_AD13
    PCI_AD12 77 78 PCI_AD11
    79 79 80 80
    PCI_AD10 81 82
    81 82 PCI_AD9
    83 83 84 84
    PCI_AD8 85 86 PCI_CBE#0
    PCI_AD7 85 86 PCI_CBE#0 <22,26,27,28>
    87 87 88 88
    3 89 90 PCI_AD6 3
    PCI_AD5 89 90 PCI_AD4
    91 91 92 92
    93 94 PCI_AD2
    PCI_AD3 93 94 PCI_AD0
    95 95 96 96
    +5VS W=40mils 97 97 98 98
    PCI_AD1 99 100
    99 100
    101 101 102 102
    103 103 104 104
    105 105 106 106
    107 107 108 108
    109 109 110 110
    111 111 112 112
    113 113 114 114
    115 115 116 116
    117 117 118 118
    119 119 120 120
    W=30mils 121 121 122 122 W=40mils
    +5VS 123 123 124 124 +3V
    KS@ AMP_1318644-1

    4 4

    Compal Electronics, Inc.


    Title
    Mini PCI Slot
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 30 of 47
    A B C D E
    A B C D E F G H

    +AVDD_AC97 +AC97_DVDD
    L27
    Direct CD
    AC97 Codec +5VAMP 1 2
    1 2
    L28 0_0805_5%
    +3VS
    CTL POWER ON PATH
    0_0805_5% 1 2 +5VALWP
    +3V
    L26 1 1 0_0805_5%
    1 1

    14
    INT_CD_L 2 1 CD_L C604 C646 SN74HCT4066PW_TSSOP14
    <25> INT_CD_L 10U_0805_10V4Z R607
    R583 20K_0402_5% 0.1U_0402_16V4Z C609 C632 @ U48A

    P
    INT_CD_R2 CD_R 2 2 0.1U_0402_16V4Z 10U_0805_10V4Z AMP_LEFT
    <25> INT_CD_R 1 +5VAMP 2 1 1 A B 2
    R587 20K_0402_5% 2 2 @ 1M_0402_5%

    C
    CD_GNA

    1M_0402_5%
    2 1
    <25> CD_AGND R585 20K_0402_5% L_OUT_L R608

    25

    38

    13
    1

    9
    U45 1 2 @
    2

    R593 R586 R584 R588 C616 @ 1000P_0402_50V7K

    AVDD1

    AVDD2

    DVDD1

    DVDD2
    1 1

    6.8K_0402_5%

    6.8K_0402_5%
    1 2

    6.8K_0402_5%

    14
    2
    0_0402_5% C611 @ 1000P_0402_50V7K SN74HCT4066PW_TSSOP14
    R609 @ U48B

    P
    2

    2
    14 35 LINEL 1 2 L_OUT_L 2 1 11 A AMP_RIGHT
    AUX_L LINE_OUT_L +5VAMP B 10
    1

    bypass EQ when NBA_PLUG = High C615 1U_0402_6.3V4Z @ 1M_0402_5%

    C
    LINER L_OUT_R

    1M_0402_5%
    15 AUX_R LINE_OUT_R 36 1 2
    C612 1U_0402_6.3V4Z L_OUT_R R610

    12
    16 37 @
    NBA_PLUG JD2 MONO_OUT/VREFOUT3
    <32> NBA_PLUG
    R590 1 2 17 JD1 HP_OUT_L 39
    +3VS

    2
    C651 1U_0402_6.3V4Z
    MD_SPK 1 2 C_MD_SPK 1 2 23 41 C626 47P_0402_50V8J
    C649 0.1U_0402_16V4Z LINE_IN_L HP_OUT_R
    1 1 2 1
    1

    2
    0_0402_5% PATH_SEL
    0.01U_0402_25V4Z

    1 2 24 LINE_IN_R
    C656 C653 R582 C650 0.1U_0402_16V4Z 6 1 2
    BIT_CLK AC97_BITCLK <23>
    @ @ 10K_0402_5% CD_L 2 1 CD_LIN 18 R555 33_0402_5% R519
    0.1U_0402_16V4Z 2 2 C641 1U_0402_6.3V4Z CD_L @ 10K_0402_5% +5VALWP
    SDATA_IN 8 1 2 AC97_SDIN0 <23> DIRECT PLAY PATH
    CD_R 2 1 CD_R IN 20 R561 33_0402_5%
    CD_R
    2

    1
    C643 1U_0402_6.3V4Z 2 XTL_IN 1 2

    14
    XTL_IN CLK_14M_CODEC <12>
    CD_GNA 2 1 CD_GNA1 19 R527 SN74HCT4066PW_TSSOP14
    CD_GND

    2
    C642 1U_0402_6.3V4Z @ 0_0402_5% R611 @ U48C

    P
    MIC 2 1 C_MIC 21 2 1 4 AMP_LEFT
    <32> MIC
    C644 1U_0402_6.3V4Z MIC1 R517
    +5VAMP
    @ 1M_0402_5% A B 3
    +AVDD_AC97

    C
    XTL_OUT @ 10K_0402_5%

    1M_0402_5%
    22 MIC2 XTL_OUT 3
    Use to isolate +5VALW and +AC97_DVDD C698 R612

    5
    C_MD_SPK 2 1 13 29 1 2 INT_CD_L 1 2 @
    PHONE AFILT1

    2
    C648 1U_0402_6.3V4Z C630 1000P_0402_50V7K
    MONO_IN 12 30 1 2 @ 1U_0603_10V4Z

    14
    PC_BEEP AFILT2

    2
    Use to isolate +5VALW and +AC97_DVDD C628 1000P_0402_50V7K R602 SN74HCT4066PW_TSSOP14
    28 +VREFOUT 1 2 1M_0402_5% R613 @ U48D
    +AUD_VREF

    P
    AC97_RST# VREFOUT R566 0_0603_5% AMP_RIGHT
    <23> AC97_RST# 1 2 11 RESET# +5VAMP 2 1 8 A B 9

    1
    R511 2 1 R578 33_0402_5% 27 @ 1M_0402_5%
    VREF

    C
    2 10K_0402_5% AC97_SYNC 2 2

    1M_0402_5%
    <23> AC97_SYNC 1 10 SYNC
    +AC97_DVDD 2 1 R577 33_0402_5% 32 C699 R614
    DCVOL

    6
    R510 1K_0402_5% AC97_SDOUT 2 1 5 INT_CD_R 1 2 @
    <23> AC97_SDOUT SDATA_OUT
    R550 33_0402_5%

    0.01U_0402_16V7K

    1U_0402_6.3V4Z

    0.1U_0402_16V4Z

    1U_0402_6.3V4Z
    2

    Q40 EC_SM_D2 45 31 @ 1U_0603_10V4Z


    G

    SDA NC 1 1 1 1

    2
    2N7002_SOT23 46 33 C621 C622 C635 C636
    EC_SM_D2 XTLSEL VREFOUT2 +VAUX 1

    1U_0402_6.3V4Z
    <4,34> EC_SMD_2 1 3 VAUX 34 2 +AVDD_AC97

    1
    47 43 R518 0_0603_5% R546 1
    D

    <32> EAPD_CODEC SPDIFI/EAPD DISABLE# 2 2 2 2

    0_0402_5%
    44 EC_SM_C2 PATH_SEL_1
    SCK
    1

    1 2 48 @
    R549 @ 0_0402_5% R521 SPDIFO C624
    NC 40
    R512 2 0_0402_5% 2
    1 Ra 4 DVSS1 AVSS1 26

    2
    10K_0402_5% @ 7 42 AGND L_OUT_L 1 R619 2AMP_LEFT
    DVSS2 AVSS2 0_0402_5% AMP_LEFT <32>
    +AC97_DVDD 2 1
    2

    R513 1K_0402_5% ALC250-C_LQFP48 L_OUT_R 1 R620 2AMP_RIGHT


    +5VALWP 0_0402_5% AMP_RIGHT <32>
    DGND AGND 1 2 +3VS
    2

    Q39 R523 10K_0402_5%


    G

    2N7002_SOT23 UnPoped:Clock source from X'tal 1 2 EC_IDERST <25,34>

    2
    <4,34> EC_SMC_2 1 3 EC_SM_C2
    Poped: Clock source from Clock Gen Place these components R522 0_0402_5%
    R615
    D

    close to Codec 10K_0402_5%


    1 2 1 2 @
    R535 @ 0_0402_5% R540 @ 1M_0402_5% R616

    1
    X3 PATH_SEL_1 2 1 EC_IDERST
    XTL_IN 2 1 XTL_OUT @ 0_0402_5%
    D

    1
    R617
    24.576MHz_16P_3XG-24576-43E1 C638 4.7U_0805_10V4Z 2 PATH_SEL 2 1 SUSP# <34,37,42,43,44>
    Q43

    22P_0402_50V8J
    1 1 +AUD_VREF 1 2 G
    C610 C619 2N7002_SOT23 S @ @ 0_0402_5%
    22P_0402_50V8J

    3
    GND Connect AGND 1 2
    Keep a 80mil bridge far away from DC-DC area 2 2 C629 0.1U_0402_16V4Z
    3 3

    System Sound +3V +3VALW


    +AVDD_AC97
    1
    1

    C206 R581
    <34> BEEP#
    R189 10K_0402_5%
    100K_0402_5%
    1 2

    0.1U_0402_16V4Z
    MDC Connector
    2
    13

    14
    2

    U15D U17A 1 2 1 MD_SPK


    +3V
    1

    R193 C209 R200 C659 0_0805_5% R187 2 JP14 L11


    P
    OE#

    12 11 1 2 1 2 1 2 1 2 R594 10U_0805_10V4Z +5VS_MDC 1 2


    I O I O +5VS
    8.2K_0402_5% 10K_0402_5% C184 1 2 2 0_0603_5%
    2 MONO_OUT/PC_BEEP AUDIO_PWRDN/DETECH
    G

    1U_0402_6.3V4Z 560_0402_5% 10U_0805_10V4Z 3 4

    +3V_MDC
    1 1 GND MONO_PHONE
    SN74LVC125APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 5 6 C204 1U_0603_10V4Z
    AUXA_RIGHT RESERVED/BT_ON#
    7

    C211 +3V POWER C647 0_0603_5% 7 8


    0.22U_0402_10V4Z MONO_IN_O MONO_IN AUXA_LEFT GND 1
    2 1 +3VS 1 2+3VS_MDC 9 CD_GND +5Vmain 10
    2 L9 2 11 CD_RIGHT RESERVED/USB+ 12
    1U_0402_6.3V4Z 13 14 R192
    C183 CD_LEFT RESERVED/USB- +3VS_MDC_R
    15 GND RESERVED/PRIMARY_DN 16 1 2 +3VS
    2

    R201 10U_0805_10V4Z 17 18 10K_0402_5%


    1 +3.3Vaux/BT_VCC RESERVED/+5VD/WAKEUP
    1

    C210 C Q42 R591 19 20


    MONO_IN_I R488 GND RESERVED/GND R507 1
    <28> PCM_SPK# 1 2 1 2 2 21 +3.3Vmain AC97_SYNC 22 2 33_0402_5% AC97_SYNC
    B AC97_SDOUT 2 33_0402_5%
    2.4K_0402_5%

    1 23 AC97_SDATA_OUT AC97_SDATA_IN1 24 2 1 1 2 AC97_SDIN1 <23>


    1U_0402_6.3V4Z 560_0402_5% E AC97_RST# 2 33_0402_5% R191 0_0402_5% R194 33_0402_5%
    2SC2411K_SC59

    1 25 AC97_RESET# AC97_SDATA_IN0 26
    3

    R489 27 28
    GND GND R190 1 AC97_BITCLK
    +3VALW 29 AC97_MSTRCLK AC97_BITCLK 30 2 33_0402_5%
    4 4
    +3V POWER
    ACES_88018-3010
    14

    U17B
    C212 R202
    P

    <23> SB_SPKR 3 I O 4 1 2 1 2
    G

    1U_0402_6.3V4Z 560_0402_5%
    Compal Electronics, Inc.
    1

    SN74LVC14APWLE_TSSOP14
    7

    Title
    R203
    10K_0402_5%
    D8
    RB751V_SOD323
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AC97 CODEC ALC250 Ver.C
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    2

    0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 31 of 47
    A B C D E F G H
    A B C D E

    Audio AMP Audio Board Connector


    +5VAMP

    W=40Mil
    W/O EQ R385=R386= 1.3K Ohm SHUTDOWN# 2 1 +5VAMP
    C537=C539= 0.47U 1 1 R597 100K_0402_5%
    JP20
    R = R385, R386 C245 C663
    D +5VAMP 1 1 13 13

    1
    C = C537, C539 0.1U_0402_16V4Z 4.7U_0805_10V4Z NBA_PLUG 2 14
    2 2 Q41 EAPD VOL_AMP 2 14
    2 3 3 15 15
    fo=1/(2*3.14*R*C)=260Hz G +AUD_VREF 4 4 16 16
    R=1.5K / C=0.47U 2N7002_SOT23S 5 17
    5 17

    3
    1 MIC 1
    <31> MIC 6 6 18 18
    7 7 19 19
    HIGH PIN 10,4 ACTIVE INTSPK_R1 8 8 20 20
    Pin 22 U21 INTSPK_L1 9 9 21 21
    LOW PIN 9,5 ACTIVE 7 22 10 22
    PVDD SHUTDOWN# NBA_PLUG 10 22
    18 PVDD SE/BTL# 15 <34> WL_LED# 11 11 23 23
    19 VDD PC-BEEP 14 1 2 <30,34> KILL_SW# 12 12 24 24
    11 C239 0.1U_0402_16V4Z
    <31> NBA_PLUG BYPASS
    NBA_PLUG 2 9 INTSPK_L2 ACES_85203-1202
    VOL_AMP HP/LINE# LOUT- INTSPK_R2
    2 1 3 VOLUME ROUT- 16
    C235 0.1U_0402_16V4Z INTSPK_L1 4 10
    INTSPK_R1 LOUT+ LIN
    21 ROUT+ RIN 8
    AMP_LEFT 1 2 AMP_L 1 2 AMP_LIN 5
    <31> AMP_LEFT LLINEIN
    C240 0.47U_0603_16V4Z C237 0.47U_0603_16V4Z AMP_RIN 23 1
    AMP_RIGHT AMP_R RLINEIN GND

    0.47U_0603_16V4Z

    0.47U_0603_16V4Z

    0.47U_0603_16V4Z
    <31> AMP_RIGHT 1 2 1 2 6 LHPIN GND 12
    C661 0.47U_0603_16V4Z C665 0.47U_0603_16V4Z 20 13 2 1 1
    AMP_LEFT HP_L RHPIN GND
    1 2 GND 24
    C241 0.47U_0603_16V4Z 17
    AMP_RIGHT HP_R CLK C253 C251 C252
    1 2
    C666 0.47U_0603_16V4Z TPA0232PWP_TSSOP24 1 2 2
    1
    1.5K_0402_5% 2 1 R221 AMP_L C238
    0.047U_0402_16V4Z (0.47U~1U)
    1.5K_0402_5% 2 2
    1 R596 AMP_R

    +3VALW

    14
    U9A
    <31> EAPD_CODEC 1 Speaker Connector

    P
    2 A EAPD 2
    O 3
    <34> EAPD_KBC 2 B

    G
    SN74LVC32APWLE_TSSOP14

    1
    D28 D27
    V-PORT-0603-220 M-V05_0603 @ @ V-PORT-0603-220 M-V05_0603

    JP19

    2
    INTSPK_R1 L34 1 2 FBM-11-160808-121-T_0603
    INTSPK_R2 L33 FBM-11-160808-121-T_0603 1
    1 2 2
    INTSPK_L1 L32 FBM-11-160808-121-T_0603
    Regulator for AMP INTSPK_L2 L31
    1
    1
    2
    2 FBM-11-160808-121-T_0603 3
    4
    ACES_85204-0400

    1
    D26 D25
    +5VALW DECOUPLING
    +5VALW TO +5VLDO
    V-PORT-0603-220 M-V05_0603 @ @ V-PORT-0603-220 M-V05_0603
    +5VALWP

    2
    +5VALWP
    3

    R232 10K_0402_5%
    22U_1206_16V4Z_V1

    1 2 2
    22U_1206_16V4Z_V1

    1U_0603_10V4Z

    1U_0603_10V4Z
    1
    Q19
    C254 1 1 1 1
    1U_0603_10V4Z AOS 3401_SOT23 C244 C243
    2
    1

    C255 C249
    3 @ 3
    +5VALW_LDO 2 2 2 2
    +5VALWP +12VALW
    Moat Bridge
    5
    6
    7
    8
    D
    D
    D
    D
    1

    R230 R215 SI4800 1N_SO8


    U20
    G
    S
    S
    S

    (4.5V)
    10K_0402_5% 1K_0402_5%
    4
    3
    2
    1

    +5VLDO DECOUPLING
    2

    +5VLDO
    D
    1

    1U_0805_25V4Z

    1
    2 Q20 C234 +5VLDO (4.5V)
    G
    S 2N7002_SOT23 @ 1 2
    2
    3

    R223 0_0805_5%
    D
    1

    R595
    0.1U_0402_10V6K
    22U_1206_16V4Z_V1

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    1U_0603_10V4Z

    0.1U_0402_16V4Z

    1 2
    CD_PLAY LM431SB_SOT23 R516 0_0805_5%
    1U_0603_10V4Z

    <25,34> CD_PLAY 2
    G 3.9K_0603_1% 1 2
    Q21 S 2 1 1 1 1 1 1 1 R567 0_0805_5%
    K
    3

    2N7002_SOT23 C645 C660 C652 C662 C664 C657 C658


    1 A @ @ @
    2 2 2 2 2 2 2
    R 3
    1

    D13 R592

    4.99K_0603_1%
    +5VAMP TO +5VLDO
    2

    4 L29 4

    +5VLDO 1 2 +5VAMP
    0_0805_5%

    L30
    1 2
    0_0805_5%

    Compal Electronics, Inc.


    Title
    AMP & Audio Jack
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 32 of 47
    A B C D E
    10 9 8 7 6 5 4 3 2 1

    SUPER I/O SMsC LPC47N217


    +3VS FIR Module L: R POP; FIR Enable
    H: R De-POPFIR Disable

    1 1 1 1
    H C45 SIO@ C53 SIO@ C32 SIO@ C69 SIO@ H
    +3VS FIR_DET#
    4.7U_0805_10V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    1 2
    IRRX 1 2 FIR@ R112 0_0402_5%
    2 2 2 2 RP2 R357 FIR@
    DCD#1 8 1 10K_0402_5%
    RI#1 7 2
    DSR#1 6 3
    CTS#1 5 4
    SIO@ +IR_ANODE
    4.7K_1206_8P4R_5%
    for VISHAY FIR issue +3VS 1
    R157
    2
    4.7_1206_5% @
    1
    R160
    2
    4.7_1206_5% FIR@
    W=60mil

    G G
    U8 SIO@ 1K_0402_5%
    LPC_AD0 10 62 RXD1 R62 1 2 U38
    <23,34> LPC_AD0 LPC_AD1 LAD0 RXD1 TXD1
    12 63 1

    SERIAL I/F
    <23,34> LPC_AD1 LAD1 TXD1 +IR_3VS IRED_A
    LPC_AD2 13 64 DSR#1 2 3 T = 12mil IRTXOUT
    <23,34> LPC_AD2 LPC_AD3 LAD2 DSR1# RTS#1 IRRX IRED_C TXD IRMODE
    <23,34> LPC_AD3 14 LAD3 RTS1# 1 4 RXD SD/MODE 5 T = 12mil
    2 CTS#1 +3VS 1 2 +IR_3VS 6 7
    LPC_FRAME# CTS1# DTR#1 R163 FIR@ VCC MODE
    <23,34> LPC_FRAME# LPC_DRQ#1
    15 LFRAME# DTR1# 3
    RI#1 47_1206_5%
    W=40mil 8 GND
    <23> LPC_DRQ#1 16 LDRQ# RI1# 4 1 1
    DCD#1 C130 C125 TFDU6102-TR3_8P FIR@

    LPC I/F
    DCD1# 5
    B_PCIRST# 17 FIR@ FIR@
    <22,26,34> B_PCIRST# PCI_RESET#
    R109 1 SIO@ 2 10K_0402_5% SIO_PD# IRRX 10U_0805_10V4Z 0.1U_0402_16V4Z
    +3VS 18 LPCPD#
    FIR IRRX2 37
    38 IRTXOUT 2 2 Change to Vishay 6102
    PM_CLKRUN# IRTX2 IRMODE
    <23,26,30,34> PM_CLKRUN# 19 CLKRUN# IRMODE/IRRX3 39
    CLK_PCI_SIO 20
    <12> CLK_PCI_SIO PCI_CLK
    SIRQ 21 41 LPTINIT#
    F <22,28,34> SIRQ SER_IRQ INIT# F
    1 2 SIO_PME# 6 42 LPTSLCTIN#
    +3VS R76 SIO@ 10K_0402_5% IO_PME# SLCTIN# LPD0
    PD0 44
    CLK_14M_SIO 9 46 LPD1
    <12> CLK_14M_SIO CLK14 PD1 LPD2
    CLOCK PD2 47
    LPD3

    Parallel Port
    23 GPIO40 PD3 48

    PARALLEL I/F
    R104 100K_0402_5% NOT-FIR@ 24 49 LPD4
    GPIO41 PD4 LPD5
    +3VS 2 1 25 GPIO42 PD5 50
    27 51 LPD6
    FIR_DET# GPIO43 PD6 LPD7 +5V_PRN
    28 53

    GPIO
    GPIO44 PD7 LPTSLCT
    29 55 D16
    LPT_DET# GPIO45 SLCT LPTPE W=20mil
    30 GPIO46 PE 56 +5VS 2 1
    R105 100K_0402_5% NOT-PIO@ 31 57 LPTBUSY PIO@
    GPIO47 BUSY LPTACK#
    +3VS 2 1 32 GPIO10 ACK# 58 RB420D_SOT23 1

    1
    R92 2 1 1K_0402_5% SIO_GPIO11 33 59 LPTERR# PIO@
    SIO@ R95 1 SIO@ SIO_SMI# GPIO11/SYSOPT ERROR# LPTAFD#
    +3VS 2 10K_0402_5% 34 GPIO12/IO_SMI# ALF# 60 R239 C264 RP32
    R362 1 SIO@ 2 10K_0402_5% SIO_IRQ 35 61 LPTSTB# PIO@ 0.1U_0402_16V4Z
    E GPIO13/IRQIN1 STROBE# 2 E
    36 2.2K_0402_5% LPD3 1 8 F D3
    R82 SIO_GPIO23 GPIO14/IRQIN2 LPD2 F D2
    1 SIO@ 2 10K_0402_5% 40 GPIO23 2 7

    2
    W=20mil LPD1 3 6 F D1
    8 7 +3VS LPD0 4 5 F D0
    VSS VTR LPTSTB# 1 +5V_PRN_R
    22 VSS VCC 11 2
    43 POWER 26 PIO@ R238 33_0402_5% PIO@ 33_1206_8P4R_5%
    VSS VCC JP1
    52 VSS VCC 45
    54 RP35
    VCC LPD7 F D7
    1 1 8
    CLK_14M_SIO CLK_PCI_SIO LPC47N217_STQFP64 SIO@ LPTAFD# 1 2 AFD/3M# 14 LPD6 2 7 F D6
    PIO@ R235 33_0402_5% F D0 2 LPD5 3 6 F D5
    2

    Base I/O Address LPTERR# 15 LPD4 4 5 F D4


    R81 R110 * 0 = 02Eh F D1 3
    10_0402_5% 33_0402_5% 1 = 04Eh LPT_INIT# 16 PIO@ 33_1206_8P4R_5%
    @ @ F D2 4
    D SLCTIN# 17 LPTINIT# 1 2 LPT_INIT# D
    1

    2 2 F D3 5 PIO@ R237 33_0402_5%


    18
    C47 C81 F D4 6 LPTSLCTIN# 1 2 SLCTIN#
    @ 15P_0402_50V8J @ 22P_0402_50V8J 19 PIO@ R236 33_0402_5%
    1 1 F D5 7
    20
    F D6 8
    21 +5V_PRN
    F D7 9
    22
    LPTACK# 10 RP33 CP8
    23 1 8 F D0 AFD/3M# 1 8
    LPTBUSY 11 2 7 F D1 LPTERR# 2 7
    24 3 6 F D2 LPT_INIT# 3 6
    C LPTPE 12 4 5 F D3 SLCTIN# 4 5 C
    25 PIO@
    LPTSLCT 13 PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K

    RP34 CP10
    PIO@ FOX_DZ11391-H7 1 8 F D7 LPTACK# 1 8
    2 7 F D6 LPTBUSY 2 7
    3 6 F D5 LPTPE 3 6
    4 5 F D4 LPTSLCT 4 5
    PIO@
    PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K

    RP31 CP9
    1 8 SLCTIN# F D0 1 8
    2 7 LPT_INIT# F D1 2 7
    3 6 LPTERR# F D2 3 6
    B Place on the TOP side(Under MDC conn.) 4 5 AFD/3M# F D3 4 5 B
    L: R POP; PIO Enable PIO@
    H: R De-POP PIO Disable PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K
    +5VS
    RP36 CP7
    1 8 LPTACK# F D4 1 8
    JP9 2 7 LPTBUSY F D5 2 7
    1 LPT_DET# 1 2 3 6 LPTPE F D6 3 6
    1 PIO@ R113 0_0402_5% LPTSLCT F D7
    2 2 4 5 4 5
    RXD1 3 PIO@
    TXD1 3 PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K
    4 4
    DSR#1 5
    RTS#1 5
    6 6
    CTS#1 7 7
    A
    DTR#1
    RI#1
    8
    9
    8 Compal Electronics, Inc. A
    DCD#1 9 Title
    10 10
    @ E&T_96212-1011S
    SMsC LAP47N217 SIO,PIO,FIR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    For SW debug use when no seial port
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    Custom
    EAL20 LA-2461
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期三, 八月 04, 2004 Sheet 33 of 47
    10 9 8 7 6 5 4 3 2 1
    A B C D E

    +3VALW +EC_RTCVCC
    +EC_AVCC
    1
    R56
    2
    0_0402_5%
    +3VALW
    JP23 For EC Tools
    0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1 2 1
    +3VALW +RTCVCC 1 +3VALW
    1 1 1 1 1 1 2 R59 @ 0_0402_5% 2
    2

    ECAGND
    C105 C367 C372 C371 C462 C427 C31
    For ENE KB910 Rev.B4 3 3
    4 4
    1U_0603_10V4Z 5 5
    2 2 2 2 2 2 1
    6 6
    7 7

    123
    136
    157
    166

    161

    159
    4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 8 E51_RXD

    16
    34
    45

    95

    96
    U35 KSO[0..15] 8 E51_TXD
    KSO[0..15] <36> 9 9
    L23 <23,33> LPC_AD0 15 10

    VCC
    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    VCCA

    AGND

    VCCBAT

    BATGND
    LAD0 KSO0 KSI[0..7] 10
    +3VALW 1 2 +EC_AVCC <23,33> LPC_AD1 14 LAD1 GPOK0/KSO0 49 KSI[0..7] <36>
    FBM-L11-160808-800LMT_0603 2 1 13 50 KSO1 @ E&T_96212-1011S
    <23,33> LPC_AD2 LAD2 GPOK1/KSO1 ADB[0..7]
    10 51 KSO2
    1 C463 <23,33> LPC_AD3 LAD3 GPOK2/KSO2 ADB[0..7] <35> +3VALW 1
    C467 KSO3
    0.1U_0402_16V4Z
    <23,33> LPC_FRAME# 9 LFRAME# LPC Interface GPOK3/KSO3 52
    KSO4 KBA[0..18]
    <22,26,33> B_PCIRST# 165 LRST#/GPIO2C GPOK4/KSO4 53 KBA[0..18] <35>
    1 2

    ENE-KB910-B4
    L8 CLK_PCI_LPC 18 56 KSO5
    ECAGND <12> CLK_PCI_LPC LCLK GPOK5/KSO5 KSO6 KBA5
    1 2 <22,28,33> SIRQ 7 SERIRQ GPOK6/KSO6 57 1 2
    FBM-L11-160808-800LMT_0603 1000P_0402_50V7K 25 58 KSO7 R348 1K_0402_5%
    <23,26,30,33> PM_CLKRUN# CLKRUN#/GPIO0C * GPOK7/KSO7
    24 59 KSO8 KBA4 1 2
    LPCPD#/GPIO0B * GPOK8/KSO8 KSO9 R55 1K_0402_5%
    GPOK9/KSO9 60
    FREAD# 150 61 KSO10 KBA1 1 2
    <35> FREAD# RD# GPOK10/KSO10
    FW R# 151 64 KSO11 R57 1K_0402_5%

    Internal Keyboard
    <35> FWR# WR# GPOK11/KSO11
    FSEL# 173 65 KSO12 1 2
    +5VS <35> FSEL# MEMCS# GPOK12/KSO12
    152 66 KSO13 R622 @ 10K_0402_5%
    ADB0 IOCS# GPOK13/KSO13 KSO14
    138 D0 GPOK14/KSO14 67 1 2
    RP3 ADB1 139 68 KSO15 R623 @ 10K_0402_5%
    PSCLK1 ADB2 D1 GPOK15/KSO15
    1 8 140 D2 GPOK16/KSO16 153 1 2
    2 7 PSDATA1 ADB3 141 154 KSO17 R624 @ 10K_0402_5%
    D3 GPOK17/KSO17 KSO17 <36>
    3 6 TP_DATA ADB4 144
    TP_CLK ADB5 D4 KSI0 SKU_ID0
    4 5 145 D5 GPIK0/KSI0 71 1 2
    ADB6 KSI1 R625 10K_0402_5%

    X-BUS Interface
    146 D6 GPIK1/KSI1 72
    10K_1206_8P4R_5% ADB7 147 73 KSI2 SKU_ID1 1 2
    KBA0 D7 GPIK2/KSI2 KSI3 R626 10K_0402_5%
    124 A0 GPIK3/KSI3 74
    1 2 PSDATA2 KBA1 125 A1/XIOP_TP GPIK4/KSI4 77 KSI4 SKU_ID2 1 2
    R111 10K_0402_5% KBA2 126 78 KSI5 R627 10K_0402_5%
    A2 GPIK5/KSI5
    1 2 PSCLK2 KBA3 127 A3 GPIK6/KSI6 79 KSI6
    R114 10K_0402_5% KBA4 128 80 KSI7
    KBA5 A4/DMRP_TP GPIK7/KSI7
    131 A5/EMWB_TP
    KBA6 132 32
    A6 GPOW0/PWM0 INVT_PWM <20>
    KBA7 133 33
    +3VALW A7 GPOW1/PWM1 BEEP# <31>
    KBA8 143 36
    A8 FAN2PWM/GPOW2/PWM2 SUSP_LED <36>
    KBA9 142 37
    A9 GPOW3/PWM3 ACOFF <40>
    1 2 FSEL# KBA10 135 Pulse Width GPOW4/PWM4 38
    A10 PM_BATLOW# <23>
    R353 10K_0402_5% KBA11 134 39
    2 A11 GPOW5/PWM5 EC_ON <36> 2
    1 2 MUL_KEY# KBA12 130 40
    A12 GPOW6/PWM6 EC_LID_OUT# <23>
    R387 10K_0402_5% KBA13
    1 2 FREAD# KBA14
    129
    121
    A13 FAN1PWM/GPOW7/PWM7 43 S4_LATCH <36> Board ID
    R316 10K_0402_5% KBA15 A14
    120 A15 GPWU0 2 ON/OFFBTN# <36>
    EC_SMI# KBA16 +3VALW
    1 2 113 A16 GPWU1 26 ACIN <22,36,38>
    R392 10K_0402_5% KBA17 112 29
    A17 GPWU2 KILL_SW# <30,32>
    KBA18 104 30
    A18 GPWU3 SLP_S3# <23>

    1
    103 A19 Wake Up Pin GPWU4 44 PM_SLP_S5# <23>
    R135
    +3VALW R375 2 1 10K_0402_5% EC_TINIT#
    108
    105
    A20/GPIO23 GPWU5 76
    172
    SLP_S1# <12,23> Ra 10K_0402_5%
    E51CS#/GPIO20/ISPEN TIN1/GPWU6 PCI_PME# <26,28,30>
    TIN2/FANFB2/GPWU7 176 BATT_TEMP <39>
    PSCLK1 110 PSCLK1

    2
    PSDATA1 111 81 1 2 ECAGND AD_BID0
    PSCLK2 PSDAT1 GPIAD0/AD0 ADP_IR C110 0.01U_0402_16V7K 1 R141
    114 PSCLK2 GPIAD1/AD1 82 2 ADP_I <40>

    1
    PSDATA2
    <36> TP_CLK
    TP_CLK
    115
    116
    PSDAT2PS2
    PSCLK3
    Interface GPIAD2/AD2
    GPIAD3/AD3
    83
    84 AD_BID0
    BATT_OVP <40> 10K_0402_5%
    * Rb R140
    +5VALW TP_DATA 117 Analog To Digital 87 0_0402_5%
    <36> TP_DATA PSDAT3 GPIAD4/AD4 LI/NIMH# <39> 1
    RP1 88
    GPIAD5/AD5 S4_DATA <36>
    8 1 EC_SMD_2 EC_SMC_1 163 89 MUL_KEY# C109
    <35,39> EC_SMC_1 SCL1 GPIAD6/AD6 MUL_KEY# <36>

    2
    7 2 EC_SMC_2 EC_SMD_1 164 90 0.22U_0603_16V7K
    <35,39> EC_SMD_1 SDA1 GPIAD7/AD7 2
    6 3 EC_SMC_1 EC_SMC_2 169 SMBus
    <4,31> EC_SMC_2 SCL2
    5 4 EC_SMD_1 <4,31> EC_SMD_2 EC_SMD_2 170 99
    SDA2 GPODA0/DA0 DAC_BRIG <20>
    GPODA1/DA1 100
    10K_1206_8P4R_5% 8 101
    +3VALW GPIO04 GPODA2/DA2 IREF <40>
    SCI# 20 102
    <23> SCI# GPIO07 GPODA3/DA3 EN_DFAN1 <4>
    21 GPIO08 Digital To Analog GPODA4/DA4 1
    CD_PLAY <25,32>
    1 2 LID_SW# 22 42
    R371 20K_0402_5% ENBKL GPIO09 GPODA5/DA5
    <13> ENBKL 27 GPIO0D GPODA6/DA6 47
    28 174 +3VALW
    <20> BKOFF# GPIO0E GPODA7/DA7
    <40> FSTCHG 48 GPIO10
    CLK_PCI_LPC EC_SMI# 62 85
    <23> EC_SMI# GPIO13 * GPIO18/XIO8CS# MODE_LED# <36>

    1
    3 EC_IDERST 63 86 3
    <25,31> EC_IDERST GPIO14 * GPIO19/XIO9CS# CHARGING_LED# <36>
    69 91 R61
    <30> WL_OFF# GPIO15 * GPIO1A/XIOACS# DEV_LED# <36>
    1

    <23> EC_RIOUT# 70 GPIO16 GPIO * GPIO1B/XIOBCS# 92 POWER_LED# <36> 100K_0402_5%


    R366 SKU_ID2 75 Expanded I/O * GPIO1C/XIOCCS# 93 SKU_ID0
    GPIO17 SKU_ID1
    109 GPIO24 94
    * GPIO1D/XIODCS#

    2
    @ 10_0402_5% LID_SW# 118 97
    <36> LID_SW# GPIO25 * GPIO1E/XIOECS# WL_LED# <32> <26,28,30> PCM_PME#
    119 GPIO26 98 BATT_LOW_LED# <36>
    * GPIO1F/XIOFCS#
    2

    1 <36,37,43> SYSON 148 GPIO27 FANSPEED1 <4> <26,28,30> MINI_PME#


    C433 149 171
    <31,37,42,43,44> SUSP# GPIO28 GPIO2E/TOUT1/FANFB1
    155 12 1K_0402_5% 1 2 R106
    <37,45> VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3 <26,28,30> ONBD_LAN_PME#
    @ 10P_0402_50V8K 156 FANTEST_TP/GPIO05/FAN3PWM 11 1K_0402_5% 1 2 R356
    2 <25> PCMRST# GPIO2A
    162 0_0402_5% 1 2 R621 EAPD_KBC <32>
    GPIO2B
    <23> PWRBTN_OUT# 168 GPIO2D 175 EC_THRM# <23>
    Timer Pin TOUT2/GPIO2F PCI_PME#
    PADS_LED# 55 3
    <36> PADS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 PM_RSMRST# <23>
    CAPS_LED# 54 4 SHDD_LED#
    <36> CAPS_LED# CapLock#/GPIO011 * E51IT1/GPIO01 SHDD_LED# <25>
    NUM_LED# 23 106 E51_RXD
    <36> NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK
    reserved for GMCH R367 PHDD_LED# 41 107 E51_TXD
    <25> PHDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
    1 2 EC_RST# 19 MISC
    +3VALW ECRST#
    47K_0402_5% GATEA20 5 158 CRY1
    <22> GATEA20 GA20/GPIO02 XCLKI
    2 1 R C# 6 160 CRY2 R344 2 1
    <22> RC# KBRST#/GPIO03 XCLKO
    C439 31 @ 20M_0603_5%
    GND
    GND
    GND
    GND
    GND
    GND

    ECSCI#

    10P_0402_50V8K
    0.1U_0402_16V4Z 1 R340 2
    1 2 ENBKL 0_0402_5% 1 1
    <7> GMCH_ENBKL

    10P_0402_50V8K
    R115 0_0402_5% UMA@ KB910Q B4_LQFP176 C376 C364
    17
    35
    46
    122
    137
    167

    1
    OUT

    IN
    2 2

    NC

    NC
    4 4

    2
    Y2
    32.768KHZ_12.5P_1TJS125DJ2A073

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC KB910(LPC)
    Size Document Number R ev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Custom EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 34 of 47
    A B C D E
    1 2 USB_EN
    <37> SYSON#
    R342 0_0402_5%

    +USB_VCCA +3VALW +USB_VCCC +3VALW

    1
    R296 R599
    U27 U47 100K_0402_5%
    1 8 100K_0402_5% 1 8
    GND OUT GND OUT
    +5VALWP 2 IN OUT 7 +5VALWP 2 IN OUT 7

    2
    3 6 R295 R298 3 6 R598 R600
    USB_EN IN OUT OVCUR#2 <23> USB_EN IN OUT
    4 EN# FLG 5 1 2 1 2 OVCUR#3 <23> 4 EN# FLG 5 1 2 1 2 OVCUR#4 <23>
    1 1
    C309 G528_SO8 @ 0_0402_5% 47K_0402_5% C667 G528_SO8 @ 0_0402_5% 47K_0402_5%
    1 1
    4.7U_0805_10V4Z C307 4.7U_0805_10V4Z C668
    2 2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2
    Close to JP21
    Close to JP20

    USB CONN. 3
    USB CONN. 1 USB CONN. 2
    +USB_VCCA +USB_VCCA
    W=40mils W=40mils
    +USB_VCCA +USB_VCCB +USB_VCCC
    W=40mils
    1 1
    1 1 1 1 +USB_VCCC
    C296 + C277 C281 C276 C280 + C295 1
    150U_D2_6.3VM 1 1
    0.1U_0402_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z 150U_D2_6.3VM C257 + C258 C256
    2 2 2 2 2 2 150U_D2_6.3VM
    0.1U_0402_16V4Z 1000P_0402_50V7K
    JP5 2 2 2
    5 VCC VCC 1
    6 2 JP21
    <23> USB20P3- D1- D0- USB20P2- <23>
    <23> USB20P3+ 7 D1+ D0+ 3 USB20P2+ <23> 1
    8 VSS VSS 4 <23> USB20P4- 2
    C279
    1 1 C278 1 C13 1 C12 <23> USB20P4+ 3
    10P_0402_50V8K

    10P_0402_50V8K

    10P_0402_50V8K

    10P_0402_50V8K
    9 G1 G2 10 4
    11 G3 G4 12 1 C670 1 C669

    10P_0402_50V8K

    10P_0402_50V8K
    @ @ @ @ SUYIN_2569A-04G3T
    2 2 SUYIN_020122MR008S540ZU 2 2
    @ @
    2 2

    KBA[0..18]
    512kB Flash ROM <34> KBA[0..18]
    <34> ADB[0..7]
    ADB[0..7]

    +3VALW
    FD4 FD3 FD1 FD2 FD5 FD6

    1 2 C102
    0.1U_0402_16V4Z

    1
    U4

    KBA18 1 32 CF8 CF6 CF4 CF19 CF14 CF7 CF3 CF22 CF2 CF18 CF12 CF21 CF1
    KBA16 NC VCC FWE#
    2 A16 WE* 31 1 1 1 1 1 1 1 1 1 1 1 1 1
    KBA15 3 30 KBA17
    KBA12 A15 A17 KBA14
    4 A12 A14 29
    KBA7 5 28 KBA13
    KBA6 A7 A13 KBA8 CF9 CF20 CF5 CF17 CF11 CF15 CF10 CF16 CF13
    6 A6 A8 27
    KBA5 7 26 KBA9 1 1 1 1 1 1 1 1 1
    KBA4 A5 A9 KBA11
    8 A4 A11 25
    KBA3 9 24 FREAD#
    KBA2 A3 OE* KBA10 FREAD# <34>
    10 A2 A10 23
    KBA1 11 22 FSEL#
    KBA0 A1 CE* ADB7 FSEL# <34> H9 H8 H7 H16 H15 H19 H18 H20 H3 H17 H12
    12 A0 DQ7 21
    ADB0 13 20 ADB6 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D161 H_S315D161 H_S315D161
    ADB1 DQ0 DQ6 ADB5
    14 DQ1 DQ5 19
    ADB2 15 18 ADB4
    DQ2 DQ4 ADB3
    16 VSS DQ3 17
    1

    1
    29F040/SST39VF040_PLCC

    +3VALW H2 H5 H23 H6 H1 H4
    H_O126X157D126X157N H_C126D126N H_C126D126N H_O157X126D157X126N H_T236D161 H_T236D161
    20K_0402_5%
    1

    +3VALW
    1

    1
    R94
    SUS_STAT# <13,23>
    2

    +3VALW +3VALW Q31


    G
    14

    U9B 2N7002_SOT23
    New Screw Hole
    2

    4 1 3 H10 H11 H14 H13


    P

    A EC_FLASH# <23>
    1

    FWE# 6 H_C394D122 H_C394D122 H_C394D122 H_C394D122


    D

    O
    1 2 C356 R332
    B 5 H24 H25 H21 H22
    G

    0.1U_0402_16V4Z 10K_0402_5% H_O79X126D40X87 H_O79X126D40X87 H_S276D118 H_S276D118


    SN74LVC32APWLE_TSSOP14
    7

    U31
    2

    8 VCC A0 1 FWR# <34>

    1
    7 WP A1 2
    <34,39> EC_SMC_1 6 SCL A2 3
    <34,39> EC_SMD_1 5 SDA GND 4
    1

    AT24C16N-10SI-2.7_SO8
    R334 R326 Compal Electronics, Inc.
    1K_0402_5% 1K_0402_5% Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    BIOS/WL-SW/Screw Hole/USB
    2

    Size Document Number Rev


    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 35 of 47
    +3VALW
    LID Switch KSI[0..7]
    KSI[0..7] <34>

    ON/OFF BUTTON INT_KBD CONN.

    1
    KSO[0..15]
    +3VALW KSO[0..15] <34>
    R363

    100K_0402_5% DAN202U_SC70 for ON/OFF switch KEYBOARD CONN.

    1
    D19

    2
    2 SW1 R219 ACES_88172-3400
    <34> LID_SW#
    1 1 2 J-PB JOPEN 100K_0402_5%
    S4_LID_SW# 3 2 1 37 38

    1
    D11 34 NUM_LED#
    NUM_LED# <34>

    2
    2 ON/OFFBTN# PADS_LED#
    33
    ON/OFFBTN# <34> <34> PADS_LED#
    D5 ON /OFF 1 32 CAPS_LED#
    CAPS_LED# <34>
    V-PORT-0603-220 M-V05_0603 3 4 3 51_ON# 2 R226 1 31
    51_ON# <38> +3VS
    @ ESE11MV9_4P 300_0402_5% 30 KSO15
    +3VALW DAN202U_SC70 KSO14 29

    2
    28 KSO10
    KSO11 27

    1
    1 26 KSO8

    1
    R216 D10 KSO9 25
    4.7K_0402_5% Q12 RLZ20A_LL34 24 KSO13
    C231 KSI7 23
    2 0.01U_0402_16V7K KSO3

    DTC124EK_SC59
    22

    2
    1 R213 2 2 KSO7 21
    <34> EC_ON 0_0402_5% KSO12
    20
    KSI4 19
    18 KSI6
    KSI5 17

    3
    16 KSO6
    D

    1
    KSO5
    SW/LED Connector C613 0.1U_0402_16V4Z Q13 2
    15
    14 KSI3
    1 2 G KSI0 13
    JP15 @ 2N7002_SOT23 S WHEN R=0,Vbe=1.35V 12 KSO0

    3
    1 WHEN R=33K,Vbe=0.8V KSO1 11
    1 +5V KSI1
    2 2 MODE_LED# <34> 10
    3 KSI2 9
    3 DEV_LED# <34>
    4 PWR_LED# 8 KSO2
    4 PWR_SUSP_LED KSO4
    5 5 7
    6 EC_STOPBTN# 6 1 R214 2
    6 KSI1 <34> +3VS
    7 EC_PLAYBTN# 5 300_0402_5%
    7 KSI0 <34>
    8 EC_FRDBTN# 4
    8 KSI3 <34>
    9 EC_REVBTN# 3
    9 KSI2 <34> D9
    10 EC_UTXD/KSO17 R227 2
    10 KSO17 <34>
    11 11 3 51_ON# 1 2 +3VS 2 1 1
    12 MUL_KEY_ESD# 1 R233 0_0603_5% 300_0402_5% 35 36
    12 ON /OFF
    13 13 2 MUL_KEY# MUL_KEY# <34>
    14 JP17
    14 AO3402_SOT23
    ACES_85203-1402 DAN202U_SC70
    1 3

    S
    +5VALW +5V
    Q18
    @
    Touch Pad Connector 1
    C250

    G
    2
    ACES_85203-1202
    +5VS <37> SUSON 0.1U_0402_16V4Z
    24 24 12 12
    2
    23 23 11 11 TP_CLK <34>
    22 22 10 10 TP_DATA <34> 2 2 1PADS_LED# NUM_LED# 1 2
    21 9 C232 100P_0402_50V8J C329 C676 100P_0402_50V8J
    21 9 +5VS
    20 20 8 8 +5V 2 1 KSO14 CAPS_LED# 1 2
    19 7 0.1U_0402_16V4Z 100P_0402_50V8J C680 C685 100P_0402_50V8J
    19 7 +5VALW 1
    18 18 6 6 ACIN <22,34,38> 2 1 KSO11 KSO15 1 2
    17 5 PWR_LED# 100P_0402_50V8J C689 C694 100P_0402_50V8J
    17 5 POWER_LED# <34>
    16 4 PWR_SUSP_LED 2 1 KSO9 KSO10 1 2
    16 4 SUSP_LED <34>
    15 3 100P_0402_50V8J C672 C684 100P_0402_50V8J
    15 3 CHARGING_LED# <34>
    14 2 2 1 KSI7 KSO8 1 2
    14 2 BATT_LOW_LED# <34>
    13 1 100P_0402_50V8J C681 C693 100P_0402_50V8J
    13 1
    2 1 KSO7 KSO13 1 2
    JP16 100P_0402_50V8J C690 C677 100P_0402_50V8J
    2 1 KSI4 KSO3 1 2
    100P_0402_50V8J C673 C686 100P_0402_50V8J
    KSI5 KSO12 1
    Battery mode Hibernation 2
    100P_0402_50V8J
    2
    1
    C682
    1 KSO5 KSI6
    C695
    1
    2
    100P_0402_50V8J
    2
    RTCVREF 100P_0402_50V8J C691 C678 100P_0402_50V8J
    RTCVREF 2 1 KSI0 KSO6 1 2
    100P_0402_50V8J C674 C687 100P_0402_50V8J
    RTCVREF D14 2 1 KSO1 KSI3 1 2
    1

    1N4148_SOT23 100P_0402_50V8J C683 C696 100P_0402_50V8J


    680K_0402_5% C242 0.1U_0402_16V4Z 2 1 KSI2 KSO0 1 2
    1 2 ON /OFF 100P_0402_50V8J C692 C679 100P_0402_50V8J
    1

    2 1 KSO4 KSI1 1 2
    R218 R220 R225 100P_0402_50V8J C675 C688 100P_0402_50V8J
    KSO2 1 2
    5

    100K_0402_5% 100K_0402_5% U22 C697 100P_0402_50V8J


    D
    1
    P
    2

    1 2 2 4 1 2 2 Q16
    A Y R222 G 2N7002_SOT23
    D
    1

    C236 1U_0603_10V6K 10K_0402_5% S


    3

    S4_LID_SW# Q14 NC7SZ14M5X_SOT23-5


    2
    Power OK Circuit
    3

    G 2N7002_SOT23
    S
    3

    +3VS
    D
    1

    <34,37,43> SYSON 2 +3VALW +3VALW


    G

    1
    Q17 S
    3

    2N7002_SOT23 R212
    180K_0402_5% SN74LVC14APWLE_TSSOP14

    14

    14
    RTCVREF 1 2 1 2 U17C U17D
    R224 C246 1U_0603_10V4Z

    P
    2
    10K_0402_5% 5 6 9 8
    RTCVREF I O I O PM_POK <23>

    G
    R228 U23 0.1U_0402_16V4Z 1

    1
    1 2 1 CD1# VCC 14 1 2

    7
    10K_0402_5% 2 13 C247 C229 R188
    D1 CD2# 1U_0603_10V4Z 100K_0402_5%
    <34> S4_LATCH 3 CP1 D2 12
    2
    RTCVREF 1 2 4 SD1# CP2 11
    R229 1 5 10 SN74LVC14APWLE_TSSOP14
    Q1 SD2#

    2
    10K_0402_5% C248 6 09
    Q1# Q2
    7 GND Q2# 08
    1U_0805_25V4Z @
    2 74LCX74MTC_TSSOP14

    +3VALW 1 2 1
    R231 Q15
    D C233 Compal Electronics, Inc.
    1

    10K_0402_5% D15
    2 1 D_SET_S4 2 @ 220P_0402_50V7K Title
    <34> S4_DATA 2
    RB751V_SOD323
    G
    2N7002_SOT23 S THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    S4R,LID,PIO,SYS CONN
    3

    Size Document Number R ev


    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 36 of 47
    A B C D E

    +3VALW to +3V Transfer +5VALW to +5VS Transfer


    +5VALW +5VS
    +3VALW +3V
    U19
    U29 +12VALW 8 1
    1 +12VALW D S 1
    8 D S 1 7 D S 2
    7 D S 2 1 6 D S 3

    1
    1 1 6 D S 3 5 D G 4 1 1

    1
    C327 5 4 1 1 R618 C226 C214 R204
    R476 D G C323 C330 R318 100K_0402_5% SI4800DY_SO8 C218 470_0402_5%
    100K_0402_5% SI4800DY_SO8 470_0402_5% 2 10U_0805_10V4Z 10U_0805_10V4Z
    2 10U_0805_10V4Z 2
    0.1U_0402_16V4Z 2

    0.1U_0402_16V4Z

    10U_0805_10V4Z
    2 2

    1 2
    D
    2

    1 2
    5VS_ON
    SUSON D Q8
    <36> SUSON 2 SUSP +5VALW
    2 SYSON# D 1 2N7002_SOT23 G

    1
    1 G C700 S
    D Q30

    3
    1

    1
    C332 S Q29 SUSP 2 Q44

    3
    SYSON# 2 2N7002_SOT23 G 2N7002_SOT23 0.01U_0402_16V7K R211
    G 0.01U_0402_16V7K S 2 100K_0402_5%
    2

    3
    S 2N7002_SOT23
    3

    2
    SYSON#
    <35> SYSON#

    1
    SYSON 2 Q10
    <34,36,43> SYSON
    G 2N7002_SOT23
    S

    3
    +3VALW to +3VS Transfer +1.5VALW to +1.5VS Transfer
    2 2
    +5VALW
    +3VALW +3VS

    +1.5VALW +1.5VS

    1
    U40
    +12VALW 8 1 R210
    D S U3 100K_0402_5%
    7 D S 2
    1 6 D S 3 8 D S 1
    1

    1
    5 D G 4 1 1 7 D S 2

    2
    1
    R466 C525 R431 6 3 1 1
    100K_0402_5% SI4800DY_SO8 C506 C498 @ 470_0402_5% D S R33
    5 D G 4
    2 10U_0805_10V4Z 10U_0805_10V4Z C22 C23 @ 470_0402_5% SUSP
    2 2 <44> SUSP
    1 1 1 SI4800DY_SO8 22U_1206_16V4Z_V1
    2 2
    2

    1 2
    C21 C20 0.1U_0402_16V4Z
    D D

    1
    RUNON C19
    0.1U_0402_16V4Z 2 SUSP 10U_0805_10V4Z 10U_0805_10V4Z
    D <31,34,42,43,44> SUSP# 2 Q11
    2 2 2

    1
    1 G G 2N7002_SOT23
    D
    1

    C554 S Q36 Q28


    2 SUSP S
    3

    3
    SUSP 2 Q37 @ 2N7002_SOT23 10U_0805_10V4Z RUNON G @ 2N7002_SOT23
    G 2N7002_SOT23 0.1U_0402_16V4Z S
    2

    3
    S
    3

    +5VALW

    3 3

    2
    R208
    remove on integrated VGA sku
    10K_0402_5%

    +2.5V to +2.5VS Transfer

    1
    VR_ON#
    <44> VR_ON#
    D

    1
    2 Q9
    +2.5V +2.5VS <34,45> VR_ON G 2N7002_SOT23
    S

    3
    U6 M11@
    8 D S 1
    7 D S 2
    1 6 D S 3
    1

    5 D G 4 1 1
    C44 M11@ M11@ R51
    M11@ SI4800DY_SO8 C25 C26
    2 10U_0805_10V4Z @ 470_0402_5%
    2 2
    1 2

    10U_0805_10V4Z RUNON
    D
    0.1U_0402_16V4Z 2 SUSP
    G Q4
    S @ 2N7002_SOT23
    3

    4 4

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC/DC Interface
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 37 of 47
    A B C D E
    A B C D

    VS

    VIN VIN
    PL1 1 2
    PF1 FBM-L18-453215-900LMA90T_1812 PR1 1M_0402_1%

    1
    DC_IN_S1 1 2 DC_IN_S2 1 2
    VS

    1
    PR2
    PJP1 7A_24VDC_429007 PR3
    5.6K_0402_5%

    1
    1 1 84.5K_0402_1% 1 2 ACIN <22,34,36>

    2
    1

    1
    PC1 PR4

    8
    1000P_0402_50V7K PC2 PC3 PC4 PU1A 1K_0402_5%

    2
    3 G 2 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 3

    P
    2 +

    2
    4 G PR5 22K_0402_1% 1 PACIN
    1
    O PACIN <40,41> 1

    2 -

    G
    1

    1
    SINGA_2DC-G213-B04 PR6 LM393M_SO8 PD1

    4
    PC5 PC6 PR7
    1000P_0402_50V7K 20K_0402_1% 0.1U_0402_16V7K 10K_0402_5%

    2
    RLZ4.3B_LL34

    2
    PR8
    2 1
    Vin Detector
    RTCVREF
    10K_0402_5%
    VIN 3.3V High 18.384 17.901 17.430
    Low 17.728 17.257 16.976

    2
    PD2

    1N4148_SOD80

    1
    PD3
    BATT+ 2 1

    1
    RB751V_SOD323 PR9
    VS
    33_1206_5% 1 2
    PR10

    2
    1K_1206_5%
    CHGRTCP 1 2 N1 3 1
    PR11 PQ1
    200_0603_5% TP0610T_SOT23 PD4
    1

    2 1 N3 1 2
    VIN B+
    2
    1

    1
    2
    PR13 PR12 2

    PC7 PC8 1N4148_SOD80 1K_1206_5%


    100K_0402_5% 0.22U_1206_25V7M 0.1U_0603_25V7K
    2

    2
    2

    <36> 51_ON# 1 2 1 2
    PR14 22K_0402_5% PR15
    1K_1206_5%

    RTCVREF
    1

    PR16
    PU2

    1
    S-812C33AUA-C2N-T2_SOT89 200_0603_5% 1 2 2 1
    VL PR17 100K_0402_5% PR18 2.2M_0402_5% PR19
    3.3V
    2

    PR20 PR21 499K_0402_1%


    1 2 1 2 3 2 N2
    +CHGRTC OUT IN
    1

    2
    1

    8
    200_0603_5% 200_0603_5% PD5 PD6 PU1B
    GND
    1

    PC9 RLZ16B_LL34 2 5
    <39,41> MAINPWON

    P
    PC10 1U_0805_25V4Z +
    1 7 O
    1
    2

    10U_0805_10V4Z 3 6 2 PR22 1 VL
    <40> ACON -
    2

    1
    G
    LM393M_SO8

    1
    RB715F_SOT323 34K_0402_1% PR23

    4
    1

    1
    PC11
    PC13 PR24 499K_0402_1% 1000P_0402_50V7K

    2
    PC12 1000P_0402_50V7K 66.5K_0402_1% PR25

    2
    1000P_0402_50V7K 191K_0402_1%

    2
    PJ1 PJ2
    3 +3VALWP 2 2 1 1 +3VALW +1.8VSP 2 2 1 1 +1.8VS 3

    JUMP_43X118 JUMP_43X79
    (5A,200mils ,Via NO.= 10) (1A,40mils ,Via NO.= 2)
    D

    1
    PJ3
    +5VALWP 2 1 +5VALW PJ4 PQ2
    2 2 1 PACIN
    2 1 PR26
    2N7002_SOT23 47K_0402_5%
    JUMP_43X118
    +1.5VALWP 2 2 1 1 +1.5VALW Precharge detector S
    G

    3
    (5A,200mils ,Via NO.= 10) JUMP_43X118
    (3.5A,140mils ,Via NO.= 7)
    15.97V/14.84V FOR
    PJ5

    1
    2 1
    ADAPTOR PQ3
    +12VALWP 2 1 +12VALW
    DTC115EUA_SC70
    PJ6
    JUMP_43X39
    +1.25VSP 2 2 1 1 +1.25VS 2 +5VALWP
    (120mA,40mils ,Via NO.= 2)
    JUMP_43X118
    PJ7 (2A,80mils ,Via NO.= 4)
    +2.5VP 2 2 1 1 +2.5V

    3
    JUMP_43X118 PJ8
    PJ9 +1.35VSP 2 1 +1.35VS
    2 1
    2 2 1 1 JUMP_43X118
    JUMP_43X118 (2A,80mils ,Via NO.= 4)
    (8A,320mils ,Via NO.= 16)
    PJ10
    PJ11 +VGA_COREP 2 1 +VGA_CORE
    2 1
    +1.05VP 2 2 1 1 +VCCP
    JUMP_43X118
    4
    JUMP_43X118 4

    (3.5A,140mils ,Via NO.= 7) (5A,200mils ,Via NO.= 10)

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE DCIN & DETECTOR
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2461 0.3
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
    I NC. Date: 星期三, 八月 04, 2004 Sheet 38 of 47
    A B C D
    A B C D

    PH1 under CPU botten side :


    CPU thermal protection at 84 degree C
    Recovery at 45 degree C

    VMB VL VS VL
    1 1

    PF2 PL2
    PJP2 12A_65VDC_451012 FBM-L18-453215-900LMA90T_1812

    2
    BTC-07GR1 7P BATT_S1 1 2 1 2 BATT+
    1K_0402_5% PR27
    1

    1
    ALI/NIMH# 1 PR28 2
    2 AB/I PR29 2 PH1 PC14 47K_0402_1%
    3 1 +3VALWP MAINPWON <38,41>

    1
    TS_A 47K_0402_5% 0.1U_0603_25V7K
    4

    1
    EC_SMDA PC15 PC16 PR30
    5

    1
    EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7Z 10KB_0603_1%_TH11-3H103FT 1 2
    6

    2
    PR31 47K_0402_1% PQ4
    7

    8
    1K_0402_5% PR32 DTC115EUA_SC70
    1 2 3 PU3A PD7

    P
    +
    2

    16.9K_0402_1% 1 2 1 2
    O

    2
    2
    TM_REF1 2 -

    G
    PR33 PR34 1SS355_SOD323
    100_0402_5% 100_0402_5% LM393M_SO8

    4
    1

    3
    LI/NIMH# <34>
    1

    1
    PC17
    PR36
    PR35 PR37
    2 1 0.22U_0805_16V7K_V2 3.32K_0402_1% 2 1
    +3VALWP VL

    1
    100K_0402_1%
    PC18
    6.49K_0402_1%

    2
    1

    PR38 1000P_0402_50V7K

    1
    1K_0402_5%
    PR39
    2

    100K_0402_1%
    2 2

    2
    BATT_TEMP <34>

    EC_SMD_1 <34,35> PH2 near main Battery CONN :


    EC_SMC_1 <34,35> BAT. thermal protection at 79 degree C
    Recovery at 45 degree C

    VL VL

    2
    PH2 PR40
    47K_0402_1%
    10KB_0603_1%_TH11-3H103FT
    PR41

    1
    1 2
    47K_0402_1%
    3
    PR42 3

    8
    14.7K_0402_1% PU3B
    1 2 5 PD8

    P
    +
    O 7 2 1
    TM_REF1 6 -

    G
    1SS355_SOD323

    1
    PC19 PR43 LM393M_SO8

    4
    0.22U_0805_16V7K_V2 3.48K_0402_1%

    4 4

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE BATTERY CONN / OTP
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2461 0.3
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
    I NC. Date: 星期三, 八月 04, 2004 Sheet 39 of 47
    A B C D
    A B C D

    Iadp=0~2.87A B+ PQ5
    P2 P3 AO4407_SO8
    PQ6 PQ7 1 8
    2 7
    AO4407_SO8 AO4407_SO8 PR44 PL3 3 6
    8 1 1 8 2 1 FBM-L18-453215-900LMA90T_1812 5
    VIN
    7 2 2 7 1 2 B++
    6 3 3 6 0.02_2512_1%

    4
    5 5

    1
    PC20 PC21 PC22

    4
    4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

    2
    1 1

    1
    PR45
    1

    3
    PR46 PQ8 200K_0402_1%
    47K_0402_5% DTA144EUA_SC70 PR47
    47K

    2
    1
    1 2 VIN
    2 PC23 PU4 47K_0402_5%
    47K

    2
    0.1U_0603_25V7K 1 -INC2 24
    <34> ADP_I +INC2
    2

    3
    2
    1
    PR48
    PQ9 10K_0402_5%
    2 1 2 23 AO4407_SO8
    OUTC2 GND
    1

    PR49 100K_0402_5% PC24 N18 4 ACOFF#


    1

    1
    0.022U_0402_16V7K
    3 22 CS 1 2
    +INE2 CS

    1
    PQ10
    2 PC25

    1
    DTC115EUA_SC70 4 21 1 2
    -INE2 VCC(o)

    1
    0.1U_0402_16V7K PR50

    5
    6
    7
    8
    1
    PC27 PR52 0.1U_0603_25V7K 2
    D ACOFF <34>
    1

    PC26 PR51 33.2K_0402_1% 1 2 1 2 5 20


    FB2 OUT
    3

    2 PQ12 PR53 10K_0402_1% 10K_0402_5% PQ11

    2
    G 2N7002_SOT23 150K_0402_1% 4700P_0402_25V7K

    2
    S 6 19 1 2 LXCHRG DTC115EUA_SC70
    VREF VH
    3

    3
    PC28
    2

    1
    PC29 PC30 PR54 0.1U_0603_25V7K
    PD12 0.1U_0402_16V7K 1 2 1 2 7 18 1 2
    ACOFF#1 1K_0402_5% FB1 VCC PC31
    2
    CC=0.5~2.7A
    2
    1000P_0402_50V7K 0.1U_0603_25V7K
    1SS355_SOD323 8 -INE1 RT 17 1
    PR55
    2
    CV=16.8V(12 CELLS LI-ION)
    205K_0402_1% 68K_0402_5%
    D
    1

    <34> IREF 1 2 9 +INE1 -INE3 16 2

    PACIN 1 2 2 PQ13 PR56 PL4 PR58


    <38,41> PACIN
    PR57 G 2N7002_SOT23 PR60 PC32 1 2 1 2 BATT+
    3K_0402_1% S 2 1 10 15 1 2 1 2 16UH_D104C-919AS-160M_3.7A_20%
    OUTC1 FB3
    3

    1 PR59 10K_0402_5% 47K_0402_5% 0.02_2512_1%


    PR61 1500P_0402_50V7K 4.7U_1206_25V6K
    ACON PC33 11 14 ACON
    <38> ACON OUTD CTL

    1
    100K_0402_1% PD13 PC34 PC35 PC36
    2
    2

    0.1U_0402_16V7K 12 13 EC31QS04 4.7U_1206_25V6K 4.7U_1206_25V6K


    -INC1 +INC1

    2
    IREF=1.31*Icharge

    2
    MB3887_SSOP24
    IREF=0.73~3.3V

    +3VALWP
    CS
    PR62 PR63
    4.2V
    1

    2 1 2 1
    1

    PR64
    47K_0402_5% PQ14 95.3K_0603_0.1% 143K_0603_0.1%
    DTC115EUA_SC70
    PR65
    2

    2 2 1
    1

    95.3K_0603_0.1%
    PQ15
    DTC115EUA_SC70
    3

    3
    <34> FSTCHG 2 3
    VMB
    3

    PR66
    340K_0402_1%
    2

    OVP voltage : LI
    1

    4S2P : 17.4V--> BATT_OVP= 1.935V +12VALWP PR67


    499K_0402_1%
    (BAT_OVP=0.1111 *VMB)
    2
    8

    PU5A
    LM358A_SO8 3
    P

    +
    1 0
    <34> BATT_OVP 2
    -
    4 G
    1

    PR68
    1

    PR69 PC37

    2.2K_0402_5% 0.01U_0402_25V7Z
    2

    105K_0402_1%
    2

    4 4

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CHARGER
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2461 0.3
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
    I NC. Date: 星期三, 八月 04, 2004 Sheet 40 of 47
    A B C D
    5 4 3 2 1

    PC38
    N4 1 2

    1
    PD14
    4.7U_1206_25V6K

    2
    PC39
    B+++ 470P_0805_100V7K EC11FS2_SOD106

    1
    PJ17 1 2 PC40 BST31 BST51

    2
    2 1 0.1U_0603_25V7K SNB 2 1 FLYBACK
    D B+ 2 1 D
    PR70 22_1206_5%

    2
    JUMP_43X118 PT1

    8
    7
    6
    5
    1

    1 PC42 PQ16

    D
    D
    D
    D

    2
    PC41 SI4800DY-T1_SO8 PD15
    4.7U_1206_25V6K VS
    2

    4.7U_1206_25V6K DAP202U_SOT323 1 2 PC43 10uH_SDT-1205P-100-118_5A_20%

    3
    G
    S
    S
    S
    0.1U_0603_25V7K B+++

    1
    2
    3
    4

    1
    PD16 VL
    PLX3

    5
    6
    7
    8
    1SS355_SOD323 +12VALWP PQ17

    8
    7
    6
    5

    D
    D
    D
    D
    1

    1
    PQ18 SI4800DY-T1_SO8

    D
    D
    D
    D

    1
    SI4810DY_SO8 PC44 PC45

    1
    PC46 4.7U_1206_25V6K 4.7U_1206_25V6K

    2
    1

    G
    4.7U_0805_6.3V6K

    S
    S
    S
    PR71

    1
    G
    S
    S
    S
    PC47

    4
    3
    2
    1
    0.1U_0603_25V7K PC48 1.27K_0402_1%
    1
    2
    3
    4

    2
    1

    PC49 4.7U_1206_25V6K

    PDH3

    2
    1

    47P_0402_50V8J PDL3
    PL6 PDH5

    5
    6
    7
    8

    1
    10UH_D104C-919AS-100M_4.5A_20% PR72
    2

    2 1 PC50

    D
    D
    D
    D
    1.87K_0402_1% 47P_0402_50V8J
    2

    2
    22

    21
    2

    1
    PC51 PU6 PQ19

    1
    G
    S
    S
    S
    PR73 25 4 SI4810DY_SO8

    V+

    VL
    3.74K_0402_1% 0.47U_0603_16V7K BST3 12OUT PR74
    VDD 5
    2

    4
    3
    2
    1
    2

    PR76 27 DH3 BST5 18


    C 2M_0402_1% C
    DH5 16
    1

    1M_0402_1% 2 1 26 17 PLX5
    LX3 LX5

    2
    24 19 PDL5
    +3VALWP PR75 DL3 DL5
    0_0402_5% PGND 20
    1

    CSH5 14
    PR77 CSH3 1 13 CSH5
    CSL3 CSH3 CSL5
    2 1.24K_0402_1%
    1 2 CSL3 FB5 12

    1
    3 FB3 SEQ 15

    1
    1 3.32K_0402_1% 1 2 10 9 +2.5VREF PC52 PR79
    <38,40> PACIN SKIP# REF
    1

    470U_6.3V_M PD17 PR78 23 6 1.82K_0402_1%


    SHDN# SYNC
    1

    + PR80 10K_0402_5% 11 0.47U_0603_16V7K


    RST#

    2
    1
    PC54 7 TIME/ON5

    2
    PC53 SKUL30-02AT_SMA 100P_0402_50V8J PC55
    2
    2

    28 4.7U_0805_6.3V6K

    GND
    RUN/ON3 +5VALWP
    2

    2
    PR81
    1

    1
    MAX1902EAI_SSOP28

    1
    VS 1 2 PC56 PR82 1
    2

    1
    1000P_0402_50V7K PC57 470U_6.3V_M PD18
    2

    PR83 47K_0402_5% 10.2K_0402_1% 100P_0402_50V8J PC58 +

    2
    2
    1

    10K_0402_1% SKUL30-02AT_SMA
    PC59 2
    1

    2
    1
    @ 0.047U_0402_16V4Z
    2

    PR84

    2 1 VL
    PR85 10K_0402_1%

    2
    220K_0402_5%

    B B
    MAINPWON <38,39>
    1

    PC60
    0.47U_0603_16V7K
    2

    A A

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 5V/3.3V/12V
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2461 0.3
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
    I NC. Date: 星期三, 八月 04, 2004 Sheet 41 of 47
    5 4 3 2 1
    A B C D

    PL7
    FBM-L18-453215-900LMA90T_1812
    1 2 B+

    1
    PC61

    1
    4.7U_1206_25V6K PR86 PC62

    1
    4.7U_1206_25V6K
    0_1206_5% PC63

    2
    4.7U_1206_25V6K

    2
    1
    +5VALWP 1

    2
    PD19

    1
    DAP202U_SOT323 PC64 PR87 PC65

    2.2U_0805_10V6K

    2
    0.1U_0603_25V7K 2.2_0603_5%

    1
    2

    3
    8
    7
    6
    5
    +1.35V

    D
    D
    D
    D
    PQ20
    SI4800DY-T1_SO8

    14

    28
    +1.35VSP

    G
    S
    S
    S
    PL8 PC66 PU7 PC67

    5
    6
    7
    8
    3UH_SPC-07040-3R0_5A_30% 2 1 12 17 2 1

    VIN

    VCC
    0.01U_0402_25V7Z SOFT1 SOFT2

    1
    2
    3
    4
    0.01U_0402_25V7Z

    D
    D
    D
    D
    1 2 PHASE1
    PR88 PQ21
    1 2 1 1 2 6 23 1 2 2 1 SI4800DY-T1_SO8
    BOOT1 BOOT2

    8
    7
    6
    5

    G
    S
    S
    S
    PR89
    PC70 + PC68 0_0603_5% 0_0603_5% PC69 +1.5V

    D
    D
    D
    D

    4
    3
    2
    1
    0.1U_0402_16V7K 0.1U_0402_16V7K
    470U_6.3V_M 0.01U_0402_25V7Z PQ22 N9 5 24 N11 PL9 +1.5VALWP
    2 SI4800DY-T1_SO8 UGATE1 UGATE2 3UH_SPC-07040-3R0_5A_30%
    1

    G
    S
    S
    S
    PC71 4 25 PHASE2 1 2
    PHASE1 PHASE2
    1
    2
    3
    4
    PR90 PR92
    2

    5
    6
    7
    8
    2
    4.99K_0402_1% 2K_0402_1% 2

    1 PR91
    2 7 22 1 2 0.01U_0402_25V7Z

    D
    D
    D
    D
    ISEN1 ISEN2
    2

    2K_0402_1% PQ23 PC73 1


    N10 2 27
    LGATE1 LGATE2

    1
    SI4800DY-T1_SO8 PC72 +

    1
    G
    S
    S
    S
    470U_6.3V_M
    2

    4
    3
    2
    1

    2
    3 26 PR93
    PGND1 PGND2 N12 6.81K_0402_1%

    2
    PR94 9 VOUT1 VOUT2 20
    10 VSEN1 VSEN2 19
    SUSP# 1 2 8 21 1 PR95 2 +3VALWP
    <31,34,37,43,44> SUSP# EN1 EN2

    1
    15 PG1 PG2/REF 16
    1

    1
    10K_0402_1% PR96

    GND

    DDR
    PR97 0_0402_5% PC75
    11 OCSET1 OCSET2 18
    PC74 @ 0.1U_0402_16V7K 10K_0402_1%
    2

    2
    1
    10K_0402_1% ISL6225BCA-T_SSOP28

    13

    2
    1
    @ 0.1U_0402_16V7K
    2

    PR99 PR98
    71.5K_0402_1%
    71.5K_0402_1%

    2
    2

    3 3

    4 4

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 1.35V/1.5V
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2461 0.3
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
    I NC. Date: 星期三, 八月 04, 2004 Sheet 42 of 47
    A B C D
    5 4 3 2 1

    PR100
    PJ12
    1 2 2 2 1 1 +5VS

    2
    10_0603_5% JUMP_43X118

    1
    PC76 1
    PD20 PC78

    1
    1U_0603_6.3V6M 1N4148_SOD80 4.7U_1206_25V6K + PC77

    2
    2
    470U_6.3V_M

    1
    1
    PR101 PC79
    2

    2
    5
    6
    7
    8
    470P_0402_50V8J

    5
    6.81K_0402_1% PU8

    D
    D
    D
    D
    2
    0.1U_0402_16V7K

    VCC
    D D

    1
    PC80 PQ24
    1 SI4800DY-T1_SO8
    BOOT

    G
    S
    S
    S
    7 OCSET

    4
    3
    2
    1
    PL10
    PR102 2
    D UGATE

    1
    100K_0402_5% 1.8UH_D104C-919AS-1R8N_9.5A_20%
    VL 2 1 2 PQ25 6 2 1 +VGA_COREP
    G 2N7002_SOT23 FB
    S 8
    PHASE

    5
    6
    7
    8
    PR103 1
    D

    1
    0_0402_5%

    D
    D
    D
    D
    1 2 2 PQ27 + PC81
    <31,34,37,42,44> SUSP# 470U_6.3V_M
    G 2N7002_SOT23 3 4 PQ26
    GND LGATE SI4810DY_SO8
    S
    2
    3

    G
    S
    S
    S
    2

    APW7057KC-TR_SOP8

    4
    3
    2
    1
    PC82
    1

    @ 0.1U_0402_16V7K PR104
    5.36K_0402_1%
    1 2

    2
    PR105 PR106 PC84
    20.5K_0402_1% 20.5K_0402_1% 1 2
    PC83

    1
    @ 0.1U_0402_16V7K 0.1U_0402_16V7K

    1 1

    1
    PR143
    100K_0402_5% D
    VL 2 1 2 PQ28
    C G 2N7002_SOT23 C

    S
    3

    D
    1

    2 PQ43
    <13> POWER_SEL G 2N7002_SOT23
    S PR107
    3

    Low:1.2V PJ13
    High:1.0V 1 2 2 2 1 1 +5VALWP

    2
    10_0603_5% JUMP_43X118

    1
    PC85 1

    1
    PD21
    1U_0603_6.3V6M 1N4148_SOD80 PC86 + PC87

    2
    2

    4.7U_1206_25V6K 220U_6.3V_M

    2
    1
    PR108 PC88
    2

    5
    6
    7
    8
    470P_0402_50V8J

    5
    6.81K_0402_1% PU9 PC89 PQ29

    D
    D
    D
    D
    2

    0.1U_0402_16V7K SI4800DY-T1_SO8

    VCC
    1

    1
    BOOT 1

    G
    S
    S
    S
    7 OCSET

    4
    3
    2
    1
    PL11
    UGATE 2
    1.8UH_D104C-919AS-1R8N_9.5A_20%
    PR109 6 2 1 +2.5VP
    D FB
    1

    100K_0402_5%
    VL 2 1 2 PQ30 8
    PHASE

    5
    6
    7
    8
    G 2N7002_SOT23 1
    S

    D
    D
    D
    D
    3

    B + PC90 B
    3 4 PQ31 220U_6.3V_M
    GND LGATE SI4810DY_SO8
    2

    G
    S
    S
    S
    PR110
    D
    1

    0_0402_5% APW7057KC-TR_SOP8

    4
    3
    2
    1
    1 2 2 PQ32
    <34,36,37> SYSON
    G 2N7002_SOT23
    S
    3

    PR111
    2

    5.11K_0402_1%
    PC91 1 2
    1

    @ 0.1U_0402_16V7K
    2

    1 2
    PR112
    PC92
    2.4K_0402_1% 0.1U_0402_16V7K
    1

    A A

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 2.5V/VGA_CORE
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2461 0.3
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
    I NC. Date: 星期四, 八月 05, 2004 Sheet 43 of 47
    5 4 3 2 1
    5 4 3 2 1

    D
    PJ14 PU10 +1.8VSP D
    +2.5VP 2 2 1 1 2 VIN VO 3

    2
    JUMP_43X118 PC93 1 4 PC94
    EN ADJ 10U_1206_6.3V7K
    4.7U_0805_6.3V6K 5 7
    GND GND

    1
    6 GND GND 8
    +2.5VP
    G965-18P1U_SO8
    1 2
    4,37,42,43> SUSP#

    1
    PR113
    84.5K_0402_1% PJ15

    1
    1

    JUMP_43X118
    PC95
    0.1U_0402_16V7K

    2
    2

    2
    PU11
    1 VIN VCNTL 6 +3VALWP
    2 GND NC 5

    1
    1
    PC96 3 7 PC97
    10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M

    2
    PR114 4 8
    1.37K_0402_1% VOUT NC

    TP 9

    2
    APL5331KAC-TR_SO8
    PR115

    1
    C C
    D +1.05VP

    1
    0_0402_5% 2N7002_SOT23 PC98
    1 2 2 PQ33 0.1U_0402_16V7K

    2
    <37> VR_ON#

    1
    G PR116
    S 1K_0402_1% PC99

    3
    1
    10U_1206_6.3V7K

    2
    PC100
    +2.5V @ 0.1U_0402_16V7K

    2
    1

    PJ16
    1

    JUMP_43X118
    2 2

    PU12
    1 VIN VCNTL 6 +3VALWP
    2 GND NC 5
    1

    1
    1

    PC101 3 7 PC102
    10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M
    2

    PR117 4 8
    1K_0402_1% VOUT NC

    TP 9
    2

    APL5331KAC-TR_SO8
    B PR118 B

    D +1.25VSP
    1

    0_0402_5% PQ34
    1

    SUSP 1 2 2 2N7002_SOT23
    <37> SUSP
    1

    G PR119 PC103
    S 1K_0402_1% 0.1U_0402_16V7K PC104
    3

    2
    1

    10U_1206_6.3V7K
    2

    PC105
    @ 0.1U_0402_16V7K
    2

    A A

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 1.8V/1.25V/1.05V
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2461 0.3
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
    I NC. Date: 星期三, 八月 04, 2004 Sheet 44 of 47
    5 4 3 2 1
    CPU_B+ B+
    +5VS
    PL12

    1 2
    FBM-L18-453215-900LMA90T_1812
    PD22

    4.7U_1206_25V6K

    4.7U_1206_25V6K
    1

    1
    EP10QY03

    1
    PR120 + PC106
    10_0402_5% 220U_25V_M

    PC107

    PC108
    2 1
    2

    2
    2
    2
    PC109
    PC110

    0.01U_0402_25V7Z
    2
    1U_0603_6.3V6M 2.2U_0603_6.3V6K
    1

    5
    6
    7
    8
    PU13

    PC111
    PQ35

    0.22U_0603_16V7K

    D
    D
    D
    D
    1

    1
    AO4408_SO8

    2
    V CC

    PC112
    10 VCC VDD 30

    G
    S
    S
    S
    <5> CPU_VID0 24 D0 V+ 36

    4
    3
    2
    1
    <5> CPU_VID1 23 D1 BSTM 26 2PR121 1
    2.2_0603_5% +CPU_CORE
    22 28 N5 PL13
    <5> CPU_VID2 D2 DHM 0.56UH_ETQP4LR56WFC_21A_20% PR122
    21 27 CPUPHASE1 1 2 1 2
    <5> CPU_VID3 D3 LXM
    20 29 0.001_2512_5%
    <5> CPU_VID4 D4 DLM

    5
    6
    7
    8

    1
    CPU VCC SENSE

    AO4410_SO8
    19 31

    D
    D
    D
    D
    <5> CPU_VID5 D5 PGND

    PQ36

    909_0402_1%
    EC31QS04

    1
    PD23
    25 VROK CMP 37
    <7,12,23> VGATE

    499_0402_1%

    499_0402_1%
    1

    1
    G
    S
    S
    S
    4 S0 CMN 38 @

    1000P_0402_50V7K
    PR127

    PC113
    4
    3
    2
    1

    2
    0_0402_5% V CC 5 17
    S1 OAIN+

    2
    N6 PC114
    PR126

    PR123
    1 2 6 SHDN# OAIN- 16 1 2

    1
    PR128 30.1K_0402_1% 2.7K_0402_1%
    FB 0.47U_0603_16V7K

    PR124

    PR125
    VR_ON <34,37> 2 1 1 TIME FB 15

    1
    PR129 909_0402_1%
    PC1151 2 12 14 1 2 1 2
    CCV CCI PC116 470P_0402_50V8J @
    1 2 270P_0402_50V7K 2 35
    TON BSTS
    PR132 PR130 200K_0402_1% 1 2 8 33
    78.7K_0402_1% REF DHS
    1 2 PR131
    1 2 PC117 0.22U_0603_16V7K 9 34 2.7K_0402_1%
    ILIM LXS
    +5VS
    FB 1 2 7 32 1 2 1 2
    OFS DLS
    PR133 100K_0402_1%
    10.7K_0402_1%

    PC118 PR134
    100P_0402_50V8J

    3 SUS CSP 40
    2

    1 2 2200P_0402_50V7K 0_0402_5%
    PR135

    PC119

    18 SKIP CSN 39
    D
    2

    CPU_B+
    1

    2
    PQ37

    2.2_0603_5%
    PD24
    27P_0402_50V8J

    D 11 GND GNDS 13
    1

    PQ38 EP10QY03

    PR136
    <12,23> STP_CPU# 2
    1

    RHU002N06_SOT323
    PC120

    G 2
    S G RHU002N06_SOT323
    3

    MAX1532AETL_TQFN40

    4.7U_1206_25V6K

    4.7U_1206_25V6K
    S
    3

    D 5
    D 6
    D 7
    D 8

    1
    AO4408_SO8
    PR137

    PQ39
    0_0402_5%

    PC121

    PC122
    2

    2
    0.22U_0603_16V7K
    <23> PM_DPRSLPVR 1 2

    G
    S
    S
    S
    PC123
    +5VS 1 2

    4
    3
    2
    1
    PR138 N7 PL14
    2

    20K_0402_1%
    2

    PR139 0.56UH_ETQP4LR56WFC_21A_20%
    PR140 10K_0402_1% CPUPHASE2 1 2
    100K_0402_1%

    909_0402_1%
    1 1

    5
    6
    7
    8

    1
    D
    1

    1
    AO4410_SO8
    PQ41

    D
    D
    D
    D
    PQ40

    EC31QS04
    2
    RHU002N06_SOT323

    PD25
    G
    S
    3

    2
    1

    G
    S
    S
    S
    C @

    2
    <5> PSI# 2

    4
    3
    2
    1
    B

    PR141
    1 2
    E PQ42 N8
    3

    HMBT2222A_SOT23 PC124
    0.47U_0603_16V7K

    909_0402_1%
    1 2

    PR142

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY


    OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Compal Electronics, Inc.
    SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE Title
    CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS CPU_CORE
    AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
    THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY Size Document Number R ev
    THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, EAL20 LA-2461 0.3
    I NC.
    Date: 星期四, 八月 05, 2004 Sheet 45 of 47
    PWR PIR LIST
    EVT
    page Reason for change Modify list
    41 Improve design margin Change PD17,PD18 from SSM14 to SKUL30-02AT
    43 Change 2.5V,VGA_CORE OCP to 8A Change PR101,PR108 from 5.11K to 6.81K
    39 Improve design margin Change PF2 rating from 7A to 12A

    DVT
    43 Reverse POWER_SEL signal level Add PR143(100K),PQ43
    for HW request

    41 Adjust 3.3V OCP Change PR72 from 1.27K to 1.87K_0402_1%


    Change PR73 from 1.27K to 3.74K_0402_1%
    Change PR77 from 620 to 1.24K_0402_1%

    41 Adjust 5V OCP Change PR71 from 1.54K to 1.27K_0402_1%


    Change PR79 from 698 to 1.82K_0402_1%

    43 Change choke for design margen Change PL10,PL11 from 4.7UH to 1.8UH

    44 Add 1.8V delay time for HW Change PR113 from 0 to 84.5K_0402_1%


    Add 0.1U at PC95

    45 For EMI requirement Change PR121,PR136 from 0 to 2.2_0603_5%

    45 Adjust CPU_CORE voltage Change PR126,PR131 from 3K to 2.7K_0402_1%

    42 Modify 1.5V enable signal for HW request Change PR95 from 0 to 10K_0402_1%

    PVT
    43 Modify PL10 and PL11 Footprint
    38 Change DC-IN Jack as "SINGA_2DC-G213-B04_4P"
    41 Change PL5 as PJ17
    43 Raise VGA_CORE voltage to 1.21V for HW Change PR104 from 5.11K_0402_1% to 5.36K_0402_1%
    requirement
    45 Adjust CPU_CORE voltage
    Change PC118 from 0.022U to 2200P

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND EAL20 PIR LIST
    PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
    USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    B
    FortWorth Banias 0.3

    Date: 星期三, 八月 04, 2004 Sheet 46 of 47


    A B C D E

    EAL20 LA-2461 SCHEMATIC CHANGE LIST


    REVISION CHANGE: 0.1 TO 0.2 EAL20 LA-2461 SCHEMATIC CHANGE LIST
    REVISION CHANGE: 0.2 TO 0.3
    NO DATE PAGE MODIFICATION LIST PURPOSE NO DATE PAGE MODIFICATION LIST PURPOSE
    ----------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------
    1 6/23 P31 POP R521 CODEC CLOCK SOURCE FROM CLOCK GEN 1 7/15 P19 CHANGE R389,R393 BOM STUCTURE FROM UMA@ TO @ REMOVE IN UMA SKU
    2 6/23 P35 CHANGE R342.1 CONNECTION FROM SYSON TO SYSON# CHANGE USB POWER TO LOW ACTIVE 2 7/20 P16 RESERVE D2 SIZE CAP C701 ON +VGA_CORE PLANE ADD ONE MORE BULK CAP FOR VGA CORE
    3 6/23 P29 CHANGE R492.2 PULL HIGH FROM +3VS TO +VCC_5IN1 CHANGE PULL HIGH POWER 3 7/20 P28 ADD D12,R217,R438,R440,R443,R447,R448,R456,R458,R474 CHANGE BOM STRUCTURE TO CONTROL BOM
    4 6/23 P36 SWAP PIN OF JP16 CHANGE JP16 DIRECTION ,R495,R501 BOM STRUCTURE 5IN1@
    5 6/23 P12 RESERVE C671 ADD CAP TO CONTROL VGATE RISING TIME P29 ADD C518,C585,C592,C617,C618,R449,R455,R492,R494,R502
    4
    6 7/05 P12 CHANGE CLK_PCI_ICH CONNECT FROM U49.11 TO U49.7 CHANGE ICH PCI CLK SOURCE TO FREE RUN ,R520,R528,JP13,U44 BOM STRUCTURE 5IN1@ 4

    P12 ADD R524 BOM STRUCTURE 5IN1@


    CHANGE CLK_PCI_1394 CONNECT FROM U49.7 TO U49.11 CLOCK, TO SOLVE SYSTEM CAN NOT SHUTDOWN
    4 7/20 P31 NEW ADD R619 BETWEEN L_OUT_L AND AMP_LEFT ADD RES TO BYPASS MUX
    ISSUE NEW ADD R620 BETWEEN L_OUT_R AND AMP_RIGHT
    7 7/05 P29 CHANGE 5IN1 CONNECTOR FROM TAISOL TO TAITWAN CHANGE CONNECTOR VENDOR 5 7/20 P12 CHANGE R574 TO RESERVE CHANGE AC CODEC CLOCK SOURCE
    8 7/06 P29 DEL R251,R249 DEL 75OHM TERMINATION P31 CHANGE R527,R521 TO RESERVE
    P13 ADD R603,R604 ADD 75OHM TERMINATION CLOSE TO CHIP CHANGE X3,C610,C619 TO MOUNT
    P19 RESERVE R605,R606 RESERVE 75OHM TERMINATION CLOSE TO CHIP 6 7/20 P31 CHANGE U45.47 NET NAME FROM EAPD TO EAPD_CODEC USE KBC TO MUTE AMP
    9 7/06 P22 INSERT D29 BETWEEN GPI11 AND ACIN PREVENT SB LEAKAGE DURING DC-IN P34 NEW ADD R621 BETWEEN EAPD_KBC AND U35.11
    TO SOLVE POWER BOTTON NO FUNCTION ISSUE P32 ADD U9A, CONNECT U9A.1 TO EAPD_CODEC,U9A.2 TO EAPD_KBC
    10 7/06 P13 ADD R317 100K_0402_5% PULL DOWN POWER_SEL PREVENT SIGNAL FLOATING U9A.3 TO EAPD
    7 7/21 P34 RESERVE R622.2,R623.2,R624.2 PULL HIGH TO +3VALW ADD SKU ID FUNCTION FOR EC RECOGNIZES
    11 7/06 P29 CHANGE R528 CONNECTION FOR CUSTOMER REQUEST NEW ADD R625.2,R626.2,R627.2 PULL LOW TO GND
    12 7/06 P36 DEL CP1~CP6, ADD C329,C672~C697 FOR EMI REQUEST ADD SKU_ID0 CONNECT BETWEEN U35.93,R622.1,R625.1
    13 7/06 P36 CHANGE Q16.1 CONNECT TO ON/OFF TO CORRECT LID SW FUNCTION ADD SKU_ID1 CONNECT BETWEEN U35.94,R623.1,R626.1
    14 7/06 P20 CHANGE R294 FROM 0603 TO 0805,R19 FROM 0805 TO 1206 TO INCREASE RATING ADD SKU_ID2 CONNECT BETWEEN U35.75,R624.1,R627.1
    15 7/07 P31 RESERVE 1M_0402_5% R607~R614,HCT4066 U48 TO CONTROL POWER ON/OFF AUDIO CD PATH 8 7/26 P28 Modify "5IN1@ " to "5IN1@"
    RESERVE 10K_5%_0402 R615,0_0402_5% R617,RESERVE R616 ADD MUX SW CONTROL P29 Modify "5IN1@ " to "5IN1@"
    16 7/07 P12 ADD L35 BETWEEN +3VS AND +3VS_CLK FOR CUSTOMER REQUST P30 Modify "KS@ " to "KS@"
    17 7/08 P37 CHANGE C554 FROM 0.01U TO 0.1U CHANGE POWER ON SEQUENCE P33 Modify R157 remark from "FIR@" to "@"
    CHANGE U19.4 NET FROM RUNON TO 5VS_ON P21 Modify JP3 footprint from
    "SUYIN_030336FR004T115ZU_4P_EAL20" to
    ADD R618,Q44,C700, ADD 5VS_ON NET CONTROL +5VS CONTROL GATE "030336FR004T115ZU_4P_EAL20"
    3 18 7/09 P06 CHANGE R461 FROM 27.4 TO 37.4OHM CHANGE RESISTANCE FOR 855GME 9 7/29 P36 Shift SW/LED Connector signal up one pins, leave
    3

    19 7/09 P26 CHANGE C325 FROM 0.01U TO 0.1U,R292 FROM 5.9K TO 5.36K CHANGE R,C TO PASS LAN TEST JP15.11 as NC.
    20 7/09 P29 CHANGE CP2211 U18 FROM C1 TO D3 VERSION CHANGE FOR MATERIAL EOL P35 Add 3 screw hole, H23(H_C126D126N), H24 and H25
    (H_O79X126D40X87)
    H23 for M/B location Keeping.
    H24 and H25 for Double USB holding.
    10 7/31 P20 L5 and L4 change as 0_0805_5%
    P31 L9 and L11 change as 0_0603_5%, L26, L27 and L28
    change as 0_0805_5%
    P32 L29 and L30 change as 0_0805_5%, L26, L31, L32, L33 and
    L34 change as 0_0603_5%
    P28 SDCK_XDWE# saperate SD_CLK and XDWE#, add R628 for Some card can't detect because reflection
    XDWE#
    P29 R455.2 and JP13.36 SDCK_XDWE# change XDWE#.
    R450.1 and JP13.8 SDCK_XDWE# change SD_CLK.
    XXX Update schematic name from LA2641 to LA2461.
    11 8/02 P20 Add D30 for EMI ESD test fail.
    P32 L31, L32, L33 and L34 change as Bead.
    12 8/03 P04 Delete P@ on PU5B.
    12 8/04 P19 Update R396 and R397 as 75_0402_1%.
    P13 Update R603, R604 and R365 as 75_0402_1%.

    2 2

    1 1

    Compal Electronics, Inc.


    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PIR LIST
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    EAL20 LA-2461
    Date: 星期三, 八月 04, 2004 Sheet 47 of 47
    A B C D E

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