Arithmetic Building

Blocks

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 A Generic Digital Processor

MEM ORY
INPUT-OUTPUT

CONTROL

DATAPATH

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

Building Blocks for Digital Architectures

Arithmetic unit
- Bit-sliced datapath (adder , multiplier,
shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Bit-Sliced Design
Control

Bit 3

Data-Out
Multiplexer
Bit 2
Data-In

Register

Adder

Shifter
Bit 1
Bit 0

Tile identical processing elements

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Full-Adder
A B

Cin Full Cout

adder

Sum

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 The Binary Adder
A B

Cin Full Cout

adder

Sum

S = A  B  Ci

= ABC i + ABC i + ABCi + ABCi

C o = AB + BCi + ACi

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB
Propagate (P) = A  B
Delete = A B

Can also derive expressions for S and Co based on D

and P

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 The Ripple-Carry Adder

A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 C o,1 Co,2 Co,3

FA FA FA FA
(= C i,1)

S0 S1 S2 S3

Worst case delay linear with the number of bits

td = O(N)

t adder   N – 1  tcarry + tsum

Goal: Make the fastest possible carry path circuit

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

Complimentary Static CMOS Full Adder
VDD
VDD
Ci A B
A B
A
B
Ci B VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A

Co B

28 Transistors
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 Inversion Property
A B A B

Ci FA Co Ci FA Co

S S

S  A B C i  = S  A B  Ci 

C o  A B C i  = Co  A B  Ci 

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

Minimize Critical Path by Reducing Inverting Stages

Even Cell Odd Cell

A1 B1 A3 B3
A0 B0 A2 B2

Ci,0 C o,0 Co,1 C o,2 C o,3

FA’ FA’ FA’ FA’

S0 S2
S1 S3

Exploit Inversion Property

Note: need 2 different types of cells

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 The better structure: the Mirror Adder
VDD

VDD VDD A

A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A

24 transistors

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 The Mirror Adder
• The NMOS and PMOS chains are completely symmetrical. This guarantees
identical rising and falling transitions if the NMOS and PMOS devices are
properly sized. A maximum of two series transistors can be observed in the carry-
generation circuitry.
• When laying out the cell, the most critical issue is the minimization of the
capacitance at node Co. The reduction of the diffusion capacitances is particularly
important.
• The capacitance at node Co is composed of four diffusion capacitances, two
internal gate capacitances, and six gate capacitances in the connecting adder cell .
• The transistors connected to Ci are placed closest to the output.
• Only the transistors in the carry stage have to be optimized for optimal speed. All
transistors in the sum stage can be minimal size.

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Quasi-Clocked Adder
VDD
VDD
P
B B

Ci

B P
P
P S
A A Ci Ci
Co
VDD

P P
B
V DD
A
P P

Signal Setup Carry Generation Sum Generation

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 NMOS-Only Pass Transistor Logic
B B A CC A A

A
B
A
B

C A
C
A

Sum Sum Cout Cout

Transistor count (CPL) : 28
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 NP-CMOS Adder
VD D VDD
VDD VD D
  S1
 
Ci1
A1 B1 B1
A1 A1
B1 Ci1
A1
B1

  Ci2


VD D
VDD
VDD 


Ci1 B0
A0
A0 B0 Ci0 A0
A0 B0 B0
Ci0
S0
  
Ci0

Carry Path
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 NP-CMOS Adder

Co1

S1
A1
B1

S0
A0
B0

Ci0

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Manchester Carry Chain
VDD


P0 P1 P2 P3 P4

Ci,0
G0 G1 G2 G3 G4

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Sizing Manchester Carry Chain
Discharge Transistor
R1 R2 R3 R4 R5 R6 Out
1 2 3 4 5 6
MC M0 M1 M2 M3 M4
C1 C2 C3 C4 C5 C6

N
 i 
tp = 0.69  Ci   R j
i = 1 j = 1 
25 400

20 300
Speed

Area

15 200

10 100

51 01 1.52.0 2.5 3.0

1.5
2.0 2.5 3.0
k k
Speed (normalized by 0.69RC) Area (in minimum size devices)

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Carry-Bypass Adder

P0 G1 P0 G1 P2 G2 P3 G3

Ci,0 C o,0 C o ,1 Co,2 Co,3

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA

Multiplexer
Co,3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C 0, else “kill” or “generate”.
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 Manchester-Carry Implementation

P0 P1 P2 P3 BP
Ci,0 Co,3
G0 G1 G2 G3

BP

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Carry-Bypass Adder (cont.)

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

Carry Carry Carry Carry

C i,0 Propagation Propagation Propagation Propagation

Sum Sum Sum Sum

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

Carry Ripple versus Carry Bypass

tp
ripple adder

bypass adder

4..8
N

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Carry-Select Adder

Setup

P,G

"0" "0" Carry Propagation

"1" "1" Carry Propagation

Co,k-1 Multiplexer Co,k+3

Carry Vector

Sum Generation

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

Carry Select Adder: Critical Path
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"

"1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"

Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7 Co,11 Co,15

Sum Generation Sum Generation Sum Generation Sum Generation

S0-3 S4-7 S8-11 S12-15

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Linear Carry Select
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

(1)

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
(1)

"1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(5) (5) (5) (5) (5)
(6) (7) (8)
Multiplexer Multiplexer Multiplexer Multiplexer
Ci,0
(9)

Sum Generation Sum Generation Sum Generation Sum Generation

S0-3 S 4-7 S8-11 S 12-15 (10)

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Square Root Carry Select
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19

Setup Setup Setup Setup

(1)

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
(1)

"1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(3) (3) (4) (5) (6) (7)
(4) (5) (6) (7)
Multiplexer Multiplexer Multiplexer Multiplexer Mux
C i,0
(8)
Sum Generation Sum Generation Sum Generation Sum Generation Sum

S0-1 S2-4 S5-8 S9-13 S14-19 (9)

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Adder Delays - Comparison
50.0

ripple adder
40.0

30.0
tp

linear select

20.0

10.0 square root select

0.0
0.0 20.0 40.0 60.0
N

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 LookAhead - Basic Idea

A0 ,B 0 A1 ,B 1 AN-1 ,BN-1
...

Ci,0 P0 Ci,1 P1
Ci,N-1 PN-1

...

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Look-Ahead: Topology
VDD

G3

G2

G1

G0

Ci,0
Co,3

P0

P1

P2

P3

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Logarithmic Look-Ahead Adder

A0 F

A1 A2 A3 A4 A5 A6 A7

A0
tp N
A1

A2
A3
F
A4
A5

A6 tp log2(N)
A7

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Brent-Kung Adder
Co,0
(G0,P0) Co,2 Co,4
Co,1
(G1,P1 )

Co,3
(G2,P2 ) Co,5

(G3,P3 )

(G4,P4 ) Co,6
(G5,P5 )

(G6,P6 ) Co,7
(G7,P7 )

tadd  log2(N)
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 The Binary Multiplication
M+ N– 1
Z ··  Y
X Zk 2
k
= =

k=0
M – 1 N – 1 
 i j
=  Xi 2    Yj 2 
   
 i=0  j = 0 
M – 1 N – 1 
 i + j
=
 
  Xi Yj 2 

i =0 j= 0
 

with
M –1
i
X =
 Xi 2
i=0
N– 1
j
Y =
 Y j2
j= 0
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 The Binary Multiplication

1 0 1 0 1 0

 1 0 1 1

AND operation
1 0 1 0 1 0

1 0 1 0 1 0 Partial Products

0 0 0 0 0 0

+ 1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 The Array Multiplier

Z0
X3 X2 X1 X0 Y1

HA FA FA HA

X3 X2 X1 X0 Y2 Z1

FA FA FA HA

X3 X2 X1 X0 Y3 Z2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 The MxN Array Multiplier
— Critical Path

HA FA FA HA

FA FA FA HA Critical Path 1
Critical Path 2
Critical Path 1 & 2

FA FA FA HA

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Carry-Save Multiplier

HA HA HA HA

HA FA FA FA

HA FA FA FA

HA FA FA HA

Vector Merging Adder

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Adder Cells in Array Multiplier
P
VDD
VDD
A
Ci

A A P S
P
Ci
A
B B P
VDD
V DD
P A

P Co
Ci Ci

Ci
A

Identical Delays for Carry and Sum

Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 Multiplier Floorplan
X3 X2 X1 X0

Y0
Y1 HA Multiplier Cell
C S C S C S C S
Z0

FA Multiplier Cell
Y2
C S C S C S C S
Z1 Vector Merging Cell

Y3
C S C S C S C S X and Y signals are broadcasted
Z2 through the complete array.
( )

C C C C
S S S S

Z7 Z6 Z5 Z4 Z3
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 Wallace-Tree Multiplier
y0 y1
y2

y0 y1 y2 y3 y4 y5
Ci-1
FA

y3 FA FA
Ci Ci Ci-1
Ci-1
FA Ci Ci-1

y4
FA
Ci Ci-1 Ci Ci-1
FA

y5

Ci FA
FA

C S
C S
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 Multipliers —Summary
• Optimization Goals Different Vs Binary Adder

• Once Again: Identify Critical Path

• Other possible techniques

- Logarithmic versus Linear (Wallace Tree Mult)
- Data encoding (Booth)
- Pipelining
FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Design as a Trade-Off
80.0
static mirror look-ahead
manchester select
60.0 bypass
0.4

Area (mm2 )
static
t p (nsec)

40.0
select
bypass
0.2 mirror
look-ahead
20.0
manchester

0.0 0.0
0 10 20
N 0 10 20
N

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Layout Strategies for Bit-
Sliced Datapaths
(M1)
Wires
Control (M1)
Wires

GND

Signals Wires (M2)

Signals Wires (M2)

Well
VDD
Well

GND
GND VDD GND

Approach I — Approach II —
Signal and power lines parallel Signal and power lines perpendicular
Digital Integrated Circuits Arithmetic © Prentice Hall 1995
 Layout of Bit-sliced Datapaths

Digital Integrated Circuits Arithmetic © Prentice Hall 1995

 Layout of Bit-sliced Datapaths
(a) Datapath without feedthroughs (b) Adding feedthroughs (c) Equalizing the cell height reduces
and without pitch matching (area = 3.2 mm2) the area to 2.2 mm 2.
(area = 4.2 mm 2).

Digital Integrated Circuits Arithmetic © Prentice Hall 1995